On 4/9/21 7:56 PM, Radhey Shyam Pandey wrote:
Program IRQDelay for AXI DMA. The interrupt timeout mechanism causes
the DMA engine to generate an interrupt after the delay time period
has expired. It enables dmaengine to respond in real-time even though
interrupt coalescing is configured. It also
On 4/9/21 7:56 PM, Radhey Shyam Pandey wrote:
AXIDMA IP in SG mode sets completion bit to 1 when the transfer is
completed. Read this bit to move descriptor from active list to the
done list. This feature is needed when interrupt delay timeout and
IRQThreshold is enabled i.e Dly_IrqEn is triggere
On 4/9/21 7:56 PM, Radhey Shyam Pandey wrote:
Schedule tasklet with high priority to ensure that callback processing
is prioritized. It improves throughput for netdev dma clients.
Do you have specific numbers on the throughput improvement?
On 4/9/21 7:56 PM, Radhey Shyam Pandey wrote:
AXIDMA IP in SG mode sets completion bit to 1 when the transfer is
completed. Read this bit to move descriptor from active list to the
done list. This feature is needed when interrupt delay timeout and
IRQThreshold is enabled i.e Dly_IrqEn is triggere
On 4/9/21 7:55 PM, Radhey Shyam Pandey wrote:
Some background about the patch series: Xilinx Axi Ethernet device driver
(xilinx_axienet_main.c) currently has axi-dma code inside it. The goal
is to refactor axiethernet driver and use existing AXI DMA driver using
DMAEngine API.
This is pretty ne
, thanks.
Reviewed-by: Lars-Peter Clausen
On 4/6/21 8:28 PM, Puranjay Mohan wrote:
+
+static int tmp117_write_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *channel, int val,
+ int val2, long mask)
+{
+ struct tmp117_data *data = iio_priv(indio_dev);
+ s16 off;
+
+ switch (mask)
On 4/3/21 4:58 PM, Puranjay Mohan wrote:
On Fri, Apr 2, 2021 at 1:43 PM Lars-Peter Clausen wrote:
On 4/1/21 11:16 AM, Puranjay Mohan wrote:
TMP117 is a Digital temperature sensor with integrated NV memory.
Add support for tmp117 driver in iio subsystem.
Datasheet:-https://www.ti.com/lit/gpn
On 4/1/21 11:36 AM, Andy Shevchenko wrote:
[...]
+ case IIO_CHAN_INFO_SCALE:
+ /* Conversion from 10s of uC to mC
+* as IIO reports temperature in mC
+*/
+ *val = TMP117_RESOLUTION_10UC / 1;
+ *val2 = (TMP117_RES
On 4/1/21 11:16 AM, Puranjay Mohan wrote:
TMP117 is a Digital temperature sensor with integrated NV memory.
Add support for tmp117 driver in iio subsystem.
Datasheet:-https://www.ti.com/lit/gpn/tmp117
Signed-off-by: Puranjay Mohan
Nice and clean driver. Just some comments about the CALIBBIAS
On 3/28/21 11:46 PM, Lucas Stankus wrote:
Registers the device using the devm variant.
This is the final step of converting the ad7923 to only use devm routines,
meaning that the ad7923_remove() function is no longer needed to release
resources on device detach.
Signed-off-by: Lucas Stankus
H
ann
>
> Patch applied.
>
> Yours,
> Linus Walleij
I don't understand - I submitted a fix for this already in February
(reported by Gustavo). It took some time for you to get it ack'ed - but
you did (Feb 1st).
Did it end up getting dropped?
---Lars
--
Lars Povlsen,
Microchip
On 3/24/21 10:10 AM, Alexandru Ardelean wrote:
On Tue, Mar 23, 2021 at 1:35 PM Jonathan Cameron
wrote:
[..]
Continuing a bit with the original IIO buffer ioctl(), I talked to
Lars a bit over IRC.
And there was an idea/suggestion to maybe use a struct to pass more
information to the buffer
On 3/22/21 1:11 PM, Raviteja Narayanam wrote:
-Original Message-
From: Lars-Peter Clausen
Sent: Monday, March 22, 2021 5:22 PM
To: Raviteja Narayanam ; robh...@kernel.org;
ji...@kernel.org
Cc: Michal Simek ; pme...@pmeerw.net; linux-
i...@vger.kernel.org; devicet...@vger.kernel.org
On 3/22/21 12:43 PM, Lars-Peter Clausen wrote:
On 3/22/21 11:50 AM, Raviteja Narayanam wrote:
This driver supports software buffer mode and raw reads of ina260
iio channels.
In software buffer mode, a kthread will capture the active scan_elements
periodically using a delay. This can produce a
.
- Lars
---
MAINTAINERS | 8 +
drivers/iio/adc/Kconfig | 12 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/ina260-adc.c | 556 +++
4 files changed, 577 insertions(+)
create mode 100644 drivers/iio/adc/ina260-adc.c
diff
On 3/21/21 6:07 AM, Lars-Peter Clausen wrote:
On 3/20/21 7:45 AM, Puranjay Mohan wrote:
TMP117 is a Digital temperature sensor with integrated NV memory.
Add support for tmp117 driver in iio subsystem.
Datasheet:-https://www.ti.com/lit/gpn/tmp117
Signed-off-by: Puranjay Mohan
This looks
On 3/20/21 7:45 AM, Puranjay Mohan wrote:
TMP117 is a Digital temperature sensor with integrated NV memory.
Add support for tmp117 driver in iio subsystem.
Datasheet:-https://www.ti.com/lit/gpn/tmp117
Signed-off-by: Puranjay Mohan
This looks good to me. Just two small bits I overlooked duri
On 3/19/21 9:30 PM, Puranjay Mohan wrote:
TMP117 is a Digital temperature sensor with integrated NV memory.
Add support for tmp117 driver in iio subsystem.
Datasheet:-https://www.ti.com/lit/gpn/tmp117
Signed-off-by: Puranjay Mohan
Hi,
Thanks for the patch, this looks really good. I have a
On 3/18/21 9:27 AM, Lars-Peter Clausen wrote:
On 3/18/21 9:07 AM, Pavel Andrianov wrote:
Hi,
berlin2_adc_probe [1] registers two interrupt handlers:
berlin2_adc_irq [2]
and berlin2_adc_tsen_irq [3]. The interrupt handlers operate with the
same data, for example, modify
priv->data w
s correctly those two
interrupts will never fire at the same time.
Now, if the hardware misbehaves the two interrupts could still fire at
the same time.
- Lars
red
data will be never used.
Hi,
This looks good!
Reviewed-by: Lars-Peter Clausen
One thing process wise. I know it is tempting to send version 2 as a
reply to version 1, but this way it is also easy for the messages to get
lost in longer threads. At least for the IIO mailinglist we h
On 3/12/21 7:22 PM, Pierre-Louis Bossart wrote:
Cppcheck warning:
sound/soc/codecs/ad1836.c:311:9: warning: Identical condition and return
expression 'ret', return value is always 0 [identicalConditionAfterEarlyExit]
return ret;
^
sound/soc/codecs/ad1836.c:308:6: note: If condition '
On 3/10/21 8:16 AM, Alexandru Ardelean wrote:
On Mon, 8 Mar 2021 at 18:42, Lars-Peter Clausen wrote:
On 3/8/21 3:54 PM, Alexandru Ardelean wrote:
The 'delay_usecs' field was handled for backwards compatibility in case
there were some users that still configured SPI delay transfers
On 3/8/21 3:54 PM, Alexandru Ardelean wrote:
The 'delay_usecs' field was handled for backwards compatibility in case
there were some users that still configured SPI delay transfers with
this field.
They should all be removed by now.
Signed-off-by: Alexandru Ardelean
---
drivers/spi/spi-axi-s
On 3/7/21 1:36 PM, Jonathan Cameron wrote:
On Sat, 6 Mar 2021 18:47:10 +0200
Alexandru Ardelean wrote:
Thanks to Lars for finding this.
The free of the 'attached_buffers' array should be done as late as
possible. This change moves it to iio_buffers_put(), which looks like
the best
On 2/28/21 3:34 PM, Jonathan Cameron wrote:
On Sun, 28 Feb 2021 09:51:38 +0100
Lars-Peter Clausen wrote:
On 2/15/21 11:40 AM, Alexandru Ardelean wrote:
With this change, an ioctl() call is added to open a character device for a
buffer. The ioctl() number is 'i' 0x91, which f
On 2/15/21 11:40 AM, Alexandru Ardelean wrote:
With this change, an ioctl() call is added to open a character device for a
buffer. The ioctl() number is 'i' 0x91, which follows the
IIO_GET_EVENT_FD_IOCTL ioctl.
The ioctl() will return an FD for the requested buffer index. The indexes
are the sam
On 2/15/21 11:40 AM, Alexandru Ardelean wrote:
static ssize_t iio_show_scan_index(struct device *dev,
struct device_attribute *attr,
char *buf)
@@ -1451,11 +1465,13 @@ static void __iio_buffer_free_sysfs_and_mask(struct
iio_
On 2/15/21 11:40 AM, Alexandru Ardelean wrote:
+int devm_iio_kfifo_buffer_setup(struct device *dev,
+ struct iio_dev *indio_dev,
+ int mode_flags,
+ const struct iio_buffer_setup_ops *setup_ops)
+{
+ s
On 2/15/21 11:40 AM, Alexandru Ardelean wrote:
[...]
/**
* iio_buffer_wakeup_poll - Wakes up the buffer waitqueue
* @indio_dev: The IIO device
@@ -1343,6 +1371,96 @@ static void
iio_buffer_unregister_legacy_sysfs_groups(struct iio_dev *indio_dev)
kfree(iio_dev_opaque->legacy_scan
fin PWM trigger[1] back in the day to support this. The
bfin PWM trigger driver essentially implements what I'm describing
above, but without using the PWM framework.
- Lars
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/staging/iio/trigger/iio-trig-bfin-timer.c?h=v3.15
- Lars
Geert Uytterhoeven writes:
> Hi Alexandre,
>
> On Wed, Feb 10, 2021 at 3:17 PM Alexandre Belloni
> wrote:
>> On 10/02/2021 14:53:01+0100, Geert Uytterhoeven wrote:
>> > On Wed, Feb 10, 2021 at 2:45 PM Lars Povlsen
>> > wrote:
>> > > Geert Uytte
> select GENERIC_PINCONF
Geert,
Thank you for your patch. Unfortunately, it makes it impossible to use
the driver across PCIe - which is a specifically desired configuration.
Could you add CONFIG_PCI to the || chain?
Cheers,
--
Lars Povlsen,
Microchip
This patch fixes using a wrong register offset when configuring an IRQ
trigger type.
Fixes: be2dc859abd4 ("pinctrl: pinctrl-microchip-sgpio: Add irq support (for
sparx5)")
Reported-by: Gustavo A. R. Silva
Signed-off-by: Lars Povlsen
---
drivers/pinctrl/pinctrl-microchip-sgpio.c | 2
BIT(addr.port), (!!(type & 0x2)) << addr.port);
>
> REG_INT_TRIGGER + SGPIO_MAX_BITS turns out to be 10, which is outside the
> boundaries
> of priv->properties->regoff[] at line 154:
Hi Gustavo!
Thanks for spotting this - the "+" is misplaced. I will submit a patch
On 2/2/21 10:55 PM, Rob Herring wrote:
The example and filename use 'adi,ad5686', but the schema doesn't
document it. The AD5686 is also a SPI interface variant while all the
documented variants have an I2C interface. So let's update all the
references to AD5686 to AD5
with a SPI interface and one
with a I2C interface. This binding document only describes the I2C
variants. But the ad5686 is a SPI variant.
I think this is a typo and we should replace ad5686 with ad5696,
including the document name.
Cc: Lars-Peter Clausen
Cc: Michael Hennerich
Cc: Jo
On 1/11/21 10:32 AM, Michal Simek wrote:
Hi Lars,
On 10. 01. 21 16:43, Lars-Peter Clausen wrote:
On 1/10/21 4:16 PM, Paul Thomas wrote:
On Fri, Jan 8, 2021 at 1:36 PM Radhey Shyam Pandey
wrote:
-Original Message-
From: Paul Thomas
Sent: Friday, January 8, 2021 9:27 PM
To: Radhey
ne channel that channel was always at index 0.
Regardless of whether the channel was RX or TX. But after that change
the RX channel is always at offset 1, regardless of whether the DMA has
one or two channels. This is a breakage in ABI.
If you have the choice I'd recommend to not use the Xilinx DMA, it gets
broken pretty much every other release.
- Lars
is not working, can you clarify that a bit? Is no sound
card registered? Is it registered but output stays silent?
- Lars
[1] https://www.alsa-project.org/wiki/AlsaInfo
<https://www.alsa-project.org/wiki/AlsaInfo>
On 12/30/20 2:41 PM, Jonathan Cameron wrote:
On Thu, 24 Dec 2020 03:19:21 +
Jyoti Bhayana wrote:
+ /*
+* The seconds field in the sensor interval in SCMI is 16 bits long
+* Therefore seconds = 1/Hz <= 0x. As floating point calculations
are
+* discouraged
, if this will work, it is
>> probably a better solution.
>>
>
> That was my suggestion. Then you can ensure from the reset controller
> driver that this is done exactly once, either from the sgpio driver or
> from the switchdev driver. IIRC, the sgpio from the other SoCs a
Andrew Lunn writes:
> On Tue, Dec 22, 2020 at 11:09:41AM +0100, Lars Povlsen wrote:
>>
>> Andrew Lunn writes:
>>
>> > On Fri, Nov 13, 2020 at 03:51:51PM +0100, Lars Povlsen wrote:
>> >> + led@8 {
>> >> + la
tch.
>> - STP state, VLAN support, host/bridge port mode, Forwarding DB, and
>> configuration and statistics via ethtool.
>>
>> More support will be added at a later stage.
>>
>> The Sparx5 Switch chip register model can be browsed here:
>> Link: https://microchip-ung.github.io/sparx-5_reginfo/reginfo_sparx-5.html
>
> Out of curiosity, what tool was used to generate the register
> information page? It looks really neat and well organized.
Florian,
It is an in-house tool. The input data is in a proprietary XML-like
format.
We're pleased that you like it, we do too. We are also pleased that
being a Microchip entity, we can actually make this kind of information
public.
I'll pass your praise on.
---Lars
--
Lars Povlsen,
Microchip
Andrew Lunn writes:
> On Fri, Nov 13, 2020 at 03:51:51PM +0100, Lars Povlsen wrote:
>> + led@8 {
>> + label = "eth12:green";
>> + gpios = <&sgpio_out0 12 0 GPIO_ACTIVE_HIGH>;
>
On 12/17/20 4:18 PM, Takashi Iwai wrote:
On Thu, 17 Dec 2020 15:57:02 +0100,
Lars-Peter Clausen wrote:
On 12/17/20 3:24 PM, Takashi Iwai wrote:
On Thu, 17 Dec 2020 14:16:48 +0100,
Lars-Peter Clausen wrote:
On 12/17/20 12:06 PM, Takashi Iwai wrote:
On Thu, 17 Dec 2020 11:59:23 +0100,
Lars
On 12/17/20 3:24 PM, Takashi Iwai wrote:
On Thu, 17 Dec 2020 14:16:48 +0100,
Lars-Peter Clausen wrote:
On 12/17/20 12:06 PM, Takashi Iwai wrote:
On Thu, 17 Dec 2020 11:59:23 +0100,
Lars-Peter Clausen wrote:
On 12/17/20 10:55 AM, Takashi Iwai wrote:
On Thu, 17 Dec 2020 10:43:45 +0100,
Lars
On 12/17/20 12:06 PM, Takashi Iwai wrote:
On Thu, 17 Dec 2020 11:59:23 +0100,
Lars-Peter Clausen wrote:
On 12/17/20 10:55 AM, Takashi Iwai wrote:
On Thu, 17 Dec 2020 10:43:45 +0100,
Lars-Peter Clausen wrote:
On 12/17/20 5:15 PM, Robin Gong wrote:
Since mmap for userspace is based on page
On 12/17/20 10:55 AM, Takashi Iwai wrote:
On Thu, 17 Dec 2020 10:43:45 +0100,
Lars-Peter Clausen wrote:
On 12/17/20 5:15 PM, Robin Gong wrote:
Since mmap for userspace is based on page alignment, add page alignment
for iram alloc from pool, otherwise, some good data located in the same
page of
On 12/17/20 11:14 AM, Takashi Iwai wrote:
On Thu, 17 Dec 2020 10:55:42 +0100,
Takashi Iwai wrote:
On Thu, 17 Dec 2020 10:43:45 +0100,
Lars-Peter Clausen wrote:
On 12/17/20 5:15 PM, Robin Gong wrote:
Since mmap for userspace is based on page alignment, add page alignment
for iram alloc from
On 12/17/20 5:15 PM, Robin Gong wrote:
Since mmap for userspace is based on page alignment, add page alignment
for iram alloc from pool, otherwise, some good data located in the same
page of dmab->area maybe touched wrongly by userspace like pulseaudio.
I wonder, do we also have to align size to
On 12/16/20 9:23 AM, Mircea Caprioru wrote:
[...]
Changelog v2
- fix conflict with ADS7868 device in chip_info_tbl
[...]
[ID_ADS7868] = {
.channel[0] = ADS786X_CHAN(8),
.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
Hi Mircea,
I think this is still missing a
On Tue, Dec 08, 2020 at 01:46:09PM -0800, Jay Vosburgh wrote:
>
> Jakub Kicinski wrote:
>
> >On Wed, 02 Dec 2020 20:55:57 + Lars Everbrand wrote:
> Are these bandwidth numbers from observation of the actual
> behavior? I'm not sure the real system
On Sat, Dec 05, 2020 at 11:45:13AM -0800, Jakub Kicinski wrote:
> Thanks for the patch!
Kind words for my first attempt at this. Sorry for answering a bit late,
proton-bridge is not my best friend lately.
>
> Looking at the code in question it feels a little like we're breaking
> abstractions if w
.
Signed-off-by: Lars Povlsen
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 3bb4755e9f87..044063a9beae 100644
--- a/arch/arm64
This describe the new bindings for the added IRQ support in the
pinctrl-microchip-sgpio driver.
Signed-off-by: Lars Povlsen
---
.../bindings/pinctrl/microchip,sparx5-sgpio.yaml | 16
1 file changed, 16 insertions(+)
diff --git
a/Documentation/devicetree/bindings/pinctrl
This adds 'interrupt-controller' features for the signals available on
the Microchip SGPIO controller, however only for controller versions
on the Sparx5 platform (or later).
Signed-off-by: Lars Povlsen
---
drivers/pinctrl/pinctrl-microchip-sgpio.c | 187 +-
1 fi
This adds 'interrupt-controller' features for the signals available on
the Microchip SGPIO controller.
Due to hardware limitations this feature is limited to Sparx5 platform
(or later).
Lars Povlsen (3):
pinctrl: pinctrl-microchip-sgpio: Add irq support (for sparx5)
dt-binding
33 + 0 + 0 + 100 + 33 + 33).
Signed-off-by: Lars Everbrand
---
drivers/net/bonding/bond_main.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c
index e0880a3840d7..e02d9c6d40ee 100644
--- a/drivers/net/bonding/bond_main.c
+++ b/d
x5_mc_unsync);
>> +
>> + return 0;
>> +}
>
> This looks suspiciously empty? Don't you need to tell the hardware
> which ports this port is bridges to? Normally you see some code which
> walks all the ports and finds those in the same bridge, and sets a bit
> which allows these ports to talk to each other. Is that code somewhere
> else?
>
This is applied when the STP state is handled - sparx5_update_fwd().
This is pretty much as in the ocelot driver, which can a somewhat
similar switch - and driver - architecture.
> Andrew
Thank you for your comments,
---Lars
--
Lars Povlsen,
Microchip
The pinctrl-microchip-sgpio driver needs OF support, so add that to
Kconfig.
Reported-by: Randy Dunlap
Signed-off-by: Lars Povlsen
---
drivers/pinctrl/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 9b8ed7516355
On 11/24/20 9:22 AM, Alexandru Ardelean wrote:
error = devm_add_action_or_reset(&client->dev, adp5589_clear_config,
@@ -1078,6 +1098,13 @@ static int __maybe_unused adp5589_resume(struct device
*dev)
static SIMPLE_DEV_PM_OPS(adp5589_dev_pm_ops, adp5589_suspend, adp5589_resume);
+
Linus Walleij writes:
> On Fri, Nov 13, 2020 at 3:52 PM Lars Povlsen
> wrote:
>
>> The series add support for the serial GPIO controller used by
>> Microchip Sparx5, as well as (MSCC) ocelot/jaguar2 SoCs.
>>
>> v10 changes - anniversary edition (from An
Linus Walleij writes:
> On Fri, Nov 13, 2020 at 3:52 PM Lars Povlsen
> wrote:
>
>> This adds SGPIO devices for the Sparx5 SoC and configures it for the
>> applicable reference boards.
>>
>> Signed-off-by: Lars Povlsen
>
> Reviewed-by: Linus Walleij
&
memory operations support)
Signed-off-by: Lars Povlsen
---
drivers/spi/spi-dw-core.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
index 2e50cc0a9291..a0794eac2094 100644
--- a/drivers/spi/spi-dw-core.c
+++ b/drivers/spi
s used. I believe for
example V4L2 uses this.
- Lars
On Thu, Nov 12, 2020 at 01:29:31PM +, Sang, Oliver wrote:
>
>
> > -Original Message-
> > From: Lars Poeschel
> > Sent: Monday, November 9, 2020 8:40 PM
> > To: Sang, Oliver
> > Cc: Miguel Ojeda ; lkp ; Willy Tarreau
> > ; LKML ; Linux Memo
This adds SGPIO devices for the Sparx5 SoC and configures it for the
applicable reference boards.
Signed-off-by: Lars Povlsen
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 91 ++
.../boot/dts/microchip/sparx5_pcb125.dts | 5 +
.../dts/microchip/sparx5_pcb134_board.dtsi
This adds DT bindings for the Microsemi/Microchip SGPIO controller,
bindings microchip,sparx5-sgpio, mscc,ocelot-sgpio and
mscc,luton-sgpio.
Signed-off-by: Lars Povlsen
Reviewed-by: Rob Herring
---
.../pinctrl/microchip,sparx5-sgpio.yaml | 145 ++
1 file changed, 145
This adds a pinctrl driver for the Microsemi/Microchip Serial GPIO
(SGPIO) device used in various SoC's.
The driver is added as a pinctrl driver, albeit only having just GPIO
support currently. The hardware supports other functions that will be
added following.
Signed-off-by: Lars Po
both in and output modes.
- Use direct adressing of the individual banks (#gpio-cells = <4>),
also osoleting need for addressing macros in bindings include file.
- Property 'microchip,sgpio-ports' (uint32, bitmask) replaced by
proper range set (array of [start,end]) 'microchip,s
Andy Shevchenko writes:
> On Wed, Nov 11, 2020 at 2:25 PM Lars Povlsen
> wrote:
>>
>> This adds a pinctrl driver for the Microsemi/Microchip Serial GPIO
>> (SGPIO) device used in various SoC's.
>>
>> The driver is added as a pinctrl driver, albeit o
On 11/12/20 11:14 AM, Alexandru Ardelean wrote:
On Thu, Nov 12, 2020 at 11:55 AM Lars-Peter Clausen wrote:
On 11/12/20 10:10 AM, Alexandru Ardelean wrote:
From: Lars-Peter Clausen
Use a heap allocated memory for the SPI transfer buffer. Using stack memory
can corrupt stack memory when using
On 11/12/20 10:10 AM, Alexandru Ardelean wrote:
From: Lars-Peter Clausen
Use a heap allocated memory for the SPI transfer buffer. Using stack memory
can corrupt stack memory when using DMA on some systems.
This change adds 4 bytes at the end of the current DMA buffer, which will
be used by
This adds SGPIO devices for the Sparx5 SoC and configures it for the
applicable reference boards.
Signed-off-by: Lars Povlsen
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 91 ++
.../boot/dts/microchip/sparx5_pcb125.dts | 5 +
.../dts/microchip/sparx5_pcb134_board.dtsi
This adds a pinctrl driver for the Microsemi/Microchip Serial GPIO
(SGPIO) device used in various SoC's.
The driver is added as a pinctrl driver, albeit only having just GPIO
support currently. The hardware supports other functions that will be
added following.
Signed-off-by: Lars Po
This adds DT bindings for the Microsemi/Microchip SGPIO controller,
bindings microchip,sparx5-sgpio, mscc,ocelot-sgpio and
mscc,luton-sgpio.
Signed-off-by: Lars Povlsen
Reviewed-by: Rob Herring
---
.../pinctrl/microchip,sparx5-sgpio.yaml | 145 ++
1 file changed, 145
s:
- Adds both in and output modes.
- Use direct adressing of the individual banks (#gpio-cells = <4>),
also osoleting need for addressing macros in bindings include file.
- Property 'microchip,sgpio-ports' (uint32, bitmask) replaced by
proper range set (array of [start,end]) &#
Andy Shevchenko writes:
> On Wed, Nov 11, 2020 at 10:52 AM Lars Povlsen
> wrote:
>> Andy Shevchenko writes:
>> > On Tue, Nov 10, 2020 at 5:51 PM Lars Povlsen
>> > wrote:
>> >> > On Mon, Nov 9, 2020 at 3:27 PM Lars Povlsen
>> >> >
Andy Shevchenko writes:
> On Tue, Nov 10, 2020 at 5:51 PM Lars Povlsen
> wrote:
>> > On Mon, Nov 9, 2020 at 3:27 PM Lars Povlsen
>> > wrote:
>
>> >> This adds a pinctrl driver for the Microsemi/Microchip Serial GPIO
>> >> (SGPIO) device
he
>> kernel too?
>
> If you think we have to print a message on each possible error case
> (but not always the one) we will get lost in the messages disaster and
> dmesg overflow.
> It is consumer who should decide if the setting is critical or not to
> be printed to user.
I think the message is a valid one. I will change it to
dev_err_ratelimited() - that should prevent the dmesg flooding.
---Lars
--
Lars Povlsen,
Microchip
Andy Shevchenko writes:
> On Mon, Nov 9, 2020 at 3:27 PM Lars Povlsen
> wrote:
>>
>> This adds a pinctrl driver for the Microsemi/Microchip Serial GPIO
>> (SGPIO) device used in various SoC's.
>
> Please, elaborate what you said previously, because now it
This adds SGPIO devices for the Sparx5 SoC and configures it for the
applicable reference boards.
Signed-off-by: Lars Povlsen
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 91 ++
.../boot/dts/microchip/sparx5_pcb125.dts | 5 +
.../dts/microchip/sparx5_pcb134_board.dtsi
This adds a pinctrl driver for the Microsemi/Microchip Serial GPIO
(SGPIO) device used in various SoC's.
Signed-off-by: Lars Povlsen
---
MAINTAINERS | 1 +
drivers/pinctrl/Kconfig | 16 +
drivers/pinctrl/Makefile
This adds DT bindings for the Microsemi/Microchip SGPIO controller,
bindings microchip,sparx5-sgpio, mscc,ocelot-sgpio and
mscc,luton-sgpio.
Signed-off-by: Lars Povlsen
Reviewed-by: Rob Herring
---
.../pinctrl/microchip,sparx5-sgpio.yaml | 145 ++
1 file changed, 145
o osoleting need for addressing macros in bindings include file.
- Property 'microchip,sgpio-ports' (uint32, bitmask) replaced by
proper range set (array of [start,end]) 'microchip,sgpio-port-ranges'.
- Fixes whitespace issues in Kconfig file
Lars Povlsen (3):
dt-bindings:
/trinity-i386.cgz
-N -P /home/larsi/.lkp/cache/osimage/pkg/yocto-i386-minimal-20190520.cgz
Failed to download osimage/pkg/yocto-i386-minimal-20190520.cgz/trinity-i386.cgz
It seems, that the trinity-i386.cgz file is not downloadable. Using a
webbrowser I can see an empty directory.
Can you help please ?
Thanks,
Lars
Andy Shevchenko writes:
> On Thu, Oct 29, 2020 at 3:40 PM Lars Povlsen
> wrote:
>>
>> This adds a pinctrl driver for the Microsemi/Microchip Serial GPIO
>> (SGPIO) device used in various SoC's.
>
> First Q is can you use gpio-regmap?
> Second one, why t
@@ static int lcd2s_i2c_remove(struct i2c_client *i2c)
> {
> struct lcd2s_data *lcd2s = i2c_get_clientdata(i2c);
>
> - kfree(lcd2s->charlcd);
> charlcd_unregister(lcd2s->charlcd);
> + kfree(lcd2s->charlcd);
> return 0;
> }
Reviewed-by: Lars Pöschel
Thanks,
Lars
On Wed, Nov 04, 2020 at 02:30:04PM +0100, Miguel Ojeda wrote:
> Thanks a lot for all the work, Lars. Queued in -next.
I got an email [1] with a report about a build failure in
hd44780_common. The fix is simple but I don't know the process from here
on. Should I post a v7 of the whole pat
direction encoding, and using 'offsetof' when calculating GPIO
register offsets.
The updated driver has been tested with the Sparx5 pcb134/pcb135
board, which has the mcp2221 device with several (output) GPIO's.
Signed-off-by: Lars Povlsen
---
drivers/hid/hid
On Sat, Oct 31, 2020 at 10:26:30AM +0100, Miguel Ojeda wrote:
> Hi Lars,
>
> On Thu, Oct 29, 2020 at 10:57 AM wrote:
> >
> > diff --git a/drivers/auxdisplay/Kconfig b/drivers/auxdisplay/Kconfig
> > index 81757eeded68..a56171d1a1ba 100644
> > --- a/drivers/aux
This adds DT bindings for the Microsemi/Microchip SGPIO controller,
bindings microchip,sparx5-sgpio, mscc,ocelot-sgpio and
mscc,luton-sgpio.
Signed-off-by: Lars Povlsen
Reviewed-by: Rob Herring
---
.../pinctrl/microchip,sparx5-sgpio.yaml | 145 ++
1 file changed, 145
This adds SGPIO devices for the Sparx5 SoC and configures it for the
applicable reference boards.
Signed-off-by: Lars Povlsen
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 91 ++
.../boot/dts/microchip/sparx5_pcb125.dts | 5 +
.../dts/microchip/sparx5_pcb134_board.dtsi
This adds a pinctrl driver for the Microsemi/Microchip Serial GPIO
(SGPIO) device used in various SoC's.
Signed-off-by: Lars Povlsen
---
MAINTAINERS | 1 +
drivers/pinctrl/Kconfig | 18 +
drivers/pinctrl/Makefile
pe/symbol naming changes
v2 changes:
- Adds both in and output modes.
- Use direct adressing of the individual banks (#gpio-cells = <4>),
also osoleting need for addressing macros in bindings include file.
- Property 'microchip,sgpio-ports' (uint32, bitmask) replaced by
proper ran
This series was sent wrong. Should be v5. Drop this one.
Sorry and thanks,
Lars
On Thu, Oct 29, 2020 at 10:50:07AM +0100, poesc...@lemonage.de wrote:
> From: Lars Poeschel
>
> This tries to make charlcd device independent. At the moment hd44780
> device specific code is conta
Hi Andy!
Andy Shevchenko writes:
> On Wed, Oct 14, 2020 at 6:25 PM Lars Povlsen
> wrote:
>>
>> This adds a pinctrl driver for the Microsemi/Microchip Serial GPIO
>> (SGPIO) device used in various SoC's.
>
> ...
>
>> +#define PIN_NAM_SZ
1 - 100 of 1443 matches
Mail list logo
