On Thu, Dec 06, 2018 at 08:02:38PM +0800, Hanjie Lin wrote:
> From: Yue Wang
>
> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
> PCI core. This patch adds the driver support for Meson PCIe controller.
>
> Signed-off-by: Yue Wang
> Signed-off-by: Hanjie Lin
> ---
>
On Thu, Dec 13, 2018 at 03:30:00PM +0100, Miquel Raynal wrote:
> Hi Lorenzo,
>
> > > If that's really the case, then I can see how one device and it's
> > > children are suspended and the irq for it is disabled but the providing
> > > devices (clk, regulator, bus controller, etc.) are still fully
On Thu, Dec 13, 2018 at 11:07:16AM +0100, Lucas Stach wrote:
> Am Donnerstag, den 13.12.2018, 09:57 + schrieb Richard Zhu:
> > Hi Lucas:
> >
> > > -Original Message-
> > > > > From: Lucas Stach [mailto:l.st...@pengutronix.de]
> > > Sent: 2018年12月13日 17:19
> > > > > > > To: Richard Zhu
On Thu, Dec 13, 2018 at 01:00:26AM -0800, Stephen Boyd wrote:
> Quoting Lorenzo Pieralisi (2018-12-11 06:16:27)
> > On Tue, Dec 04, 2018 at 10:42:19PM +0100, Rafael J. Wysocki wrote:
> > > On Tuesday, December 4, 2018 10:45:58 AM CET Lorenzo Pieralisi wrote:
> > > >
On Tue, Dec 11, 2018 at 10:21:08AM +, Z.q. Hou wrote:
[...]
> > > + */
> > > + if (pci->num_viewport < 2) {
> > > + ret = of_property_read_u32(np, "num-viewport",
> > > +>num_viewport);
> > > + if (ret || pci->num_viewport < 2)
> > > +
On Thu, Dec 06, 2018 at 01:25:17AM +, Z.q. Hou wrote:
> Hi Lorenzo,
>
> Thanks a lot for your comments!
>
> > -Original Message-
> > From: Lorenzo Pieralisi
> > Sent: 2018??12??6?? 0:02
> > To: Z.q. Hou
> > Cc: linux-...@vger.kernel.or
On Tue, Dec 04, 2018 at 10:42:19PM +0100, Rafael J. Wysocki wrote:
> On Tuesday, December 4, 2018 10:45:58 AM CET Lorenzo Pieralisi wrote:
> > On Mon, Dec 03, 2018 at 11:00:20PM +0100, Rafael J. Wysocki wrote:
> > > On Monday, December 3, 2018 4:38:46 PM CET Miquel Raynal wrote:
On Fri, Dec 07, 2018 at 12:57:00PM +0100, Rafael J. Wysocki wrote:
> From: Rafael J. Wysocki
> Subject: [PATCH] cpuidle: Add 'above' and 'below' idle state metrics
>
> Add two new metrics for CPU idle states, "above" and "below", to count
> the number of times the given state had been asked for
On Sat, Nov 17, 2018 at 10:12:22AM -0800, Andrey Smirnov wrote:
>
> Everyone:
>
> This series contains changes I made in order to enable support of PCIE
> IP block on i.MX8MQ SoCs (full tree can be found at [github-v0]). This series
> is _very_ preliminary and by no means is ready for inclusion
On Sat, Nov 17, 2018 at 10:12:22AM -0800, Andrey Smirnov wrote:
>
> Everyone:
>
> This series contains changes I made in order to enable support of PCIE
> IP block on i.MX8MQ SoCs (full tree can be found at [github-v0]). This series
> is _very_ preliminary and by no means is ready for inclusion
On Wed, Dec 05, 2018 at 11:35:42PM -0800, Andrey Smirnov wrote:
> Everyone:
>
> This series contains changes I made in order to enable support of PCIE
> IP block on i.MX8MQ SoCs (full tree can be found at [github-v2]).
>
> NOTE: The last patch have a Kconfig symbol depenency on [imx8mq-kconfig].
On Wed, Dec 05, 2018 at 11:35:42PM -0800, Andrey Smirnov wrote:
> Everyone:
>
> This series contains changes I made in order to enable support of PCIE
> IP block on i.MX8MQ SoCs (full tree can be found at [github-v2]).
>
> NOTE: The last patch have a Kconfig symbol depenency on [imx8mq-kconfig].
On Wed, Nov 07, 2018 at 10:09:10AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> The current type of mem_size is 'u32', so when resource_size()
> return 4G it will be truncated to zero. This patch fix it by
> changing its type to 'u64'.
>
> Signed-off-by: Hou Zhiqiang
> Acked-by: Gustavo
On Wed, Nov 07, 2018 at 10:09:10AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> The current type of mem_size is 'u32', so when resource_size()
> return 4G it will be truncated to zero. This patch fix it by
> changing its type to 'u64'.
>
> Signed-off-by: Hou Zhiqiang
> Acked-by: Gustavo
On Wed, Nov 07, 2018 at 10:09:04AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> Free the allocated pci_host_bridge struct when failed to get
> host bridge resources, and free the resource windows before
> free the bridge.
>
> Signed-off-by: Hou Zhiqiang
> Acked-by: Gustavo Pimentel
> ---
>
On Wed, Nov 07, 2018 at 10:09:04AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> Free the allocated pci_host_bridge struct when failed to get
> host bridge resources, and free the resource windows before
> free the bridge.
>
> Signed-off-by: Hou Zhiqiang
> Acked-by: Gustavo Pimentel
> ---
>
On Tue, Dec 04, 2018 at 10:42:19PM +0100, Rafael J. Wysocki wrote:
> On Tuesday, December 4, 2018 10:45:58 AM CET Lorenzo Pieralisi wrote:
> > On Mon, Dec 03, 2018 at 11:00:20PM +0100, Rafael J. Wysocki wrote:
> > > On Monday, December 3, 2018 4:38:46 PM CET Miquel Raynal wrote:
On Tue, Dec 04, 2018 at 10:42:19PM +0100, Rafael J. Wysocki wrote:
> On Tuesday, December 4, 2018 10:45:58 AM CET Lorenzo Pieralisi wrote:
> > On Mon, Dec 03, 2018 at 11:00:20PM +0100, Rafael J. Wysocki wrote:
> > > On Monday, December 3, 2018 4:38:46 PM CET Miquel Raynal wrote:
On Wed, Nov 28, 2018 at 01:04:26PM +0900, Kunihiko Hayashi wrote:
[...]
> +static void uniphier_pcie_irq_ack(struct irq_data *d)
> +{
> + struct pcie_port *pp = irq_data_get_irq_chip_data(d);
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct uniphier_pcie_priv *priv =
On Wed, Nov 28, 2018 at 01:04:26PM +0900, Kunihiko Hayashi wrote:
[...]
> +static void uniphier_pcie_irq_ack(struct irq_data *d)
> +{
> + struct pcie_port *pp = irq_data_get_irq_chip_data(d);
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct uniphier_pcie_priv *priv =
On Tue, Dec 04, 2018 at 06:40:55PM +0800, Hanjie Lin wrote:
>
>
> On 2018/12/4 6:57, Bjorn Helgaas wrote:
> > On Mon, Dec 03, 2018 at 04:41:50PM +, Lorenzo Pieralisi wrote:
> >> On Thu, Nov 22, 2018 at 04:53:54PM +0800, Hanjie Lin wrote:
> >>
On Tue, Dec 04, 2018 at 06:40:55PM +0800, Hanjie Lin wrote:
>
>
> On 2018/12/4 6:57, Bjorn Helgaas wrote:
> > On Mon, Dec 03, 2018 at 04:41:50PM +, Lorenzo Pieralisi wrote:
> >> On Thu, Nov 22, 2018 at 04:53:54PM +0800, Hanjie Lin wrote:
> >>
On Mon, Dec 03, 2018 at 11:00:20PM +0100, Rafael J. Wysocki wrote:
> On Monday, December 3, 2018 4:38:46 PM CET Miquel Raynal wrote:
> > Hi Lorenzo,
> >
> > Lorenzo Pieralisi wrote on Mon, 3 Dec 2018
> > 10:27:08 +:
> >
> > > [+Rafael, Sudeep]
>
On Mon, Dec 03, 2018 at 11:00:20PM +0100, Rafael J. Wysocki wrote:
> On Monday, December 3, 2018 4:38:46 PM CET Miquel Raynal wrote:
> > Hi Lorenzo,
> >
> > Lorenzo Pieralisi wrote on Mon, 3 Dec 2018
> > 10:27:08 +:
> >
> > > [+Rafael, Sudeep]
>
[+Stephen, Mike]
On Mon, Dec 03, 2018 at 04:38:46PM +0100, Miquel Raynal wrote:
> Hi Lorenzo,
>
> Lorenzo Pieralisi wrote on Mon, 3 Dec 2018
> 10:27:08 +:
>
> > [+Rafael, Sudeep]
> >
> > On Fri, Nov 23, 2018 at 03:18:24PM +0100, Miquel Raynal wrote:
>
[+Stephen, Mike]
On Mon, Dec 03, 2018 at 04:38:46PM +0100, Miquel Raynal wrote:
> Hi Lorenzo,
>
> Lorenzo Pieralisi wrote on Mon, 3 Dec 2018
> 10:27:08 +:
>
> > [+Rafael, Sudeep]
> >
> > On Fri, Nov 23, 2018 at 03:18:24PM +0100, Miquel Raynal wrote:
>
On Thu, Nov 22, 2018 at 04:53:54PM +0800, Hanjie Lin wrote:
[...]
> +static int meson_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
> + u32 *val)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> +
> + /*
> + * there is a bug of
On Thu, Nov 22, 2018 at 04:53:54PM +0800, Hanjie Lin wrote:
[...]
> +static int meson_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
> + u32 *val)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> +
> + /*
> + * there is a bug of
On Sat, Nov 17, 2018 at 10:12:22AM -0800, Andrey Smirnov wrote:
>
> Everyone:
>
> This series contains changes I made in order to enable support of PCIE
> IP block on i.MX8MQ SoCs (full tree can be found at [github-v0]). This series
> is _very_ preliminary and by no means is ready for inclusion
On Sat, Nov 17, 2018 at 10:12:22AM -0800, Andrey Smirnov wrote:
>
> Everyone:
>
> This series contains changes I made in order to enable support of PCIE
> IP block on i.MX8MQ SoCs (full tree can be found at [github-v0]). This series
> is _very_ preliminary and by no means is ready for inclusion
On Tue, Nov 06, 2018 at 01:19:03PM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> This patch set is aim to refactor the Mobiveil driver and add
> PCIe support for NXP LX series SoCs.
>
> Hou Zhiqiang (23):
> PCI: mobiveil: uniform the register accessors
> PCI: mobiveil: format the code
On Tue, Nov 06, 2018 at 01:19:03PM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> This patch set is aim to refactor the Mobiveil driver and add
> PCIe support for NXP LX series SoCs.
>
> Hou Zhiqiang (23):
> PCI: mobiveil: uniform the register accessors
> PCI: mobiveil: format the code
[+Rafael, Sudeep]
On Fri, Nov 23, 2018 at 03:18:24PM +0100, Miquel Raynal wrote:
> Add suspend and resume callbacks. The priority of these are
> "_noirq()", to workaround early access to the registers done by the
> PCI core through the ->read()/->write() callbacks at resume time.
>
>
[+Rafael, Sudeep]
On Fri, Nov 23, 2018 at 03:18:24PM +0100, Miquel Raynal wrote:
> Add suspend and resume callbacks. The priority of these are
> "_noirq()", to workaround early access to the registers done by the
> PCI core through the ->read()/->write() callbacks at resume time.
>
>
On Fri, Nov 30, 2018 at 11:33:00AM +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> Use the devm_of_pci_get_host_bridge_resources() API in place of the PCI OF
> DT parser.
>
> Signed-off-by: Honghui Zhang
> Acked-by: Ryder Lee
> ---
> drivers/pci/controller/pcie-mediatek.c
On Fri, Nov 30, 2018 at 11:33:00AM +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> Use the devm_of_pci_get_host_bridge_resources() API in place of the PCI OF
> DT parser.
>
> Signed-off-by: Honghui Zhang
> Acked-by: Ryder Lee
> ---
> drivers/pci/controller/pcie-mediatek.c
On Thu, Nov 08, 2018 at 10:56:55AM +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> Use the devm_of_pci_get_host_bridge_resources() API in place of the PCI OF
> DT parser.
>
> Signed-off-by: Honghui Zhang
> ---
> drivers/pci/controller/pcie-mediatek.c | 98
>
On Thu, Nov 08, 2018 at 10:56:55AM +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> Use the devm_of_pci_get_host_bridge_resources() API in place of the PCI OF
> DT parser.
>
> Signed-off-by: Honghui Zhang
> ---
> drivers/pci/controller/pcie-mediatek.c | 98
>
On Wed, Nov 07, 2018 at 10:09:21AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> The current code only support non-prefetchable memory range,
> as the non-prefetchable memory range must not be greater than
> 4GiB, one viewport can cover it, which supports upto 4GiB.
>
> To support
On Wed, Nov 07, 2018 at 10:09:21AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> The current code only support non-prefetchable memory range,
> as the non-prefetchable memory range must not be greater than
> 4GiB, one viewport can cover it, which supports upto 4GiB.
>
> To support
On Fri, Oct 12, 2018 at 02:29:37PM -0500, Jeremy Linton wrote:
> The BAD_MADT_GICC_ENTRY check is a little too strict because
> it rejects MADT entries that don't match the currently known
> lengths. We should remove this restriction to avoid problems
> if the table length changes. Future code
On Fri, Oct 12, 2018 at 02:29:37PM -0500, Jeremy Linton wrote:
> The BAD_MADT_GICC_ENTRY check is a little too strict because
> it rejects MADT entries that don't match the currently known
> lengths. We should remove this restriction to avoid problems
> if the table length changes. Future code
On Tue, Nov 20, 2018 at 09:15:31PM +0900, Kunihiko Hayashi wrote:
[...]
> > > +static int uniphier_pcie_link_up(struct dw_pcie *pci)
> >
> > This function returns a bool value, make it return a bool.
>
> This function is registered in struct dw_pcie_ops.link_up, that is defined
> in
On Tue, Nov 20, 2018 at 09:15:31PM +0900, Kunihiko Hayashi wrote:
[...]
> > > +static int uniphier_pcie_link_up(struct dw_pcie *pci)
> >
> > This function returns a bool value, make it return a bool.
>
> This function is registered in struct dw_pcie_ops.link_up, that is defined
> in
On Mon, Nov 19, 2018 at 08:01:25PM +0800, Shawn Guo wrote:
> On Wed, Nov 07, 2018 at 05:35:12AM +, Z.q. Hou wrote:
> > From: Hou Zhiqiang
> >
> > Removed the compatible string "snps,dw-pcie" from FSL layerscape-pci
> > compatible
> > string list.
> >
> > Hou Zhiqiang (4):
> >
On Mon, Nov 19, 2018 at 08:01:25PM +0800, Shawn Guo wrote:
> On Wed, Nov 07, 2018 at 05:35:12AM +, Z.q. Hou wrote:
> > From: Hou Zhiqiang
> >
> > Removed the compatible string "snps,dw-pcie" from FSL layerscape-pci
> > compatible
> > string list.
> >
> > Hou Zhiqiang (4):
> >
On Wed, Nov 07, 2018 at 01:57:03PM +, Leonard Crestez wrote:
> Enable PCI suspend/resume support on imx6sx socs. This is similar to
> imx7d with a few differences:
>
> * The PM_Turn_Off bit is exposed through an IOMUX GPR, like all other
> pcie control bits on 6sx.
> * The pcie_inbound_axi
On Wed, Nov 07, 2018 at 01:57:03PM +, Leonard Crestez wrote:
> Enable PCI suspend/resume support on imx6sx socs. This is similar to
> imx7d with a few differences:
>
> * The PM_Turn_Off bit is exposed through an IOMUX GPR, like all other
> pcie control bits on 6sx.
> * The pcie_inbound_axi
On Wed, Nov 07, 2018 at 01:57:03PM +, Leonard Crestez wrote:
> Enable PCI suspend/resume support on imx6sx socs. This is similar to
> imx7d with a few differences:
>
> * The PM_Turn_Off bit is exposed through an IOMUX GPR, like all other
> pcie control bits on 6sx.
> * The pcie_inbound_axi
On Wed, Nov 07, 2018 at 01:57:03PM +, Leonard Crestez wrote:
> Enable PCI suspend/resume support on imx6sx socs. This is similar to
> imx7d with a few differences:
>
> * The PM_Turn_Off bit is exposed through an IOMUX GPR, like all other
> pcie control bits on 6sx.
> * The pcie_inbound_axi
On Mon, Oct 08, 2018 at 11:14:26AM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> Removed the compatible string "snps,dw-pcie", it is for the reference
> platform driver for PCI RC IP Protoyping Kits based on the ARC SDP,
> so it is not suitable for all platform with designware PCIe
On Mon, Oct 08, 2018 at 11:14:26AM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> Removed the compatible string "snps,dw-pcie", it is for the reference
> platform driver for PCI RC IP Protoyping Kits based on the ARC SDP,
> so it is not suitable for all platform with designware PCIe
On Wed, Nov 07, 2018 at 10:09:16AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> FSL implements 6 viewports on Layerscape series SoCs PCIe
> controllers.
>
> Signed-off-by: Hou Zhiqiang
> ---
> V2:
> - Reworded the subject and commit description.
>
>
On Wed, Nov 07, 2018 at 10:09:16AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> FSL implements 6 viewports on Layerscape series SoCs PCIe
> controllers.
>
> Signed-off-by: Hou Zhiqiang
> ---
> V2:
> - Reworded the subject and commit description.
>
>
On Wed, Nov 21, 2018 at 01:47:05PM +, Leonard Crestez wrote:
> On 11/20/2018 11:28 PM, Trent Piepho wrote:
> > On Tue, 2018-11-20 at 21:42 +0100, Stefan Agner wrote:
> >> On 20.11.2018 20:13, Trent Piepho wrote:
>
> >>> It also seems to me that this doesn't need to be in the internal pci
>
On Wed, Nov 21, 2018 at 01:47:05PM +, Leonard Crestez wrote:
> On 11/20/2018 11:28 PM, Trent Piepho wrote:
> > On Tue, 2018-11-20 at 21:42 +0100, Stefan Agner wrote:
> >> On 20.11.2018 20:13, Trent Piepho wrote:
>
> >>> It also seems to me that this doesn't need to be in the internal pci
>
On Fri, Nov 16, 2018 at 12:08:33AM +, Trent Piepho wrote:
> The IMX6 PCI-e host drier also supports the IMX7d. However, the
> Kconfig dependencies of the driver prevented it from being enabled
> unless the kernel was built with both IMX6 and IMX7 support. It works
> fine to build with only
On Fri, Nov 16, 2018 at 12:08:33AM +, Trent Piepho wrote:
> The IMX6 PCI-e host drier also supports the IMX7d. However, the
> Kconfig dependencies of the driver prevented it from being enabled
> unless the kernel was built with both IMX6 and IMX7 support. It works
> fine to build with only
On Tue, Nov 20, 2018 at 02:27:03PM +0100, Stefan Agner wrote:
> Add length to the struct dw_pcie and check that the accessors
> dw_pcie_(rd|wr)_own_conf() do not read/write beyond that point.
>
> Signed-off-by: Stefan Agner
> ---
> drivers/pci/controller/dwc/pcie-designware-host.c | 4
>
On Tue, Nov 20, 2018 at 02:27:03PM +0100, Stefan Agner wrote:
> Add length to the struct dw_pcie and check that the accessors
> dw_pcie_(rd|wr)_own_conf() do not read/write beyond that point.
>
> Signed-off-by: Stefan Agner
> ---
> drivers/pci/controller/dwc/pcie-designware-host.c | 4
>
On Mon, Nov 19, 2018 at 11:00:22AM +0100, Stefan Agner wrote:
> Constify driver data since they don't get changed at runtime.
>
> Signed-off-by: Stefan Agner
> ---
> drivers/pci/controller/dwc/pci-layerscape.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
Applied to
On Mon, Nov 19, 2018 at 11:00:22AM +0100, Stefan Agner wrote:
> Constify driver data since they don't get changed at runtime.
>
> Signed-off-by: Stefan Agner
> ---
> drivers/pci/controller/dwc/pci-layerscape.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
Applied to
On Mon, Oct 08, 2018 at 11:14:24AM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> Removed the compatible string "snps,dw-pcie" from FSL layerscape-pci
> compatible
> string list.
>
> Hou Zhiqiang (4):
> doc/layerscape-pci: update the PCIe compatible strings
> doc/layerscape-pci:
On Mon, Oct 08, 2018 at 11:14:24AM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> Removed the compatible string "snps,dw-pcie" from FSL layerscape-pci
> compatible
> string list.
>
> Hou Zhiqiang (4):
> doc/layerscape-pci: update the PCIe compatible strings
> doc/layerscape-pci:
On Sat, Oct 27, 2018 at 08:31:19PM +0200, Julia Lawall wrote:
> The dw_pcie_host_ops structure is only stored in the ops field
> of a pcie_port structure, and this field is const, so make the
> dw_pcie_host_ops structure const as well.
>
> Done with the help of Coccinelle.
>
> Signed-off-by:
On Sat, Oct 27, 2018 at 08:31:19PM +0200, Julia Lawall wrote:
> The dw_pcie_host_ops structure is only stored in the ops field
> of a pcie_port structure, and this field is const, so make the
> dw_pcie_host_ops structure const as well.
>
> Done with the help of Coccinelle.
>
> Signed-off-by:
On Wed, Nov 07, 2018 at 05:16:49AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> The order of parameters is not correct when invoking the outbound
> window disable routine.
>
> Fixes: commit 4a2745d760fac ("PCI: layerscape: Disable outbound
> windows configured by bootloader").
>
> Cc:
On Wed, Nov 07, 2018 at 05:16:49AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> The order of parameters is not correct when invoking the outbound
> window disable routine.
>
> Fixes: commit 4a2745d760fac ("PCI: layerscape: Disable outbound
> windows configured by bootloader").
>
> Cc:
On Tue, Oct 16, 2018 at 02:27:21PM +0900, Kunihiko Hayashi wrote:
> This introduces specific glue layer for UniPhier platform to support
> PCIe host controller that is based on the DesignWare PCIe core, and
> this driver supports Root Complex (host) mode.
>
> Signed-off-by: Kunihiko Hayashi
>
On Tue, Oct 16, 2018 at 02:27:21PM +0900, Kunihiko Hayashi wrote:
> This introduces specific glue layer for UniPhier platform to support
> PCIe host controller that is based on the DesignWare PCIe core, and
> this driver supports Root Complex (host) mode.
>
> Signed-off-by: Kunihiko Hayashi
>
On Tue, Oct 16, 2018 at 02:27:20PM +0900, Kunihiko Hayashi wrote:
> Add DT bindings for PCIe controller implemented in UniPhier SoCs when
> configured in Root Complex (host) mode. This controller is based on
> the DesignWare PCIe core.
>
> Signed-off-by: Kunihiko Hayashi
> Reviewed-by: Rob
On Tue, Oct 16, 2018 at 02:27:20PM +0900, Kunihiko Hayashi wrote:
> Add DT bindings for PCIe controller implemented in UniPhier SoCs when
> configured in Root Complex (host) mode. This controller is based on
> the DesignWare PCIe core.
>
> Signed-off-by: Kunihiko Hayashi
> Reviewed-by: Rob
On Tue, Oct 09, 2018 at 09:53:10AM +0800, Hanjie Lin wrote:
> From: Yue Wang
>
> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
> PCI core. This patch adds the driver support for Meson PCIe controller.
>
> Signed-off-by: Yue Wang
> Signed-off-by: Hanjie Lin
> ---
>
On Tue, Oct 09, 2018 at 09:53:10AM +0800, Hanjie Lin wrote:
> From: Yue Wang
>
> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
> PCI core. This patch adds the driver support for Meson PCIe controller.
>
> Signed-off-by: Yue Wang
> Signed-off-by: Hanjie Lin
> ---
>
On Thu, Oct 04, 2018 at 12:11:44PM +0100, Lorenzo Pieralisi wrote:
> On Thu, Sep 20, 2018 at 05:02:53PM +0200, Jean-Jacques Hiblot wrote:
> > This makes it easier to use pcitest in automated setups.
> >
> > Signed-off-by: Jean-Jacques Hiblot
> > ---
> > tools/p
On Thu, Oct 04, 2018 at 12:11:44PM +0100, Lorenzo Pieralisi wrote:
> On Thu, Sep 20, 2018 at 05:02:53PM +0200, Jean-Jacques Hiblot wrote:
> > This makes it easier to use pcitest in automated setups.
> >
> > Signed-off-by: Jean-Jacques Hiblot
> > ---
> > tools/p
On Thu, Oct 18, 2018 at 11:23:34AM +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> Use the devm_of_pci_get_host_bridge_resources() API in place of the PCI OF
> DT parser.
>
> Signed-off-by: Honghui Zhang
> ---
> drivers/pci/controller/pcie-mediatek.c | 109
>
On Thu, Oct 18, 2018 at 11:23:34AM +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> Use the devm_of_pci_get_host_bridge_resources() API in place of the PCI OF
> DT parser.
>
> Signed-off-by: Honghui Zhang
> ---
> drivers/pci/controller/pcie-mediatek.c | 109
>
On Tue, Nov 06, 2018 at 09:47:52AM -0700, Keith Busch wrote:
> On Tue, Nov 06, 2018 at 04:34:08PM +0000, Lorenzo Pieralisi wrote:
> > The question is whether we really need to dynamically patch the kernel
> > with ftrace to achieve what that patch does.
> >
> > Further
On Tue, Nov 06, 2018 at 09:47:52AM -0700, Keith Busch wrote:
> On Tue, Nov 06, 2018 at 04:34:08PM +0000, Lorenzo Pieralisi wrote:
> > The question is whether we really need to dynamically patch the kernel
> > with ftrace to achieve what that patch does.
> >
> > Further
On Mon, Oct 08, 2018 at 10:18:47AM -0600, Keith Busch wrote:
> On Fri, Oct 05, 2018 at 12:31:45PM -0500, Bjorn Helgaas wrote:
> > [+cc arm64 folks, LKML: This conversation is about this patch:
> >
> >
> > https://lore.kernel.org/linux-pci/20180918235848.26694-3-keith.bu...@intel.com
> >
> >
On Mon, Oct 08, 2018 at 10:18:47AM -0600, Keith Busch wrote:
> On Fri, Oct 05, 2018 at 12:31:45PM -0500, Bjorn Helgaas wrote:
> > [+cc arm64 folks, LKML: This conversation is about this patch:
> >
> >
> > https://lore.kernel.org/linux-pci/20180918235848.26694-3-keith.bu...@intel.com
> >
> >
On Fri, Oct 12, 2018 at 02:29:37PM -0500, Jeremy Linton wrote:
> The BAD_MADT_GICC_ENTRY check is a little too strict because
> it rejects MADT entries that don't match the currently known
> lengths. We should remove this restriction to avoid problems
> if the table length changes. Future code
On Fri, Oct 12, 2018 at 02:29:37PM -0500, Jeremy Linton wrote:
> The BAD_MADT_GICC_ENTRY check is a little too strict because
> it rejects MADT entries that don't match the currently known
> lengths. We should remove this restriction to avoid problems
> if the table length changes. Future code
On Mon, Oct 15, 2018 at 04:08:51PM +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> This patchset includes misc patchs:
>
> The patch 1 fixup the mtk_pcie_find_port logic which will cause system
> could not touch the EP's configuration space that connected to PCIe slot 1.
>
>
On Mon, Oct 15, 2018 at 04:08:51PM +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> This patchset includes misc patchs:
>
> The patch 1 fixup the mtk_pcie_find_port logic which will cause system
> could not touch the EP's configuration space that connected to PCIe slot 1.
>
>
On Wed, Oct 17, 2018 at 01:10:53PM +0530, Kishon Vijay Abraham I wrote:
> The PCIe controller in AM654 uses Synopsys core revision 4.90a and uses
> the same TI wrapper as used in keystone2 with certain modification.
> Hence AM654 will use the same pci wrapper driver pci-keystone.c
>
> In
On Wed, Oct 17, 2018 at 01:10:53PM +0530, Kishon Vijay Abraham I wrote:
> The PCIe controller in AM654 uses Synopsys core revision 4.90a and uses
> the same TI wrapper as used in keystone2 with certain modification.
> Hence AM654 will use the same pci wrapper driver pci-keystone.c
>
> In
On Mon, Oct 15, 2018 at 06:37:13PM +0530, Kishon Vijay Abraham I wrote:
> Cleanup PHY handling by using devm_phy_optional_get to get PHYs if
> the PHYs are optional, creating a device link between the PHY device
> and the controller device and disable PHY on error cases here.
> Also invoke
On Mon, Oct 15, 2018 at 06:37:13PM +0530, Kishon Vijay Abraham I wrote:
> Cleanup PHY handling by using devm_phy_optional_get to get PHYs if
> the PHYs are optional, creating a device link between the PHY device
> and the controller device and disable PHY on error cases here.
> Also invoke
On Tue, Oct 16, 2018 at 06:44:43PM +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> The PCI configuration space header type defines the layout of the rest
> of the header (PCI r3.0 sec 6.1, PCIe r4.0 sec 7.5.1.1.9) while the
> resource assignment is based on the configuration
On Tue, Oct 16, 2018 at 06:44:43PM +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> The PCI configuration space header type defines the layout of the rest
> of the header (PCI r3.0 sec 6.1, PCIe r4.0 sec 7.5.1.1.9) while the
> resource assignment is based on the configuration
On Fri, Sep 21, 2018 at 03:51:15PM +0530, Kishon Vijay Abraham I wrote:
> Add PCIe RC support for TI's AM654 SoC. The PCIe controller in AM654
> uses Synopsys core revision 4.90a and uses the same TI wrapper as used
> in keystone2 with certain modification. Hence AM654 will use the same
> pci
On Fri, Sep 21, 2018 at 03:51:15PM +0530, Kishon Vijay Abraham I wrote:
> Add PCIe RC support for TI's AM654 SoC. The PCIe controller in AM654
> uses Synopsys core revision 4.90a and uses the same TI wrapper as used
> in keystone2 with certain modification. Hence AM654 will use the same
> pci
On Fri, Oct 12, 2018 at 04:01:29PM +0800, Honghui Zhang wrote:
> On Thu, 2018-10-11 at 12:38 +0100, Lorenzo Pieralisi wrote:
> > On Tue, Oct 09, 2018 at 11:08:15AM +0800, Honghui Zhang wrote:
> > > On Mon, 2018-10-08 at 18:23 +0100, Lorenzo Pieralisi wrote:
> > > >
On Fri, Oct 12, 2018 at 04:01:29PM +0800, Honghui Zhang wrote:
> On Thu, 2018-10-11 at 12:38 +0100, Lorenzo Pieralisi wrote:
> > On Tue, Oct 09, 2018 at 11:08:15AM +0800, Honghui Zhang wrote:
> > > On Mon, 2018-10-08 at 18:23 +0100, Lorenzo Pieralisi wrote:
> > > >
On Tue, Oct 09, 2018 at 11:08:15AM +0800, Honghui Zhang wrote:
> On Mon, 2018-10-08 at 18:23 +0100, Lorenzo Pieralisi wrote:
> > On Mon, Oct 08, 2018 at 11:24:41AM +0800, honghui.zh...@mediatek.com wrote:
> > > From: Honghui Zhang
> > >
> > > The
On Tue, Oct 09, 2018 at 11:08:15AM +0800, Honghui Zhang wrote:
> On Mon, 2018-10-08 at 18:23 +0100, Lorenzo Pieralisi wrote:
> > On Mon, Oct 08, 2018 at 11:24:41AM +0800, honghui.zh...@mediatek.com wrote:
> > > From: Honghui Zhang
> > >
> > > The
On Mon, Oct 08, 2018 at 11:24:41AM +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> The PCIe controller of MT7622 has TYPE 1 configuration space type, but
> the HW default class type values is invalid.
>
> The commit 101c92dc80c8 ("PCI: mediatek: Set up vendor ID and class
>
On Mon, Oct 08, 2018 at 11:24:41AM +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> The PCIe controller of MT7622 has TYPE 1 configuration space type, but
> the HW default class type values is invalid.
>
> The commit 101c92dc80c8 ("PCI: mediatek: Set up vendor ID and class
>
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