From: Sanjay R Mehta
Expose data about the configuration and operation of the PTDMA
through debugfs entries: device name, capabilities, configuration,
statistics.
Signed-off-by: Sanjay R Mehta
Reviewed-by: Shyam Sundar S K
Reviewed-by: Rajesh Kumar
---
drivers/dma/ptdma/Makefile|
From: Sanjay R Mehta
This is the driver for the AMD passthrough DMA Engine
Signed-off-by: Sanjay R Mehta
Reviewed-by: Shyam Sundar S K
Reviewed-by: Rajesh Kumar
---
MAINTAINERS | 6 +
drivers/dma/Kconfig | 2 +
drivers/dma/Makefile | 1 +
From: Sanjay R Mehta
Enable management of multiple PTDMA engine in a system.
Each device will get a unique identifier, as well as
uniquely named resources. Treat each PTDMA as an orthogonal
unit and register resources individually.
Signed-off-by: Sanjay R Mehta
Reviewed-by: Shyam Sundar S K
From: Sanjay R Mehta
This Registers the ptdma to Linux dmaengine
framework as general purpose DMA channels.
Signed-off-by: Sanjay R Mehta
Reviewed-by: Shyam Sundar S K
Reviewed-by: Rajesh Kumar
---
drivers/dma/ptdma/Kconfig | 1 +
drivers/dma/ptdma/Makefile | 3 +-
From: Sanjay R Mehta
*** This patch series adds support for AMD PTDMA engine ***
Sanjay R Mehta (4):
dma: Add PTDMA Engine driver support
dma: Support for multiple PTDMA
dmaengine: Register as a DMA resource
dmaengine: Add debugfs entries for PTDMA information
MAINTAINERS
From: Sanjay R Mehta
The AMD new hardware uses BAR23 and BAR45 as memory windows
as compared to previos where BAR1, BAR23 and BAR45 is used
for memory windows.
This patch add support for both AMD hardwares.
Signed-off-by: Sanjay R Mehta
---
drivers/ntb/hw/amd/ntb_hw_amd.c | 23
From: Sanjay R Mehta
Signed-off-by: Sanjay R Mehta
---
drivers/ntb/hw/amd/ntb_hw_amd.c | 3 ++-
drivers/ntb/hw/amd/ntb_hw_amd.h | 1 -
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/ntb/hw/amd/ntb_hw_amd.c b/drivers/ntb/hw/amd/ntb_hw_amd.c
index 2859cc9..e9286cf 100644
Hi All,
Any comments on below patch?
Thanks & Regards,
Sanjay Mehta
-Original Message-
From: Mehta, Sanju
Sent: Friday, March 29, 2019 5:03 PM
To: S-k, Shyam-sundar ; jdma...@kudzu.us;
dave.ji...@intel.com; alle...@gmail.com
Cc: linux-...@googlegroups.com; linux-ke
From: Sanjay R Mehta
second parameter of ntb_peer_mw_get_addr is pointing to wrong memory
window index by passing "peer gidx" instead of "local gidx".
For ex, "local gidx" value is '0' and "peer gidx" value is '1', then
on peer side ntb_mw_set_trans() api is used as below with gidx pointing to
From: Sanjay R Mehta
when ntb_perf is unloaded, the command scratchpad register still
retains the last initialized value of PERF_CMD_INVAL. When ntb_perf
is re-loaded and reads peer command scratchpad register and it mis
interprets the peer state as initialized.
To avoid this, clearing the
From: Sanjay R Mehta
As per amd ntb spec it says that peer limit register
must be programmed
Signed-off-by: Sanjay R Mehta
---
drivers/ntb/hw/amd/ntb_hw_amd.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/ntb/hw/amd/ntb_hw_amd.c
From: Sanjay R Mehta
If ntb link disabled before clearing peer's XLAT register, the clearing
won't have any effect since the link is already down. So modified the
sequence so that the link is down only towards the end of the function
after clearing the XLAT register
Signed-off-by: Sanjay R
From: Sanjay R Mehta
while waiting for the peer ntb_perf to initialize scratchpad
registers, local side ntb_perf might have already exhausted the
maximum number of retries which is currently set to 500. To avoid
this and to give little more time to the peer ntb_perf for scratchpad
From: Sanjay R Mehta
Add bug fix for ntb_perf and ntb_hw_amd
Sanjay R Mehta (4):
NTB: ntb_perf: Increased the number of message retries to 1000
NTB: ntb_perf: Disable NTB link after clearing peer XLAT registers
NTB: ntb_perf: Clear stale values in doorbell and command SPAD
register
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