From: Peng Fan
V5:
yaml fix
V4:
yaml fix for num-chans in patch 1/2.
https://patchwork.kernel.org/cover/6521/
V3:
Drop interrupt
Introduce transports for mem/reg usage
Add chan-id for mem usage
Convert to yaml format
https://patchwork.kernel.org/cover/11043541/
V2:
This is a modified
Hi Rob,
> Subject: Re: [PATCH v4 1/2] dt-bindings: mailbox: add binding doc for the ARM
> SMC/HVC mailbox
>
> On Tue, Aug 27, 2019 at 4:51 AM Peng Fan wrote:
> >
> > From: Peng Fan
> >
> > The ARM SMC/HVC mailbox binding describes a firmware interface to
&g
Hi Robin,
> Subject: Re: [PATCH] arm: xen: mm: use __GPF_DMA32 for arm64
>
> On 09/07/2019 09:22, Peng Fan wrote:
> > arm64 shares some code under arch/arm/xen, including mm.c.
> > However ZONE_DMA is removed by commit
> > ad67f5a6545("arm64: replace ZONE_DMA wi
From: Peng Fan
This mailbox driver implements a mailbox which signals transmitted data
via an ARM smc (secure monitor call) instruction. The mailbox receiver
is implemented in firmware and can synchronously return data when it
returns execution to the non-secure world again.
An asynchronous
From: Peng Fan
V4:
yaml fix for num-chans in patch 1/2.
V3:
Drop interrupt
Introduce transports for mem/reg usage
Add chan-id for mem usage
Convert to yaml format
https://patchwork.kernel.org/cover/11043541/
V2:
This is a modified version from Andre Przywara's patch series
https
From: Peng Fan
The ARM SMC/HVC mailbox binding describes a firmware interface to trigger
actions in software layers running in the EL2 or EL3 exception levels.
The term "ARM" here relates to the SMC instruction as part of the ARM
instruction set, not as a standard endorsed by ARM Lt
g mm.c.
> > However ZONE_DMA is removed by commit
> > ad67f5a6545("arm64: replace ZONE_DMA with ZONE_DMA32").
> > So to ARM64, need use __GFP_DMA32.
> >
> > Signed-off-by: Peng Fan
> > ---
> > arch/arm/xen/mm.c | 2 +-
> > 1 file change
From: Peng Fan
There is hardware issue that:
The output clock the LPCG cell will not turn back on as expected,
even though a read of the IPG registers in the LPCG indicates that
the clock should be enabled.
The software workaround is to write twice to enable the LPCG clock
output.
Signed-off
From: Peng Fan
pll BYPASS bit should be kept inside pll driver for glitchless freq
setting following spec. If exposing the bit, that means pll driver and
clk driver has two paths to touch this bit, which is wrong.
So use EXT_BYPASS bit here.
And drop uneeded set parent, because EXT_BYPASS
From: Peng Fan
pll BYPASS bit should be kept inside pll driver for glitchless freq
setting following spec. If exposing the bit, that means pll driver and
clk driver has two paths to touch this bit, which is wrong.
So use EXT_BYPASS bit here.
And drop uneeded set parent, because EXT_BYPASS
From: Peng Fan
When registering the PLL, unbypass the PLL.
The PLL has two bypass control bit, BYPASS and EXT_BYPASS.
we will expose EXT_BYPASS to clk driver for mux usage, and keep
BYPASS inside pll14xx usage. The PLL has a restriction that
when M/P change, need to RESET/BYPASS pll to avoid
From: Peng Fan
According to PLL1443XA and PLL1416X spec,
"When BYPASS is 0 and RESETB is changed from 0 to 1, FOUT starts to
output unstable clock until lock time passes. PLL1416X/PLL1443XA may
generate a glitch at FOUT."
So set BYPASS when RESETB is changed from 0 to 1 to av
> Subject: Re: [PATCH] clk: imx: pll14xx: avoid glitch when set rate
>
> On 20.08.2019 05:17, Peng Fan wrote:
> > According to PLL1443XA and PLL1416X spec, "When BYPASS is 0 and RESETB
> > is changed from 0 to 1, FOUT starts to output unstable clock until
> > lock
From: Peng Fan
Introduce HOLE/ECC_REGION flag and in_hole helper to ease the check
of hole region. The ECC_REGION is also introduced here which is
preparing for programming support. ECC_REGION could only be programmed
once, so need take care.
Signed-off-by: Peng Fan
---
drivers/nvmem/imx
From: Peng Fan
The fuse programming from non-secure world is blocked, so we could
only use Arm Trusted Firmware SIP call to let ATF program fuse.
Because there is ECC region that could only be programmed once,
so add a heler in_ecc to check the ecc region.
Signed-off-by: Peng Fan
---
The ATF
From: Peng Fan
According to PLL1443XA and PLL1416X spec,
"When BYPASS is 0 and RESETB is changed from 0 to 1, FOUT starts to
output unstable clock until lock time passes. PLL1416X/PLL1443XA may
generate a glitch at FOUT."
So set BYPASS when RESETB is changed from 0 to 1 to av
From: Peng Fan
The AUDIO PLL max support 650M, so the original clk settings violate
spec. This patch makes the output 786432000 -> 393216000,
and 722534400 -> 361267200 to aligned with NXP vendor kernel without any
impact on audio functionality and go within 650MHz PLL limit.
Sign
Hi Stephen,
> Subject: Re: [PATCH] clk: imx8mn: fix int pll clk gate
>
> Quoting peng@nxp.com (2019-08-13 18:53:12)
> > From: Peng Fan
> >
> > To Frac pll, the gate shift is 13, however to Int PLL the gate shift
> > is 11.
> >
> > Cc:
&g
From: Peng Fan
To Frac pll, the gate shift is 13, however to Int PLL the gate shift
is 11.
Cc:
Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver")
Signed-off-by: Peng Fan
Reviewed-by: Jacky Bai
---
drivers/clk/imx/clk-imx8mn.c | 12 ++--
1 file
ol operations
> * @sensor_ops: pointer to set of sensor protocol operations
> + * @reset_ops: pointer to set of reset protocol operations
> * @perf_priv: pointer to private data structure specific to performance
> * protocol(for internal use only)
> * @clk_priv: pointer to private data structure specific to clock @@ -204,6
> +225,8 @@ struct scmi_sensor_ops {
> * protocol(for internal use only)
> * @sensor_priv: pointer to private data structure specific to sensors
> * protocol(for internal use only)
> + * @reset_priv: pointer to private data structure specific to reset
> + * protocol(for internal use only)
> */
> struct scmi_handle {
> struct device *dev;
> @@ -212,11 +235,13 @@ struct scmi_handle {
> struct scmi_clk_ops *clk_ops;
> struct scmi_power_ops *power_ops;
> struct scmi_sensor_ops *sensor_ops;
> + struct scmi_reset_ops *reset_ops;
> /* for protocol internal use */
> void *perf_priv;
> void *clk_priv;
> void *power_priv;
> void *sensor_priv;
> + void *reset_priv;
> };
>
> enum scmi_std_protocol {
> @@ -226,6 +251,7 @@ enum scmi_std_protocol {
> SCMI_PROTOCOL_PERF = 0x13,
> SCMI_PROTOCOL_CLOCK = 0x14,
> SCMI_PROTOCOL_SENSOR = 0x15,
> + SCMI_PROTOCOL_RESET = 0x16,
> };
Reviewed-by: Peng Fan
>
> struct scmi_device {
> --
> 2.17.1
2
> +domain,
> u32 *level, bool poll)
> {
> int ret;
> @@ -387,6 +469,20 @@ static int scmi_perf_level_get(const struct
> scmi_handle *handle, u32 domain,
> return ret;
> }
>
> +static int scmi_perf_level_get(const struct scmi_handle *handle, u32
> domain,
> +u32 *level, bool poll)
> +{
> + struct scmi_perf_info *pi = handle->perf_priv;
> + struct perf_dom_info *dom = pi->dom_info + domain;
> +
> + if (dom->fc_info && dom->fc_info->level_get_addr) {
> + *level = ioread32(dom->fc_info->level_get_addr);
> + return 0;
> + }
> +
> + return scmi_perf_mb_level_get(handle, domain, level, poll); }
> +
> static bool scmi_perf_fc_size_is_valid(u32 msg, u32 size) {
> if ((msg == PERF_LEVEL_GET || msg == PERF_LEVEL_SET) && size == 4)
Reviewed-by: Peng Fan
> --
> 2.17.1
_desc_fc(handle, domain, PERF_LEVEL_SET,
> + >level_set_addr, >level_set_db);
> + scmi_perf_domain_desc_fc(handle, domain, PERF_LEVEL_GET,
> + >level_get_addr, NULL);
> + scmi_perf_domain_desc_fc(handle, domain, PERF_LIMITS_SET,
> + >limit_set_addr, >limit_set_db);
> + scmi_perf_domain_desc_fc(handle, domain, PERF_LIMITS_GET,
> + >limit_get_addr, NULL);
> + *p_fc = fc;
> +}
> +
> /* Device specific ops */
> static int scmi_dev_domain_id(struct device *dev) { @@ -494,6 +636,9
> @@ static int scmi_perf_protocol_init(struct scmi_handle *handle)
>
> scmi_perf_domain_attributes_get(handle, domain, dom);
> scmi_perf_describe_levels_get(handle, domain, dom);
> +
> + if (dom->perf_fastchannels)
> + scmi_perf_domain_init_fc(handle, domain, >fc_info);
> }
>
> handle->perf_ops = _ops;
Reviewed-by: Peng Fan
> --
> 2.17.1
Hi All,
> Subject: [PATCH v3 2/2] mailbox: introduce ARM SMC based mailbox
Any comments with this patch?
>
> From: Peng Fan
>
> This mailbox driver implements a mailbox which signals transmitted data via
> an ARM smc (secure monitor call) instruction. The mailbox receive
ARM64, need use __GFP_DMA32.
>
> Signed-off-by: Peng Fan
> ---
> arch/arm/xen/mm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/xen/mm.c b/arch/arm/xen/mm.c index
> e1d44b903dfc..a95e76d18bf9 100644
> --- a/arch/arm/xen/mm.c
>
Hi Stephen,
> Subject: Re: [PATCH] clk: imx: imx8mm: fix audio pll setting
>
> Quoting Peng Fan (2019-07-14 19:55:43)
> > From: Peng Fan
> >
> > The AUDIO PLL max support 650M, so the original clk settings violate
> > spec. This patch makes the output 78643200
Hi Sudeep,
> Subject: Re: [PATCH v3 1/2] dt-bindings: mailbox: add binding doc for the ARM
> SMC/HVC mailbox
>
> This looks much better now.
>
> On Mon, Jul 15, 2019 at 10:10:10AM +, Peng Fan wrote:
> > From: Peng Fan
> >
> > The ARM SMC/HVC mailbox bi
Hi Rob,
> Subject: Re: [PATCH v3 1/2] dt-bindings: mailbox: add binding doc for the ARM
> SMC/HVC mailbox
>
> On Mon, Jul 15, 2019 at 4:10 AM Peng Fan wrote:
> >
> > From: Peng Fan
> >
> > The ARM SMC/HVC mailbox binding describes a firmware interface to
&g
From: Peng Fan
The ARM SMC/HVC mailbox binding describes a firmware interface to trigger
actions in software layers running in the EL2 or EL3 exception levels.
The term "ARM" here relates to the SMC instruction as part of the ARM
instruction set, not as a standard endorsed by ARM Lt
From: Peng Fan
This mailbox driver implements a mailbox which signals transmitted data
via an ARM smc (secure monitor call) instruction. The mailbox receiver
is implemented in firmware and can synchronously return data when it
returns execution to the non-secure world again.
An asynchronous
From: Peng Fan
V3:
Drop interrupt
Introduce transports for mem/reg usage
Add chan-id for mem usage
Convert to yaml format
V2:
This is a modified version from Andre Przywara's patch series
https://lore.kernel.org/patchwork/cover/812997/.
The modification are mostly:
Introduce arm,num-chans
From: Peng Fan
The AUDIO PLL max support 650M, so the original clk settings violate
spec. This patch makes the output 786432000 -> 393216000,
and 722534400 -> 361267200 to aligned with NXP vendor kernel without any
impact on audio functionality and go within 650MHz PLL limit.
Cc:
arm64 shares some code under arch/arm/xen, including mm.c.
However ZONE_DMA is removed by commit
ad67f5a6545("arm64: replace ZONE_DMA with ZONE_DMA32").
So to ARM64, need use __GFP_DMA32.
Signed-off-by: Peng Fan
---
arch/arm/xen/mm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
Hi Rob,
> Subject: Re: [PATCH V2 1/2] DT: mailbox: add binding doc for the ARM SMC
> mailbox
>
> On Mon, Jun 03, 2019 at 04:30:04PM +0800, peng@nxp.com wrote:
> > From: Peng Fan
> >
> > The ARM SMC mailbox binding describes a firmware interface to trigger
Hi All,
> Subject: Re: [PATCH V2 2/2] mailbox: introduce ARM SMC based mailbox
>
> On Tue, Jun 25, 2019 at 2:30 AM Peng Fan wrote:
> >
> > Hi Jassi
> >
> > > Subject: Re: [PATCH V2 2/2] mailbox: introduce ARM SMC based mailbox
> > >
Hi Jassi
> Subject: Re: [PATCH V2 2/2] mailbox: introduce ARM SMC based mailbox
>
> On Mon, Jun 3, 2019 at 3:28 AM wrote:
> >
> > From: Peng Fan
> >
> > This mailbox driver implements a mailbox which signals transmitted
> > data via an ARM smc (secure
Hi Sudeep,
> Subject: Re: [PATCH V2 2/2] mailbox: introduce ARM SMC based mailbox
>
> On Thu, Jun 20, 2019 at 10:21:09AM +0000, Peng Fan wrote:
> > Hi Sudeep,
> >
> > > Subject: Re: [PATCH V2 2/2] mailbox: introduce ARM SMC based mailbox
> > >
> > >
Hi Jassi,
> -Original Message-
> From: Jassi Brar [mailto:jassisinghb...@gmail.com]
> Sent: 2019年6月21日 0:50
> To: Peng Fan
> Cc: Rob Herring ; Mark Rutland
> ; Sudeep Holla ; Florian
> Fainelli ; , Sascha Hauer ;
> dl-linux-imx ; Shawn Guo ;
> feste...@gmail.c
Hi Sudeep,
> Subject: Re: [PATCH V2 2/2] mailbox: introduce ARM SMC based mailbox
>
> On Mon, Jun 03, 2019 at 04:30:05PM +0800, peng@nxp.com wrote:
> > From: Peng Fan
> >
> > This mailbox driver implements a mailbox which signals transmitted
> > data vi
Hi Rob,
> Subject: Re: [RFC 1/2] dt-bindings: imx-ocotp: Add fusable-node property
>
> On Mon, May 20, 2019 at 03:06:35AM +0000, Peng Fan wrote:
> > Introduce fusable-node property for i.MX OCOTP driver.
> > The property will only be used by Firmware(eg. U-Boot) to runtime
> >
> > > On 6/3/19 1:30 AM, peng@nxp.com wrote:
> > > > From: Peng Fan
> > > >
> > > > This mailbox driver implements a mailbox which signals transmitted
> > > > data via an ARM smc (secure monitor call) instruction. The m
> Subject: Re: linux-next: Fixes tag needs some work in the imx-mxs tree
>
> On Tue, Jun 11, 2019 at 08:36:52AM +0000, Peng Fan wrote:
> > Hi Shawn, Stephen
> > > Subject: Re: linux-next: Fixes tag needs some work in the imx-mxs
> > > tree
> > >
>
Hi Shawn, Stephen
> Subject: Re: linux-next: Fixes tag needs some work in the imx-mxs tree
>
> On Fri, Jun 07, 2019 at 07:46:52AM +1000, Stephen Rothwell wrote:
> > Hi all,
> >
> > In commit
> >
> > f6a8ff82ce68 ("clk: imx: imx8mm: correct audio_pll2_clk to
> > audio_pll2_out")
> >
> > Fixes
Hi Andre,
> Subject: Re: [PATCH V2 2/2] mailbox: introduce ARM SMC based mailbox
>
> On Mon, 3 Jun 2019 09:32:42 -0700
> Florian Fainelli wrote:
>
> Hi,
>
> > On 6/3/19 1:30 AM, peng@nxp.com wrote:
> > > From: Peng Fan
> > >
> > >
> Subject: Re: [PATCH V2 2/2] mailbox: introduce ARM SMC based mailbox
>
> On 6/3/19 1:30 AM, peng@nxp.com wrote:
> > From: Peng Fan
> >
> > This mailbox driver implements a mailbox which signals transmitted
> > data via an ARM smc (secure monitor call) inst
quot; here relates to the SMC instruction as part of the
> > > > ARM instruction set, not as a standard endorsed by ARM Ltd.
> > > >
> > > > Signed-off-by: Peng Fan
> > > > ---
> > > >
> > > > V2:
> > > > Introd
From: Peng Fan
This mailbox driver implements a mailbox which signals transmitted data
via an ARM smc (secure monitor call) instruction. The mailbox receiver
is implemented in firmware and can synchronously return data when it
returns execution to the non-secure world again.
An asynchronous
From: Peng Fan
This is a modified version from Andre Przywara's patch series
https://lore.kernel.org/patchwork/cover/812997/.
The modification are mostly:
Introduce arm,num-chans
Introduce arm_smccc_mbox_cmd
txdone_poll and txdone_irq are both set to false
arm,func-ids are kept
From: Peng Fan
The ARM SMC mailbox binding describes a firmware interface to trigger
actions in software layers running in the EL2 or EL3 exception levels.
The term "ARM" here relates to the SMC instruction as part of the ARM
instruction set, not as a standard endorsed by ARM Ltd.
Hi Shawn,
> Subject: Re: [PATCH] clk: imx: imx8mm: correct audio_pll2_clk to
> audio_pll2_out
>
> On Thu, May 30, 2019 at 01:22:57AM +0000, Peng Fan wrote:
> > Hi Stephen,
> >
> > > Subject: Re: [PATCH] clk: imx: imx8mm: correct audio_pll2_clk to
> > >
From: Peng Fan
There is no audio_pll2_clk registered, it should be audio_pll2_out.
Cc:
Fixes: ba5625c3e27 ("clk: imx: Add clock driver support for imx8mm")
Signed-off-by: Peng Fan
---
drivers/clk/imx/clk-imx8mm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
>
> > > Subject: Re: [PATCH 0/2] mailbox: arm: introduce smc triggered
> > > mailbox
> > >
> > > Hi,
> > >
> > > On 5/22/19 10:50 PM, Peng Fan wrote:
> > > > This is a modified version from Andre Przywara's patch series
>
Hi Stephen,
> Subject: Re: [PATCH] clk: imx: imx8mm: correct audio_pll2_clk to
> audio_pll2_out
>
> Quoting Shawn Guo (2019-05-23 06:22:36)
> > On Wed, May 22, 2019 at 01:34:46AM +, Peng Fan wrote:
> > > There is no audio_pll2_clk registered, it should be aud
ime disable the device tree nodes for those modules that are
> disable(fused).
>
> Signed-off-by: Peng Fan
> ---
>
> Currently NXP vendor use U-Boot to set status to disabled for devices that
> could not function,
> https://source.codeaurora.org/external/im
Hi Andre,
> Subject: Re: [PATCH 0/2] mailbox: arm: introduce smc triggered mailbox
>
> On 24/05/2019 18:56, Sudeep Holla wrote:
> > On Thu, May 23, 2019 at 10:30:50AM -0700, Florian Fainelli wrote:
>
> Hi,
>
> >> On 5/22/19 10:50 PM, Peng Fan wrote:
> >&
Hi Sudeep,
> Subject: Re: [PATCH 0/2] mailbox: arm: introduce smc triggered mailbox
>
> On Thu, May 23, 2019 at 10:30:50AM -0700, Florian Fainelli wrote:
> > Hi,
> >
> > On 5/22/19 10:50 PM, Peng Fan wrote:
> > > This is a modified version from Andre Przywara'
Hi Florian,
> Subject: Re: [PATCH 0/2] mailbox: arm: introduce smc triggered mailbox
>
> Hi,
>
> On 5/22/19 10:50 PM, Peng Fan wrote:
> > This is a modified version from Andre Przywara's patch series
> >
> https://eur01.safelinks.protection.outlook.com/?url=ht
Hi Jassi,
> Subject: Re: [PATCH 0/2] mailbox: arm: introduce smc triggered mailbox
>
> On Thu, May 23, 2019 at 12:50 AM Peng Fan wrote:
> >
> > This is a modified version from Andre Przywara's patch series
> >
> https://eur01.safelinks.protection.outlook.
Hi Shawn,
> -Original Message-
> From: Shawn Guo [mailto:shawn...@kernel.org]
> Sent: 2019年5月23日 20:53
> To: Peng Fan
> Cc: srinivas.kandaga...@linaro.org; robh...@kernel.org;
> s.ha...@pengutronix.de; feste...@gmail.com; dl-linux-imx
> ; linux-kernel@vger.kernel
From: Peng Fan
Build in CONFIG_NVMEM_IMX_OCOTP_SCU.
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Shawn Guo
Cc: Andy Gross
Cc: Maxime Ripard
Cc: Olof Johansson
Cc: Jagan Teki
Cc: Bjorn Andersson
Cc: Leonard Crestez
Cc: Marc Gonzalez
Cc: Enric Balletbo i Serra
Cc: linux-arm-ker
From: Peng Fan
Add i.MX8QXP ocotp node
Cc: Rob Herring
Cc: Mark Rutland
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Pengutronix Kernel Team
Cc: Fabio Estevam
Cc: NXP Linux Team
Cc: Anson Huang
Cc: Daniel Baluta
Cc: devicet...@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Reviewed
The ARM SMC mailbox binding describes a firmware interface to trigger
actions in software layers running in the EL2 or EL3 exception levels.
The term "ARM" here relates to the SMC instruction as part of the ARM
instruction set, not as a standard endorsed by ARM Ltd.
Signed-off-by
/patchwork/patch/812999/
Cc: Andre Przywara
Signed-off-by: Peng Fan
---
drivers/mailbox/Kconfig | 7 ++
drivers/mailbox/Makefile| 2 +
drivers/mailbox/arm-smc-mailbox.c | 154
include/linux/mailbox/arm-smc-mailbox.h | 10
/tree/scmi
Peng Fan (2):
DT: mailbox: add binding doc for the ARM SMC mailbox
mailbox: introduce ARM SMC based mailbox
.../devicetree/bindings/mailbox/arm-smc.txt| 96 +
drivers/mailbox/Kconfig| 7 +
drivers/mailbo
The rate_discrete needs to be assigned to clk->rate_discrete,
then scmi_clk_round_rate could get the value.
Fixes: 5f6c6430e904 ("firmware: arm_scmi: add initial support for clock
protocol")
Signed-off-by: Peng Fan
---
drivers/firmware/arm_scmi/clock.c | 2 ++
1 file changed,
Hi Srinivas,
> Subject: Re: [PATCH V3 2/4] nvmem: imx: add i.MX8 nvmem driver
>
>
>
> On 15/05/2019 08:53, Peng Fan wrote:
> > This patch adds i.MX8 nvmem ocotp driver to access fuse via RPC to
> > i.MX8 system controller.
> >
> > Cc: Srinivas Kandag
This patch adds i.MX8 nvmem ocotp driver to access fuse via
RPC to i.MX8 system controller.
Cc: Srinivas Kandagatla
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Pengutronix Kernel Team
Cc: Fabio Estevam
Cc: NXP Linux Team
Cc: linux-arm-ker...@lists.infradead.org
Signed-off-by: Peng Fan
---
V3:
Use
Reviewed-by: Dong Aisheng
Signed-off-by: Peng Fan
---
V3:
No change
V2:
rename patch title, add review tag
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 979a95c915b6..32b85102b857 100644
--- a/arch
: Stephen Boyd
Cc: Anson Huang
Cc: devicet...@vger.kernel.org
Reviewed-by: Rob Herring
Reviewed-by: Dong Aisheng
Signed-off-by: Peng Fan
---
V3:
Add R-b tag
V2:
Move OCOTP to end, add example, add "scu"
.../devicetree/bindings/arm/freescale/fsl,scu.txt | 22
Signed-off-by: Peng Fan
---
V3:
Add R-b tag
V2:
move address/size-cells below compatible, add "scu"
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
b/arch/arm64/boot/dts/freescale/imx8qxp.
There is no audio_pll2_clk registered, it should be audio_pll2_out.
Cc:
Fixes: ba5625c3e27 ("clk: imx: Add clock driver support for imx8mm")
Signed-off-by: Peng Fan
---
drivers/clk/imx/clk-imx8mm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/c
> Subject: Re: [RFC 1/2] dt-bindings: imx-ocotp: Add fusable-node property
>
> On 20.05.2019 06:06, Peng Fan wrote:
> > Introduce fusable-node property for i.MX OCOTP driver.
> > The property will only be used by Firmware(eg. U-Boot) to runtime
> > disable the n
Add fusable-node property for OCOTP
Signed-off-by: Peng Fan
---
arch/arm/boot/dts/imx6ull.dtsi | 7 +++
arch/arm/boot/dts/imx6ulz.dtsi | 6 ++
2 files changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi
index 22e4a307fa59..b616ed6ee4bf
for the serval parts, instead
we could provide one device tree and let Firmware to runtime disable
the device tree nodes for those modules that are disable(fused).
Signed-off-by: Peng Fan
---
Currently NXP vendor use U-Boot to set status to disabled for devices
that could not function,
https
To Frac pll, the gate shift is 13, however to Int PLL the gate shift
is 11.
Cc:
Fixes: ba5625c3e27 ("clk: imx: Add clock driver support for imx8mm")
Signed-off-by: Peng Fan
Reviewed-by: Fabio Estevam
Reviewed-by: Jacky Bai
---
V3:
Move Fixes Tag to correct place
V2:
Upd
Fixes: ba5625c3e27 ("clk: imx: Add clock driver support for imx8mm")
To Frac pll, the gate shift is 13, however to Int PLL the gate shift
is 11.
Cc:
Signed-off-by: Peng Fan
Reviewed-by: Fabio Estevam
Reviewed-by: Jacky Bai
---
V2:
Update commit with Fixes, Add R-b and cc stable
To Frac pll, the gate shift is 13, however to Int PLL the gate shift
is 11.
Signed-off-by: Peng Fan
Reviewed-by: Jacky Bai
---
drivers/clk/imx/clk-imx8mm.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk
This patch adds i.MX8 nvmem ocotp driver to access fuse via
RPC to i.MX8 system controller.
Cc: Srinivas Kandagatla
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Pengutronix Kernel Team
Cc: Fabio Estevam
Cc: NXP Linux Team
Cc: linux-arm-ker...@lists.infradead.org
Signed-off-by: Peng Fan
---
V3:
Use
: Stephen Boyd
Cc: Anson Huang
Cc: devicet...@vger.kernel.org
Reviewed-by: Rob Herring
Reviewed-by: Dong Aisheng
Signed-off-by: Peng Fan
---
V3:
Add R-b tag
V2:
Move OCOTP to end, add example, add "scu"
.../devicetree/bindings/arm/freescale/fsl,scu.txt | 22
Signed-off-by: Peng Fan
---
V3:
Add R-b tag
V2:
move address/size-cells below compatible, add "scu"
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
b/arch/arm64/boot/dts/freescale/imx8qxp.
Reviewed-by: Dong Aisheng
Signed-off-by: Peng Fan
---
V3:
No change
V2:
rename patch title, add review tag
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 979a95c915b6..32b85102b857 100644
--- a/arch
Hi Aisheng,
> Subject: RE: [PATCH V2 2/4] nvmem: imx: add i.MX8 nvmem driver
>
> > From: Peng Fan
> > Sent: Wednesday, May 8, 2019 10:56 AM
> >
> > This patch adds i.MX8 nvmem ocotp driver to access fuse via RPC to
> > i.MX8 system controller.
> >
>
-by: Peng Fan
---
V2:
move address/size-cells below compatible, add "scu"
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 0683ee2a48ae..72
Reviewed-by: Dong Aisheng
Signed-off-by: Peng Fan
---
V2:
rename patch title, add review tag
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index eb31c20e9914..9d8a512fc3d5 100644
--- a/arch/arm64/configs
Cc: Shawn Guo
Cc: Ulf Hansson
Cc: Stephen Boyd
Cc: Anson Huang
Cc: devicet...@vger.kernel.org
Signed-off-by: Peng Fan
---
V2:
Move OCOTP to end, add example, add "scu"
.../devicetree/bindings/arm/freescale/fsl,scu.txt | 22 ++
1 file changed, 22 insertions(+)
This patch adds i.MX8 nvmem ocotp driver to access fuse via
RPC to i.MX8 system controller.
Cc: Srinivas Kandagatla
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Pengutronix Kernel Team
Cc: Fabio Estevam
Cc: NXP Linux Team
Cc: linux-arm-ker...@lists.infradead.org
Signed-off-by: Peng Fan
---
V2:
Add
Hi Aisheng,
> Subject: RE: [PATCH 1/4] dt-bindings: fsl: scu: add ocotp binding
>
> > From: Peng Fan
> > Sent: Sunday, May 5, 2019 9:28 PM
> >
> > NXP i.MX8QXP is an ARMv8 SoC with a Cortex-M4 core inside as system
> > controller(SCU), the ocotp controller is
Hi Aisheng,
> Subject: RE: [PATCH 2/4] nvmem: imx: add i.MX8 nvmem driver
>
> > From: Peng Fan
> > Sent: Sunday, May 5, 2019 9:28 PM
> > Subject: [PATCH 2/4] nvmem: imx: add i.MX8 nvmem driver
> >
> > This patch adds i.MX8 nvmem ocotp driver to access fuse vi
Build in CONFIG_NVMEM_IMX_OCOTP_SCU.
Signed-off-by: Peng Fan
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Shawn Guo
Cc: Andy Gross
Cc: Maxime Ripard
Cc: Olof Johansson
Cc: Jagan Teki
Cc: Bjorn Andersson
Cc: Leonard Crestez
Cc: Marc Gonzalez
Cc: Enric Balletbo i Serra
Cc: linux-arm-ker
Add i.MX8QXP ocotp node
Signed-off-by: Peng Fan
Cc: Rob Herring
Cc: Mark Rutland
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Pengutronix Kernel Team
Cc: Fabio Estevam
Cc: NXP Linux Team
Cc: Aisheng Dong
Cc: Anson Huang
Cc: Daniel Baluta
Cc: devicet...@vger.kernel.org
Cc: linux-arm-ker
This patch adds i.MX8 nvmem ocotp driver to access fuse via
RPC to i.MX8 system controller.
Signed-off-by: Peng Fan
Cc: Srinivas Kandagatla
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Pengutronix Kernel Team
Cc: Fabio Estevam
Cc: NXP Linux Team
Cc: linux-arm-ker...@lists.infradead.org
---
drivers
NXP i.MX8QXP is an ARMv8 SoC with a Cortex-M4 core inside as
system controller(SCU), the ocotp controller is being controlled
by the SCU, so Linux need use RPC to SCU for ocotp handling. This
patch adds binding doc for i.MX8 SCU OCOTP driver.
Signed-off-by: Peng Fan
Cc: Rob Herring
Cc: Mark
It does not make sense to only get value from pll->base and assign
to a local variable when recalc_rate.
Signed-off-by: Peng Fan
---
drivers/clk/imx/clk-pll14xx.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/
Hi Adrian,
>
> On 16/04/19 9:48 AM, Peng Fan wrote:
> > On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card
> > as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let the
> > the 1st linux configure power/clock for the 2nd Linux.
&g
: sdhci: ADMA Err: 0x | ADMA Ptr: 0x
Signed-off-by: Peng Fan
---
drivers/mmc/host/cqhci.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/mmc/host/cqhci.c b/drivers/mmc/host/cqhci.c
index d59cb0a51964..4f41960ac7ad 100644
--- a/drivers/mmc/host/cqhci.c
+++ b/drivers
There is no function named munlock_vma_pages, correct it to
munlock_vma_page.
Signed-off-by: Peng Fan
---
mm/swap.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/mm/swap.c b/mm/swap.c
index 301ed4e04320..3a75722e68a9 100644
--- a/mm/swap.c
+++ b/mm/swap.c
@@ -867,7 +867,7
Hi Shawn,
> -Original Message-
> From: Aisheng Dong
> Sent: 2019年3月15日 18:24
> To: Peng Fan ; robh...@kernel.org;
> mark.rutl...@arm.com; shawn...@kernel.org; s.ha...@pengutronix.de;
> ker...@pengutronix.de; feste...@gmail.com; dl-linux-imx
> ; Anson Huang ; Dani
Hi Shawn,
> -Original Message-
> From: Aisheng Dong
> Sent: 2019年3月15日 18:24
> To: Peng Fan ; robh...@kernel.org;
> mark.rutl...@arm.com; shawn...@kernel.org; s.ha...@pengutronix.de;
> ker...@pengutronix.de; feste...@gmail.com; dl-linux-imx
> ; Anson Huang ; Dani
> -Original Message-
> From: Fabio Estevam [mailto:feste...@gmail.com]
> Sent: 2019年3月19日 21:14
> To: Peng Fan
> Cc: Russell King - ARM Linux admin ;
> nicolas.pi...@linaro.org; r...@kernel.org; mho...@suse.com;
> a...@arndb.de; linux-kernel@vger.kernel.org; ros
> -Original Message-
> From: Aisheng Dong
> Sent: 2019年3月15日 21:40
> To: Peng Fan ; shawn...@kernel.org;
> s.ha...@pengutronix.de; ker...@pengutronix.de; feste...@gmail.com;
> dl-linux-imx ; Anson Huang ;
> a...@arndb.de; linux-arm-ker...@lists.infradea
Hi Russell,
> -Original Message-
> From: Russell King - ARM Linux admin [mailto:li...@armlinux.org.uk]
> Sent: 2019年2月13日 1:27
> To: Peng Fan
> Cc: a...@arndb.de; r...@linux.vnet.ibm.com; r...@kernel.org;
> f.faine...@gmail.com; a...@linux-foundation.org; mho..
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