The following commit has been merged into the irq/irqchip-next branch of
irqchip:
Commit-ID: 5deaa1d7c49151988b0bf919eeea6ad5535a29a2
Gitweb:
https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/5deaa1d7c49151988b0bf919eeea6ad5535a29a2
Author:Rajendra Nayak
On 3/31/2021 2:49 AM, Doug Anderson wrote:
Hi,
On Wed, Mar 24, 2021 at 10:45 PM Rajendra Nayak wrote:
@@ -111,6 +113,15 @@ static const struct qfprom_soc_compatible_data
sc7180_qfprom = {
.nkeepout = ARRAY_SIZE(sc7180_qfprom_keepout)
};
+static const struct nvmem_keepout
On 2/5/2021 8:25 PM, Doug Anderson wrote:
Hi,
On Fri, Feb 5, 2021 at 3:29 AM Ravi Kumar Bokka wrote:
QFPROM controller hardware requires 1.8V min for fuse blowing.
So, this change sets the voltage to 1.8V, required to blow the fuse
for qfprom-efuse controller.
To disable fuse blowing, we
Handle the differences across LDO voltage needed for blowing fuses,
and the blow timer value, identified using a minor version of 15
on sc7280.
Signed-off-by: Rajendra Nayak
Signed-off-by: Ravi Kumar Bokka
---
Applies on top of https://lore.kernel.org/patchwork/patch/1376175/
drivers/nvmem
Document SoC compatible for sc7280
Signed-off-by: Rajendra Nayak
---
Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
From: Sai Prakash Ranjan
Add compatible for watchdog timer on SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
Acked-by: Rob Herring
---
This was earlier posted as part of the entire DT series for sc7280 [1]
Rest of the patches are now
From: Sai Prakash Ranjan
Add the SoC specific compatible for SC7280 implementing
arm,mmu-500.
Signed-off-by: Sai Prakash Ranjan
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
Acked-by: Rob Herring
---
This was earlier posted as part of the entire DT series for sc7280 [1]
Rest
Add the compatible string for sc7280 SoC from Qualcomm
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
Acked-by: Rob Herring
---
This was earlier posted as part of the entire DT series for sc7280 [1]
Rest of the patches are now picked, posting this separately so it can
be picked up via
Add compatible for sc7280 SoC
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/firmware/qcom,scm.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt
b/Documentation
On 3/11/2021 2:45 PM, Rajendra Nayak wrote:
On 3/11/2021 5:43 AM, Bjorn Andersson wrote:
On Fri 12 Feb 01:28 CST 2021, Rajendra Nayak wrote:
This series includes a few minor binding updates and base device tree
files (to boot to shell) for SC7280 SoC and the IDP board using this SoC
From: Maulik Shah
Add cpuidle states for little and big cpus.
The latency values are preliminary placeholders and will be updated
once testing provides the real numbers.
Signed-off-by: Maulik Shah
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sc7280
From: satya priya
Add SPMI PMIC arbiter device to communicate with PMICs
attached to SPMI bus.
Signed-off-by: satya priya
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom
Add rpmhcc clock controller node for SC7280. Also add references to
rpmhcc clocks in gcc.
Signed-off-by: Taniya Das
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64
Add the DT node for the rpmhpd power controller on SC7280 SoCs.
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 47
1 file changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b
From: Sai Prakash Ranjan
Add compatible for watchdog timer on SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml | 1 +
1 file changed, 1 insertion(+)
diff
From: Maulik Shah
Add fw reserved memory area for CPUCP (CPUSS control
processor) and AOP (Always ON processor)
Signed-off-by: Maulik Shah
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot
From: Sai Prakash Ranjan
Add APSS (Application Processor Subsystem) watchdog
DT node for SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git
From: Sai Prakash Ranjan
Adding device node for APPS SMMU available on SC7280 chipset.
This is shared among the multiple client devices such as
display, video, usb, mmc and others.
Signed-off-by: Sai Prakash Ranjan
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 89
Add initial device tree support for the sc7280 SoC and the IDP
boards based on this SoC
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sc7280-idp.dts | 47 +
arch/arm64/boot/dts/qcom/sc7280.dtsi
From: Sai Prakash Ranjan
Add the SoC specific compatible for SC7280 implementing
arm,mmu-500.
Signed-off-by: Sai Prakash Ranjan
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 +
1 file changed, 1
From: Maulik Shah
Add PDC interrupt controller along with apps RSC device.
Also add reserved memory for command_db.
Signed-off-by: Maulik Shah
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 44
1 file changed, 44 insertions
Add the compatible string for sc7180 SoC from Qualcomm
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings
cpuidle states
Rajendra Nayak (6):
dt-bindings: arm: qcom: Document sc7280 SoC and board
dt-bindings: firmware: scm: Add sc7280 support
arm64: dts: sc7280: Add basic dts/dtsi files for sc7280 soc
dt-bindings: qcom,pdc: Add compatible for sc7280
arm64: dts: qcom: SC7280: Add rpmhcc clock
Document the sc7280 SoC and the IDP board bindings
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml
b
On 3/4/2021 5:37 AM, Stephen Boyd wrote:
Quoting Rajendra Nayak (2021-03-03 04:17:47)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
new file mode 100644
index 000..4a56d9c
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -0,0 +1,299
On 3/11/2021 5:43 AM, Bjorn Andersson wrote:
On Fri 12 Feb 01:28 CST 2021, Rajendra Nayak wrote:
This series includes a few minor binding updates and base device tree
files (to boot to shell) for SC7280 SoC and the IDP board using this SoC.
The series is dependent on a few driver patches
On 2/23/2021 1:09 PM, Stephen Boyd wrote:
Quoting Rajendra Nayak (2021-02-11 23:28:41)
Add the compatible string for sc7180 SoC from Qualcomm
Signed-off-by: Rajendra Nayak
---
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt | 1 +
Is this being YAML-ified at some
On 3/4/2021 5:43 AM, Stephen Boyd wrote:
Quoting Rajendra Nayak (2021-03-03 04:17:57)
From: Maulik Shah
Add cpuidle states for little and big cpus.
Please also say "The latency values are preliminary placeholders and will be
updated
once testing provides the real numbers".
On 3/4/2021 5:42 AM, Stephen Boyd wrote:
Quoting Rajendra Nayak (2021-03-03 04:17:56)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index fe4fdb9..aa6f847 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
On 3/4/2021 5:34 AM, Stephen Boyd wrote:
Quoting Rajendra Nayak (2021-03-03 04:17:49)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 4a56d9c..21c2399 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
Add the DT node for the rpmhpd power controller on SC7280 SoCs.
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 47
1 file changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom
From: Maulik Shah
Add cpuidle states for little and big cpus.
Signed-off-by: Maulik Shah
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 78
1 file changed, 78 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b
From: Sai Prakash Ranjan
Add compatible for watchdog timer on SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
---
Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation
From: Sai Prakash Ranjan
Adding device node for APPS SMMU available on SC7280 chipset.
This is shared among the multiple client devices such as
display, video, usb, mmc and others.
Signed-off-by: Sai Prakash Ranjan
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 89
From: Sai Prakash Ranjan
Add APSS (Application Processor Subsystem) watchdog
DT node for SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git
From: Sai Prakash Ranjan
Add the SoC specific compatible for SC7280 implementing
arm,mmu-500.
Signed-off-by: Sai Prakash Ranjan
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
From: satya priya
Add SPMI PMIC arbiter device to communicate with PMICs
attached to SPMI bus.
Signed-off-by: satya priya
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom
From: Maulik Shah
Add fw reserved memory area for CPUCP (CPUSS control
processor) and AOP (Always ON processor)
Signed-off-by: Maulik Shah
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot
From: Maulik Shah
Add PDC interrupt controller along with apps RSC device.
Also add reserved memory for command_db.
Signed-off-by: Maulik Shah
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 44
1 file changed, 44 insertions
Add rpmhcc clock controller node for SC7280. Also add references to
rpmhcc clocks in gcc.
Signed-off-by: Taniya Das
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
Add the compatible string for sc7180 SoC from Qualcomm
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
---
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/interrupt-controller
Add compatible for sc7280 SoC
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
---
Documentation/devicetree/bindings/firmware/qcom,scm.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt
b/Documentation/devicetree/bindings
Document the sc7280 SoC and the IDP board bindings
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
---
Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml
b/Documentation/devicetree
Add initial device tree support for the sc7280 SoC and the IDP
boards based on this SoC
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sc7280-idp.dts | 47 +
arch/arm64/boot/dts/qcom/sc7280.dtsi
cpuidle states
Rajendra Nayak (6):
dt-bindings: arm: qcom: Document sc7280 SoC and board
dt-bindings: firmware: scm: Add sc7280 support
arm64: dts: sc7280: Add basic dts/dtsi files for sc7280 soc
dt-bindings: qcom,pdc: Add compatible for sc7280
arm64: dts: qcom: SC7280: Add rpmhcc clock
Add the power domains exposed by RPMH in the Qualcomm Technologies Inc
sc7280 platform
Signed-off-by: Rajendra Nayak
---
drivers/soc/qcom/rpmhpd.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c
index 7ce0635
Add compatible and constants for the power domains exposed by the RPMH
in the Qualcomm Technologies Inc sc7280 platform.
Signed-off-by: Rajendra Nayak
---
Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 +
include/dt-bindings/power/qcom-rpmpd.h | 11 +++
2
The offsets for SDC_QDSD_PINGROUP and UFS_RESET were off by 0x10
due to an issue in the scripts generating the data.
Fixes: ecb454594c43: ("pinctrl: qcom: Add sc7280 pinctrl driver")
Reported-by: Veerabhadrarao Badiganti
Signed-off-by: Rajendra Nayak
---
drivers/pinctrl/qc
Fix SDC1_RCLK configurations which are in a different register so fix the
offset from 0xb3000 to 0xb3004.
Fixes: ecb454594c43: ("pinctrl: qcom: Add sc7280 pinctrl driver")
Reported-by: Veerabhadrarao Badiganti
Signed-off-by: Rajendra Nayak
---
drivers/pinctrl/qcom/pinctrl-sc7280.c
On 2/23/2021 1:15 PM, Stephen Boyd wrote:
Quoting Rajendra Nayak (2021-02-11 23:28:46)
From: Maulik Shah
Add fw reserved memory area for CPUCP and AOP.
Does CPUCP stand for CPU Content Protection? AOP is Always On Processor.
It would help if the commit text told us what these acronyms
On 2/23/2021 1:07 PM, Stephen Boyd wrote:
Quoting Rajendra Nayak (2021-02-11 23:28:40)
Add initial device tree support for the SC7280 SoC and the IDP
boards based on this SoC
Signed-off-by: Rajendra Nayak
---
Reviewed-by: Stephen Boyd
diff --git a/arch/arm64/boot/dts/qcom/sc7280
From: Sai Prakash Ranjan
Add compatible for watchdog timer on SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan
Signed-off-by: Rajendra Nayak
---
Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings
From: Sai Prakash Ranjan
Add APSS (Application Processor Subsystem) watchdog
DT node for SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom
From: Maulik Shah
Add cpuidle states for little and big cpus.
Signed-off-by: Maulik Shah
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 78
1 file changed, 78 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b
Add the compatible string for sc7180 SoC from Qualcomm
Signed-off-by: Rajendra Nayak
---
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
b/Documentation
From: Sai Prakash Ranjan
Adding device node for APPS SMMU available on SC7280 chipset.
This is shared among the multiple client devices such as
display, video, usb, mmc and others.
Signed-off-by: Sai Prakash Ranjan
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 89
From: satya priya
Add SPMI PMIC arbiter device to communicate with PMICs
attached to SPMI bus.
Signed-off-by: satya priya
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom
From: Maulik Shah
Add fw reserved memory area for CPUCP and AOP.
Signed-off-by: Maulik Shah
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom
From: Sai Prakash Ranjan
Add the SoC specific compatible for SC7280 implementing
arm,mmu-500.
Signed-off-by: Sai Prakash Ranjan
Signed-off-by: Rajendra Nayak
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree
Add rpmhcc clock controller node for SC7280. Also add the 'fixed
clock' nodes which can now be referenced in gcc.
Signed-off-by: Taniya Das
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 55
1 file changed, 55 insertions(+)
diff
=484517
https://lore.kernel.org/patchwork/project/lkml/list/?series=484489
https://lore.kernel.org/patchwork/patch/1379831/
Maulik Shah (3):
arm64: dts: qcom: sc7280: Add RSC and PDC devices
arm64: dts: qcom: Add reserved memory for fw
arm64: dts: qcom: sc7280: Add cpuidle states
Rajendra
Add initial device tree support for the SC7280 SoC and the IDP
boards based on this SoC
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sc7280-idp.dts | 47 +
arch/arm64/boot/dts/qcom/sc7280.dtsi| 294
Add compatible for SC7280 SoC
Signed-off-by: Rajendra Nayak
---
Documentation/devicetree/bindings/firmware/qcom,scm.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt
b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
index
From: Maulik Shah
Add PDC interrupt controller along with apps RSC device.
Also add reserved memory for command_db.
Signed-off-by: Maulik Shah
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 44
1 file changed, 44 insertions
Document the SC7280 SoC and the IDP board bindings
Signed-off-by: Rajendra Nayak
---
Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml
b/Documentation/devicetree/bindings/arm/qcom.yaml
index
From: Maulik Shah
GPIOs that can be configured as wakeup sources, have their
interrupt lines routed to PDC interrupt controller.
Provide the interrupt map of the GPIO to its wakeup capable
interrupt parent.
Signed-off-by: Maulik Shah
Signed-off-by: Rajendra Nayak
---
drivers/pinctrl/qcom
On 1/15/2021 9:45 PM, Bjorn Andersson wrote:
On Thu 24 Dec 05:12 CST 2020, Roja Rani Yarubandi wrote:
While most devices within power-domains which support performance states,
scale the performance state dynamically, some devices might want to
set a static/default performance state while the
On 1/15/2021 8:13 PM, Bjorn Andersson wrote:
On Thu 24 Dec 05:12 CST 2020, Roja Rani Yarubandi wrote:
@@ -629,6 +658,16 @@ static int __maybe_unused geni_i2c_runtime_suspend(struct
device *dev)
struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
disable_irq(gi2c->irq);
+
+
orks well for them and there isn't
some other phantom interrupt source that I'm not aware of.
I currently don;t have access to any non-PDC hardware, so could not really do
any real tests, but the changes seem sane, so
Reviewed-by: Rajendra Nayak
Changes in v4:
- ("pinctrl: qcom: Don'
Add device tree binding Documentation details for Qualcomm SC7280
TLMM block.
Signed-off-by: Rajendra Nayak
Reviewed-by: Rob Herring
---
v2: Consolidated functions under phase_flag and qdss
.../bindings/pinctrl/qcom,sc7280-pinctrl.yaml | 158 +
1 file changed, 158
Add initial pinctrl driver to support pin configuration with
pinctrl framework for SC7280 SoC
Signed-off-by: Rajendra Nayak
---
v2: Consolidated functions under phase_flag and qdss
Moved ufs reset pin to pin175 so its exposed as a gpio
npios updated from 175 to 176
drivers/pinctrl/qcom
, that seems like the right thing to do. Sorry, looks like I hadn't
really tested the cleanup path by loading/unloading the module :/
Reviewed-by: Rajendra Nayak
Fixes: 9a538b83612c ('media: venus: core: Add support for opp tables/perf
voting')
Signed-off-by: Stanimir Varbanov
---
drivers/media
On 10/29/2020 7:50 PM, Bjorn Andersson wrote:
On Fri 16 Oct 01:58 CDT 2020, Rajendra Nayak wrote:
diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280.c
b/drivers/pinctrl/qcom/pinctrl-sc7280.c
[..]
+static const struct msm_function sc7280_functions[] = {
[..]
+ FUNCTION(phase_flag0
Add initial pinctrl driver to support pin configuration with
pinctrl framework for SC7280 SoC
Signed-off-by: Rajendra Nayak
---
drivers/pinctrl/qcom/Kconfig |9 +
drivers/pinctrl/qcom/Makefile |1 +
drivers/pinctrl/qcom/pinctrl-sc7280.c | 1717
Add device tree binding Documentation details for Qualcomm SC7280
TLMM block.
Signed-off-by: Rajendra Nayak
---
.../bindings/pinctrl/qcom,sc7280-pinctrl.yaml | 170 +
1 file changed, 170 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/qcom
On 10/4/2020 3:56 AM, Kuogee Hsieh wrote:
Set link rate by using OPP set rate api so that CX level will be set
accordingly based on the link rate.
Changes in v2:
-- remove dev from dp_ctrl_put() parameters
-- address review comments
This needs to go below '---' and should not be part of the
On 9/30/2020 1:54 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2020-09-29 10:10:26)
Set link rate by using OPP set rate api so that CX level will be set
accordingly base on the link rate.
s/base/based/
Signed-off-by: Kuogee Hsieh
---
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c
On 9/30/2020 7:34 PM, Lukasz Luba wrote:
On 9/30/20 11:55 AM, Rajendra Nayak wrote:
On 9/30/2020 1:55 PM, Lukasz Luba wrote:
Hi Douglas,
On 9/30/20 12:53 AM, Doug Anderson wrote:
Hi,
On Tue, Sep 29, 2020 at 5:16 AM Lukasz Luba wrote:
The Energy Model (EM) can store power values
On 9/30/2020 1:55 PM, Lukasz Luba wrote:
Hi Douglas,
On 9/30/20 12:53 AM, Doug Anderson wrote:
Hi,
On Tue, Sep 29, 2020 at 5:16 AM Lukasz Luba wrote:
The Energy Model (EM) can store power values in milli-Watts or in abstract
scale. This might cause issues in the subsystems which use the
On 9/1/2020 7:50 PM, Rajendra Nayak wrote:
Rob, can you pick PATCH 1 since its already reviewed by you.
Stan, Patch 2 and 3 will need to be picked by you and they both have your ACKs
Rob/Stan, any plans to get the patches merged for 5.10?
Patch 4 and 5 will need to be merged via the qcom
On 9/3/2020 10:14 AM, Rajendra Nayak wrote:
On 9/2/2020 9:02 PM, Doug Anderson wrote:
Hi,
On Tue, Sep 1, 2020 at 10:36 PM Rajendra Nayak wrote:
* In terms of the numbers here, I believe that you're claiming that we
can dissipate 768 mW * 6 + 1202 mW * 2 = ~7 Watts of power. My memory
On 9/2/2020 9:02 PM, Doug Anderson wrote:
Hi,
On Tue, Sep 1, 2020 at 10:36 PM Rajendra Nayak wrote:
* In terms of the numbers here, I believe that you're claiming that we
can dissipate 768 mW * 6 + 1202 mW * 2 = ~7 Watts of power. My memory
of how much power we could dissipate
I'm not massively familiar with this area of the code, but I guess I
shouldn't let that stop me from having an opinion! :-P
* I would agree that it seems highly unlikely that someone would put
one of these chips in a device that could only dissipate the heat from
the lowest OPP, so having
* In terms of the numbers here, I believe that you're claiming that we
can dissipate 768 mW * 6 + 1202 mW * 2 = ~7 Watts of power. My memory
of how much power we could dissipate in previous laptops I worked on
is a little fuzzy, but that doesn't seem insane for a passively-cooled
laptop.
Post a successful pm_ops->core_get, an error in probe
should exit by doing a pm_ops->core_put which seems
to be missing. So fix it.
Signed-off-by: Rajendra Nayak
Acked-by: Stanimir Varbanov
Reviewed-by: Bjorn Andersson
---
drivers/media/platform/qcom/venus/core.c | 15 ++-
of https://lore.kernel.org/patchwork/patch/1241077/
These patches add DVFS support for Venus
Rajendra Nayak (5):
dt-bindings: media: venus: Add an optional power domain for perf
voting
media: venus: core: Fix error handling in probe
media: venus: core: Add support for opp tables/perf voting
impact the functionality but just makes
the platform a little less power efficient.
Signed-off-by: Rajendra Nayak
Reviewed-by: Rob Herring
Reviewed-by: Bjorn Andersson
---
Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml| 6 +-
Documentation/devicetree/bindings/media/qcom
Add the OPP tables in order to be able to vote on the performance state
of a power-domain
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 35 +--
1 file changed, 33 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom
Add support to add OPP tables and perf voting on the OPP powerdomain.
This is needed so venus votes on the corresponding performance state
for the OPP powerdomain along with setting the core clock rate.
Signed-off-by: Rajendra Nayak
Reviewed-by: Matthias Kaehlcke
Acked-by: Stanimir Varbanov
Add the OPP tables in order to be able to vote on the performance state of
a power-domain.
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 40 ++--
1 file changed, 38 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom
On 9/1/2020 2:08 PM, Viresh Kumar wrote:
On 01-09-20, 13:01, Rajendra Nayak wrote:
So FWIU, dpu_unbind() gets called even when dpu_bind() fails for some reason.
Ahh, I see.
I tried to address that earlier [1] which I realized did not land.
I don't think that patch was required, as you
On 8/28/2020 11:37 AM, Viresh Kumar wrote:
dev_pm_opp_of_remove_table() doesn't report any errors when it fails to
find the OPP table with error -ENODEV (i.e. OPP table not present for
the device). And we can call dev_pm_opp_of_remove_table()
unconditionally here.
Its a little tricky to call
On 8/20/2020 1:26 PM, Viresh Kumar wrote:
Hi,
Here is another version of the cleanups I sent earlier.
Rajendra: Please see if these work fine now.
I gave these a quick spin, and they don';t result in the crash I
earlier observed
Tested-by: Rajendra Nayak
V3:
- Dropped v2 1/4
On 8/13/2020 9:59 AM, Viresh Kumar wrote:
The common "enabled" flag can be used here instead of
"regulator_enabled" now.
Signed-off-by: Viresh Kumar
---
drivers/opp/core.c | 13 +++--
drivers/opp/opp.h | 2 --
2 files changed, 3 insertions(+), 12 deletions(-)
diff --git
On 8/13/2020 9:59 AM, Viresh Kumar wrote:
On 11-08-20, 14:09, Stephen Boyd wrote:
This is a goto maze! Any chance we can clean this up?
I have sent a short series in reply to this series, please have a
look. It should look better now.
Thanks, I was out a few days so could not get to the
such that it now matches with the
production rev of sdm845 SoC.
Fixes: 13cadb34e593 ("arm64: dts: sdm845: Add OPP table for all qup
devices")
Reported-by: John Stultz
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +++--
1 file changed, 7 insertions(+), 2
On 8/12/2020 1:09 PM, Rajendra Nayak wrote:
On 8/12/2020 1:05 PM, Amit Pundir wrote:
Hi Rajendra,
On Wed, 12 Aug 2020 at 11:18, Rajendra Nayak wrote:
On 8/12/2020 7:03 AM, John Stultz wrote:
On Tue, Aug 11, 2020 at 4:11 PM John Stultz wrote:
On Wed, Mar 20, 2019 at 2:49 AM Rajendra
On 8/12/2020 1:05 PM, Amit Pundir wrote:
Hi Rajendra,
On Wed, 12 Aug 2020 at 11:18, Rajendra Nayak wrote:
On 8/12/2020 7:03 AM, John Stultz wrote:
On Tue, Aug 11, 2020 at 4:11 PM John Stultz wrote:
On Wed, Mar 20, 2019 at 2:49 AM Rajendra Nayak wrote:
geni serial needs to express
On 8/12/2020 2:58 AM, Stephen Boyd wrote:
We get the opp_table pointer at the top of the function and so we should
put the pointer at the end of the function like all other exit paths
from this function do.
Cc: Rajendra Nayak
Fixes: aca48b61f963 ("opp: Manage empty OPP tables with clk h
On 8/12/2020 7:03 AM, John Stultz wrote:
On Tue, Aug 11, 2020 at 4:11 PM John Stultz wrote:
On Wed, Mar 20, 2019 at 2:49 AM Rajendra Nayak wrote:
geni serial needs to express a perforamnce state requirement on CX
depending on the frequency of the clock rates. Use OPP table from
DT
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