[PATCH v2 00/10] irqdomain, gic-v3-its: Implement late irq domain initialization

in irq_domain_handle_requests() * add comment that describes this check in irq_domain_handle_ requests() Robert Richter (10): irqdomain: Add interface to request an irq domain irqchip/gic-v3-its-platform-msi: Remove domain init order dependencies irqchip/irq-gic-v3-its-pci-msi: Remove domain init

[PATCH 2/2] irqchip/gic-v3-its: Use CMA for allocation of large device tables

-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its.c | 113 --- 1 file changed, 82 insertions(+), 31 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index a4b1b2fcb60f..6ba221aa27b9 100644 --- a/drivers/irqchip/irq

[PATCH 2/2] irqchip/gic-v3-its: Use CMA for allocation of large device tables

-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its.c | 113 --- 1 file changed, 82 insertions(+), 31 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index a4b1b2fcb60f..6ba221aa27b9 100644 --- a/drivers/irqchip/irq

[PATCH 1/2] irqchip/gic-v3-its: Handle its nodes as kernel devices

Manage its nodes as kernel devices. We can then use the kernel's device resource management for memory allocation. Freeing memory becomes much easier now. This also allows us to use CMA for the allocation of large its tables. Signed-off-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its.c

[PATCH 1/2] irqchip/gic-v3-its: Handle its nodes as kernel devices

Manage its nodes as kernel devices. We can then use the kernel's device resource management for memory allocation. Freeing memory becomes much easier now. This also allows us to use CMA for the allocation of large its tables. Signed-off-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its.c

[PATCH 0/2] irqchip/gic-v3-its: Use CMA for its table allocation

the release of resources (devres used) and device based messages (dev_* printk variants used). The new its table allocator still uses the old scheme for small tables to allow a further rework that supports NUMA-aware its tables. Robert Richter (2): irqchip/gic-v3-its: Handle its nodes as kernel

[PATCH 0/2] irqchip/gic-v3-its: Use CMA for its table allocation

the release of resources (devres used) and device based messages (dev_* printk variants used). The new its table allocator still uses the old scheme for small tables to allow a further rework that supports NUMA-aware its tables. Robert Richter (2): irqchip/gic-v3-its: Handle its nodes as kernel

[PATCH 07/10] irqchip/gic-v3-its: Split probing from its node initialization

To initialize the its nodes at a later point during boot, we need to split probing from initialization. Collect all information required for initialization in struct its_node. We can then use the its node list for initialization. Signed-off-by: Robert Richter --- drivers/irqchip/irq-gic-v3

[PATCH 08/10] irqchip/gic-v3-its: Decouple its initialization from gic

This patch separates its initialization from the gic. Probing and initialization of its nodes is separate now. There is an own cpu notifier for its now. Signed-off-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its.c | 58 +- drivers/irqchip/irq-gic-v3.c

[PATCH 07/10] irqchip/gic-v3-its: Split probing from its node initialization

To initialize the its nodes at a later point during boot, we need to split probing from initialization. Collect all information required for initialization in struct its_node. We can then use the its node list for initialization. Signed-off-by: Robert Richter --- drivers/irqchip/irq-gic-v3

[PATCH 08/10] irqchip/gic-v3-its: Decouple its initialization from gic

This patch separates its initialization from the gic. Probing and initialization of its nodes is separate now. There is an own cpu notifier for its now. Signed-off-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its.c | 58 +- drivers/irqchip/irq-gic-v3.c

[PATCH 06/10] irqchip/gic-v3-its: Initialize its nodes in probe order

ATM the last discovered node is initialized first. Though this order should work too, change the initialization of nodes to probe order as one would expect it. Signed-off-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH 10/10] irqchip/gic-v3-its: Initialize MSIs with subsys_initcalls

Since ITS is initialized with with the subsys_initcall now, we don't need to enable ITS children earlier. Due to the use of irq_domain_ request_host_*() there are no order dependencies when initializing irq domains. Signed-off-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c

[PATCH 05/10] fsl-mc/dprc-driver: Remove domain init order dependencies

-by: Robert Richter --- drivers/bus/fsl-mc/dprc-driver.c | 41 drivers/bus/fsl-mc/fsl-mc-msi.c | 6 +- 2 files changed, 42 insertions(+), 5 deletions(-) diff --git a/drivers/bus/fsl-mc/dprc-driver.c b/drivers/bus/fsl-mc/dprc-driver.c index 52c7e15143d6

[PATCH 06/10] irqchip/gic-v3-its: Initialize its nodes in probe order

ATM the last discovered node is initialized first. Though this order should work too, change the initialization of nodes to probe order as one would expect it. Signed-off-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH 10/10] irqchip/gic-v3-its: Initialize MSIs with subsys_initcalls

Since ITS is initialized with with the subsys_initcall now, we don't need to enable ITS children earlier. Due to the use of irq_domain_ request_host_*() there are no order dependencies when initializing irq domains. Signed-off-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c

[PATCH 05/10] fsl-mc/dprc-driver: Remove domain init order dependencies

-by: Robert Richter --- drivers/bus/fsl-mc/dprc-driver.c | 41 drivers/bus/fsl-mc/fsl-mc-msi.c | 6 +- 2 files changed, 42 insertions(+), 5 deletions(-) diff --git a/drivers/bus/fsl-mc/dprc-driver.c b/drivers/bus/fsl-mc/dprc-driver.c index 52c7e15143d6

[PATCH 04/10] irqchip/irq-gic-v3-its-fsl-mc-msi: Remove domain init order dependencies

-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c | 47 ++--- 1 file changed, 29 insertions(+), 18 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c b/drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c index 606efa64adff..0e9b31f13618 100644

[PATCH 09/10] irqchip/gic-v3-its: Initialize its nodes later

-off-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its.c | 3 ++- drivers/irqchip/irq-gic-v3.c | 4 include/linux/irqchip/arm-gic-v3.h | 1 - 3 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index

[PATCH 04/10] irqchip/irq-gic-v3-its-fsl-mc-msi: Remove domain init order dependencies

-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c | 47 ++--- 1 file changed, 29 insertions(+), 18 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c b/drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c index 606efa64adff..0e9b31f13618 100644

[PATCH 09/10] irqchip/gic-v3-its: Initialize its nodes later

-off-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its.c | 3 ++- drivers/irqchip/irq-gic-v3.c | 4 include/linux/irqchip/arm-gic-v3.h | 1 - 3 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index

[PATCH 00/10] irqdomain, gic-v3-its: Implement late irq domain initialization

and #10 change initcall levels for various drivers. Patches have been tested with Cavium ThunderX and ThunderX2. I have an implementation of CMA ITS table allocation on top of this series available, I will send out patches for this in a couple of days. Robert Richter (10): irqdomain: Add

[PATCH 02/10] irqchip/gic-v3-its-platform-msi: Remove domain init order dependencies

-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its-platform-msi.c | 54 +-- 1 file changed, 42 insertions(+), 12 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its-platform-msi.c b/drivers/irqchip/irq-gic-v3-its-platform-msi.c index 7b8e87b493fe..1f2849bc58c4

[PATCH 01/10] irqdomain: Add interface to request an irq domain

and the request removed from the list. With a late_initcall all requests from the list should already have been handled, otherwise all remaining requests are removed with an error reported. Signed-off-by: Robert Richter --- include/linux/irqdomain.h | 15 + kernel/irq/irqdomain.c| 158

[PATCH 03/10] irqchip/irq-gic-v3-its-pci-msi: Remove domain init order dependencies

-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its-pci-msi.c | 66 ++-- 1 file changed, 38 insertions(+), 28 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its-pci-msi.c b/drivers/irqchip/irq-gic-v3-its-pci-msi.c index 8d6d009d1d58..7d7366d55d34 100644

[PATCH 00/10] irqdomain, gic-v3-its: Implement late irq domain initialization

and #10 change initcall levels for various drivers. Patches have been tested with Cavium ThunderX and ThunderX2. I have an implementation of CMA ITS table allocation on top of this series available, I will send out patches for this in a couple of days. Robert Richter (10): irqdomain: Add

[PATCH 02/10] irqchip/gic-v3-its-platform-msi: Remove domain init order dependencies

-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its-platform-msi.c | 54 +-- 1 file changed, 42 insertions(+), 12 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its-platform-msi.c b/drivers/irqchip/irq-gic-v3-its-platform-msi.c index 7b8e87b493fe..1f2849bc58c4

[PATCH 01/10] irqdomain: Add interface to request an irq domain

and the request removed from the list. With a late_initcall all requests from the list should already have been handled, otherwise all remaining requests are removed with an error reported. Signed-off-by: Robert Richter --- include/linux/irqdomain.h | 15 + kernel/irq/irqdomain.c| 158

[PATCH 03/10] irqchip/irq-gic-v3-its-pci-msi: Remove domain init order dependencies

-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its-pci-msi.c | 66 ++-- 1 file changed, 38 insertions(+), 28 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its-pci-msi.c b/drivers/irqchip/irq-gic-v3-its-pci-msi.c index 8d6d009d1d58..7d7366d55d34 100644

Re: [PATCH v3 0/7] Remove errors building drivers/DRIVERNAME

On 27.09.18 23:08:09, Leonardo Brás wrote: > This Patchset changes some driver's Makefile to allow them building > using the command 'make drivers/DRIVERNAME', if compatible. > > The changed drivers would return error if the above command was run > on them, after an x86 allyesconfig. I don't see

Re: [PATCH v3 0/7] Remove errors building drivers/DRIVERNAME

On 27.09.18 23:08:09, Leonardo Brás wrote: > This Patchset changes some driver's Makefile to allow them building > using the command 'make drivers/DRIVERNAME', if compatible. > > The changed drivers would return error if the above command was run > on them, after an x86 allyesconfig. I don't see

Re: [PATCH RESEND 3/6] arm64: add sysfs vulnerability show for spectre v1

On 18.09.18 18:15:51, Will Deacon wrote: > On Tue, Sep 18, 2018 at 11:52:27AM +0200, Robert Richter wrote: > > On 18.09.18 09:38:05, Will Deacon wrote: > > > On Mon, Sep 17, 2018 at 07:22:07PM +0200, Robert Richter wrote: > > > > On 27.08.18 16:33:07, Mian Yousaf Kauk

Re: [PATCH RESEND 3/6] arm64: add sysfs vulnerability show for spectre v1

On 18.09.18 18:15:51, Will Deacon wrote: > On Tue, Sep 18, 2018 at 11:52:27AM +0200, Robert Richter wrote: > > On 18.09.18 09:38:05, Will Deacon wrote: > > > On Mon, Sep 17, 2018 at 07:22:07PM +0200, Robert Richter wrote: > > > > On 27.08.18 16:33:07, Mian Yousaf Kauk

Re: [PATCH RESEND 3/6] arm64: add sysfs vulnerability show for spectre v1

On 18.09.18 09:38:05, Will Deacon wrote: > On Mon, Sep 17, 2018 at 07:22:07PM +0200, Robert Richter wrote: > > On 27.08.18 16:33:07, Mian Yousaf Kaukab wrote: > > > Hard-coded since patches are merged and there are no configuration > > > options. > > > > C

Re: [PATCH RESEND 3/6] arm64: add sysfs vulnerability show for spectre v1

On 18.09.18 09:38:05, Will Deacon wrote: > On Mon, Sep 17, 2018 at 07:22:07PM +0200, Robert Richter wrote: > > On 27.08.18 16:33:07, Mian Yousaf Kaukab wrote: > > > Hard-coded since patches are merged and there are no configuration > > > options. > > > > C

Re: [PATCH RESEND 3/6] arm64: add sysfs vulnerability show for spectre v1

On 27.08.18 16:33:07, Mian Yousaf Kaukab wrote: > Hard-coded since patches are merged and there are no configuration > options. Could you add a list of upstream patches to the description that are required to solve this? This would be a strict definition for the mitigation being enabled and makes

Re: [PATCH RESEND 3/6] arm64: add sysfs vulnerability show for spectre v1

On 27.08.18 16:33:07, Mian Yousaf Kaukab wrote: > Hard-coded since patches are merged and there are no configuration > options. Could you add a list of upstream patches to the description that are required to solve this? This would be a strict definition for the mitigation being enabled and makes

Re: [RFC PATCH] MIPS: Oprofile: Drop support

On 04.05.18 12:03:12, Matt Redfearn wrote: > >As said, oprofile version 0.9.x is still available for cpus that do > >not support perf. What is the breakage? > > The breakage I originally set out to fix was the MT support in perf. >

Re: [RFC PATCH] MIPS: Oprofile: Drop support

On 04.05.18 12:03:12, Matt Redfearn wrote: > >As said, oprofile version 0.9.x is still available for cpus that do > >not support perf. What is the breakage? > > The breakage I originally set out to fix was the MT support in perf. >

Re: [RFC PATCH] MIPS: Oprofile: Drop support

On 04.05.18 10:54:32, Matt Redfearn wrote: > perf is available for MIPS and supports many more CPU types than oprofile. > oprofile userspace seemingly has been broken since 1.0.0 - removing oprofile > support from the MIPS kernel would not break it more thatn it already is, What do you mean with

Re: [RFC PATCH] MIPS: Oprofile: Drop support

On 04.05.18 10:54:32, Matt Redfearn wrote: > perf is available for MIPS and supports many more CPU types than oprofile. > oprofile userspace seemingly has been broken since 1.0.0 - removing oprofile > support from the MIPS kernel would not break it more thatn it already is, What do you mean with

Re: [RFC PATCH] MIPS: Oprofile: Drop support

On 24.04.18 14:15:58, Matt Redfearn wrote: > On 24/04/18 14:05, James Hogan wrote: > >On Tue, Apr 24, 2018 at 01:55:54PM +0100, Matt Redfearn wrote: > >>Since it appears that MIPS oprofile support is currently broken, core > >>oprofile is not getting many updates and not as many architectures >

Re: [RFC PATCH] MIPS: Oprofile: Drop support

On 24.04.18 14:15:58, Matt Redfearn wrote: > On 24/04/18 14:05, James Hogan wrote: > >On Tue, Apr 24, 2018 at 01:55:54PM +0100, Matt Redfearn wrote: > >>Since it appears that MIPS oprofile support is currently broken, core > >>oprofile is not getting many updates and not as many architectures >

Re: [PATCH] watchdog: sbsa: use 32-bit read for WCV

oes two 32-bit reads. > > Signed-off-by: Jayachandran C <jn...@caviumnetworks.com> Reviewed-by: Robert Richter <rrich...@cavium.com> I have looked into the non-atomic use of the register access and it looks sane as the WCV register is only incremented by hardware. There is no concurrent (write) access from the kernel. -Robert

Re: [PATCH] watchdog: sbsa: use 32-bit read for WCV

oes two 32-bit reads. > > Signed-off-by: Jayachandran C Reviewed-by: Robert Richter I have looked into the non-atomic use of the register access and it looks sane as the WCV register is only incremented by hardware. There is no concurrent (write) access from the kernel. -Robert

Re: [PATCH v6] PCI: quirks: update Cavium ThunderX ACS quirk implementation

Bjorn, On 27.09.17 11:20:39, Vadim Lomovtsev wrote: > This commit makes Cavium PCI ACS quirk applicable only to Cavium > ThunderX (CN8XXX) family PCIE Root Ports which has limited PCI capabilities > in terms of no ACS support advertisement. However, the RTL internally > implements similar

Re: [PATCH v6] PCI: quirks: update Cavium ThunderX ACS quirk implementation

Bjorn, On 27.09.17 11:20:39, Vadim Lomovtsev wrote: > This commit makes Cavium PCI ACS quirk applicable only to Cavium > ThunderX (CN8XXX) family PCIE Root Ports which has limited PCI capabilities > in terms of no ACS support advertisement. However, the RTL internally > implements similar

Re: [PATCH v7 0/4] Add support for ThunderX2 pmu events using json files

On 12.10.17 16:04:15, Ganapatrao Kulkarni wrote: > tools/perf/arch/arm64/util/Build | 1 + > tools/perf/arch/arm64/util/header.c| 65 > ++ > tools/perf/arch/powerpc/util/header.c | 2 +- > tools/perf/arch/x86/util/header.c

Re: [PATCH v7 0/4] Add support for ThunderX2 pmu events using json files

On 12.10.17 16:04:15, Ganapatrao Kulkarni wrote: > tools/perf/arch/arm64/util/Build | 1 + > tools/perf/arch/arm64/util/header.c| 65 > ++ > tools/perf/arch/powerpc/util/header.c | 2 +- > tools/perf/arch/x86/util/header.c

Re: [PATCH v4 0/3] Workaround for bus/slot reset on Cavium cn8xxx root ports

Bjorn, On 08.09.17 10:10:30, Jan Glauber wrote: > Using vfio-pci on a combination of cn8xxx and some PCI devices results in > a kernel panic. This is triggered by issuing a bus or a slot reset > on the PCI device. > > With this series both checks indicate that the reset is not possible >

Re: [PATCH v4 0/3] Workaround for bus/slot reset on Cavium cn8xxx root ports

Bjorn, On 08.09.17 10:10:30, Jan Glauber wrote: > Using vfio-pci on a combination of cn8xxx and some PCI devices results in > a kernel panic. This is triggered by issuing a bus or a slot reset > on the PCI device. > > With this series both checks indicate that the reset is not possible >

Re: [PATCH v6 4/4] perf vendor events arm64: Add ThunderX2 implementation defined pmu core events

On 11.10.17 13:19:27, Will Deacon wrote: > On Tue, Aug 29, 2017 at 02:47:30PM +0200, Robert Richter wrote: > > Shaokun, > > > > On 29.08.17 17:26:00, Zhangshaokun wrote: > > > On 2017/8/24 20:03, Ganapatrao Kulkarni wrote: > > > > This is not a full eve

Re: [PATCH v6 4/4] perf vendor events arm64: Add ThunderX2 implementation defined pmu core events

On 11.10.17 13:19:27, Will Deacon wrote: > On Tue, Aug 29, 2017 at 02:47:30PM +0200, Robert Richter wrote: > > Shaokun, > > > > On 29.08.17 17:26:00, Zhangshaokun wrote: > > > On 2017/8/24 20:03, Ganapatrao Kulkarni wrote: > > > > This is not a full eve

Re: [PATCH v6 4/4] perf vendor events arm64: Add ThunderX2 implementation defined pmu core events

Shaokun, On 31.08.17 18:29:01, Zhangshaokun wrote: > On 2017/8/29 20:47, Robert Richter wrote: > > On 29.08.17 17:26:00, Zhangshaokun wrote: > >> On 2017/8/24 20:03, Ganapatrao Kulkarni wrote: > >>> This is not a full event list, but a short list of useful

Re: [PATCH v6 4/4] perf vendor events arm64: Add ThunderX2 implementation defined pmu core events

Shaokun, On 31.08.17 18:29:01, Zhangshaokun wrote: > On 2017/8/29 20:47, Robert Richter wrote: > > On 29.08.17 17:26:00, Zhangshaokun wrote: > >> On 2017/8/24 20:03, Ganapatrao Kulkarni wrote: > >>> This is not a full event list, but a short list of useful

Re: [PATCH v6 4/4] perf vendor events arm64: Add ThunderX2 implementation defined pmu core events

Shaokun, On 29.08.17 17:26:00, Zhangshaokun wrote: > On 2017/8/24 20:03, Ganapatrao Kulkarni wrote: > > This is not a full event list, but a short list of useful events. > > > > Signed-off-by: Ganapatrao Kulkarni > > --- > >

Re: [PATCH v6 4/4] perf vendor events arm64: Add ThunderX2 implementation defined pmu core events

Shaokun, On 29.08.17 17:26:00, Zhangshaokun wrote: > On 2017/8/24 20:03, Ganapatrao Kulkarni wrote: > > This is not a full event list, but a short list of useful events. > > > > Signed-off-by: Ganapatrao Kulkarni > > --- > > tools/perf/pmu-events/arch/arm64/mapfile.csv | 15 ++ > >

Re: [PATCH v3 6/8] irqchip/gic-v3-its: Initialize its nodes later

Marc, thanks for your review. On 21.08.17 09:30:24, Marc Zyngier wrote: > +Lorenzo > > On 08/08/17 13:22, Robert Richter wrote: > > Use an initcall to initialize its. This allows us to use the device > > framework during initialization that is up at this point. We use >

Re: [PATCH v3 6/8] irqchip/gic-v3-its: Initialize its nodes later

Marc, thanks for your review. On 21.08.17 09:30:24, Marc Zyngier wrote: > +Lorenzo > > On 08/08/17 13:22, Robert Richter wrote: > > Use an initcall to initialize its. This allows us to use the device > > framework during initialization that is up at this point. We use >

Re: [PATCH v3 0/8] irqchip/gic-v3-its: Implement ITS nodes as kernel devices and use CMA

Marc, On 08.08.17 14:22:50, Robert Richter wrote: > This patch series implements ITS nodes as kernel devices. The > advantage of that is that CMA can be used to allocate large ITS > tables, where standard memory and page allocation fails (above > MAX_ORDER - 1). This approach was sug

Re: [PATCH v3 0/8] irqchip/gic-v3-its: Implement ITS nodes as kernel devices and use CMA

Marc, On 08.08.17 14:22:50, Robert Richter wrote: > This patch series implements ITS nodes as kernel devices. The > advantage of that is that CMA can be used to allocate large ITS > tables, where standard memory and page allocation fails (above > MAX_ORDER - 1). This approach was sug

Re: [PATCH v4] acpi/iort: numa: Add numa node mapping for smmuv3 devices

On 15.08.17 16:05:49, Lorenzo Pieralisi wrote: > On Tue, Aug 15, 2017 at 05:02:13PM +0200, Robert Richter wrote: > > Lorenzo, Will, > > > > On 25.07.17 10:32:37, Ganapatrao Kulkarni wrote: > > > ARM IORT specification(rev. C) has added provision to define proximi

Re: [PATCH v4] acpi/iort: numa: Add numa node mapping for smmuv3 devices

On 15.08.17 16:05:49, Lorenzo Pieralisi wrote: > On Tue, Aug 15, 2017 at 05:02:13PM +0200, Robert Richter wrote: > > Lorenzo, Will, > > > > On 25.07.17 10:32:37, Ganapatrao Kulkarni wrote: > > > ARM IORT specification(rev. C) has added provision to define proximi

Re: [PATCH v4] acpi/iort: numa: Add numa node mapping for smmuv3 devices

Lorenzo, Will, On 25.07.17 10:32:37, Ganapatrao Kulkarni wrote: > ARM IORT specification(rev. C) has added provision to define proximity > domain in SMMUv3 IORT table. Adding required code to parse Proximity > domain and set numa_node of smmv3 platform devices. > > Add code to parse proximity

Re: [PATCH v4] acpi/iort: numa: Add numa node mapping for smmuv3 devices

Lorenzo, Will, On 25.07.17 10:32:37, Ganapatrao Kulkarni wrote: > ARM IORT specification(rev. C) has added provision to define proximity > domain in SMMUv3 IORT table. Adding required code to parse Proximity > domain and set numa_node of smmv3 platform devices. > > Add code to parse proximity

[PATCH v3 1/8] irqchip/gic-v3-its: Initialize its nodes in probe order

ATM the last discovered node is initialized first. Though this order should work too, change the initialization of nodes to probe order as one would expect it. Signed-off-by: Robert Richter <rrich...@cavium.com> --- drivers/irqchip/irq-gic-v3-its.c | 2 +- 1 file changed, 1 insertion

[PATCH v3 1/8] irqchip/gic-v3-its: Initialize its nodes in probe order

ATM the last discovered node is initialized first. Though this order should work too, change the initialization of nodes to probe order as one would expect it. Signed-off-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH v3 2/8] irqchip/gic-v3-its: Initialize MSIs with subsys_initcalls

This allows us to use kernel core functionality (e.g. cma) for ITS initialization. MSIs must be up before the device_initcalls (pci and platform device probe) and after arch_initcalls (dma init), so subsys_initcall is fine. Signed-off-by: Robert Richter <rrich...@cavium.com> --- drivers/i

[PATCH v3 2/8] irqchip/gic-v3-its: Initialize MSIs with subsys_initcalls

This allows us to use kernel core functionality (e.g. cma) for ITS initialization. MSIs must be up before the device_initcalls (pci and platform device probe) and after arch_initcalls (dma init), so subsys_initcall is fine. Signed-off-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its-pci

[PATCH v3 6/8] irqchip/gic-v3-its: Initialize its nodes later

-off-by: Robert Richter <rrich...@cavium.com> --- drivers/irqchip/irq-gic-v3-its.c | 3 ++- drivers/irqchip/irq-gic-v3.c | 5 - include/linux/irqchip/arm-gic-v3.h | 1 - 3 files changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqch

[PATCH v3 6/8] irqchip/gic-v3-its: Initialize its nodes later

-off-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its.c | 3 ++- drivers/irqchip/irq-gic-v3.c | 5 - include/linux/irqchip/arm-gic-v3.h | 1 - 3 files changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index

[PATCH v3 5/8] irqchip/gic-v3-its: Prevent its init ordering dependencies

Right now its_init() must be called before pci and platform init. Remove ordering dependencies to allow all initialization functions being called with the same initcall type. Signed-off-by: Robert Richter <rrich...@cavium.com> --- drivers/irqchip/irq-gic-v3-its-pci-msi.c | 4 +++- d

[PATCH v3 5/8] irqchip/gic-v3-its: Prevent its init ordering dependencies

Right now its_init() must be called before pci and platform init. Remove ordering dependencies to allow all initialization functions being called with the same initcall type. Signed-off-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its-pci-msi.c | 4 +++- drivers/irqchip/irq-gic-v3-its

[PATCH v3 7/8] irqchip/gic-v3-its: Handle its nodes as kernel devices

Manage its nodes as kernel devices. We can then use the kernel's device resource management for memory allocation. Freeing memory becomes much easier now. This also allows us to use CMA for the allocation of large its tables. Signed-off-by: Robert Richter <rrich...@cavium.com> --- d

[PATCH v3 7/8] irqchip/gic-v3-its: Handle its nodes as kernel devices

Manage its nodes as kernel devices. We can then use the kernel's device resource management for memory allocation. Freeing memory becomes much easier now. This also allows us to use CMA for the allocation of large its tables. Signed-off-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its.c

[PATCH v3 0/8] irqchip/gic-v3-its: Implement ITS nodes as kernel devices and use CMA

: * rebased onto v4.11-rc1, * fixed syntax error in its_init() function (split probing patch), * added comment in its_create_device(), * fixed GITS_BASER_PAGE_SIZE_MASK usage in its_setup_baser() Robert Richter (8): irqchip/gic-v3-its: Initialize its nodes in probe order irqchip/gic-v3-its

[PATCH v3 0/8] irqchip/gic-v3-its: Implement ITS nodes as kernel devices and use CMA

: * rebased onto v4.11-rc1, * fixed syntax error in its_init() function (split probing patch), * added comment in its_create_device(), * fixed GITS_BASER_PAGE_SIZE_MASK usage in its_setup_baser() Robert Richter (8): irqchip/gic-v3-its: Initialize its nodes in probe order irqchip/gic-v3-its

[PATCH v3 8/8] irqchip, gicv3-its, cma: Use CMA for allocation of large device tables

-by: Robert Richter <rrich...@cavium.com> --- drivers/irqchip/irq-gic-v3-its.c | 74 1 file changed, 45 insertions(+), 29 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index b7d853dd6b75..8da9b423f9e1

[PATCH v3 8/8] irqchip, gicv3-its, cma: Use CMA for allocation of large device tables

-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its.c | 74 1 file changed, 45 insertions(+), 29 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index b7d853dd6b75..8da9b423f9e1 100644 --- a/drivers/irqchip/irq

[PATCH v3 3/8] irqchip/gic-v3-its: Split probing from its node initialization

To initialize the its nodes at a later point during boot, we need to split probing from initialization. Collect all information required for initialization in struct its_node. We can then use the its node list for initialization. Signed-off-by: Robert Richter <rrich...@cavium.com> --- d

[PATCH v3 3/8] irqchip/gic-v3-its: Split probing from its node initialization

To initialize the its nodes at a later point during boot, we need to split probing from initialization. Collect all information required for initialization in struct its_node. We can then use the its node list for initialization. Signed-off-by: Robert Richter --- drivers/irqchip/irq-gic-v3

[PATCH v3 4/8] irqchip/gic-v3-its: Decouple its initialization from gic

This patch separates its initialization from the gic. Probing and initialization of its nodes is separate now. There is an own cpu notifier for its now. Signed-off-by: Robert Richter <rrich...@cavium.com> --- drivers/irqchip/irq-gic-v3-its.c | 61 +++--- d

[PATCH v3 4/8] irqchip/gic-v3-its: Decouple its initialization from gic

This patch separates its initialization from the gic. Probing and initialization of its nodes is separate now. There is an own cpu notifier for its now. Signed-off-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its.c | 61 +++--- drivers/irqchip/irq-gic-v3.c

[PATCH] MAINTAINERS: Update Cavium ThunderX2 entry

On 08.08.17 01:07:04, Jayachandran C wrote: > Add Robert Richter as the primary maintainer for this platform. > > Signed-off-by: Jayachandran C <jn...@caviumnetworks.com> > --- > MAINTAINERS | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/MAINTAINERS

[PATCH] MAINTAINERS: Update Cavium ThunderX2 entry

On 08.08.17 01:07:04, Jayachandran C wrote: > Add Robert Richter as the primary maintainer for this platform. > > Signed-off-by: Jayachandran C > --- > MAINTAINERS | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > in

Re: [PATCHv2 1/2] arm64:vdso: Rewrite gettimeofday into C.

Will, On 31.05.17 13:44:30, Will Deacon wrote: > Thanks for posting this, but please try to cc the maintainers in future -- I > almost missed it! > > On Tue, May 30, 2017 at 05:34:19PM -0700, Andrew Pinski wrote: > > This allows the compiler to optimize the divide by 1000. > > And remove the

Re: [PATCHv2 1/2] arm64:vdso: Rewrite gettimeofday into C.

Will, On 31.05.17 13:44:30, Will Deacon wrote: > Thanks for posting this, but please try to cc the maintainers in future -- I > almost missed it! > > On Tue, May 30, 2017 at 05:34:19PM -0700, Andrew Pinski wrote: > > This allows the compiler to optimize the divide by 1000. > > And remove the

Re: [PATCH] irqchip/gic-v3-its: Remove ACPICA version check for ACPI NUMA

Marc, I think this can go in as fix for 4.13. Please review. Thanks, -Robert On 12.07.17 15:25:09, Robert Richter wrote: > The version check was added due to dependency to > > a618c7f89a02 ACPICA: Add support for new SRAT subtable > > Now, that this code is in the kernel, r

Re: [PATCH] irqchip/gic-v3-its: Remove ACPICA version check for ACPI NUMA

Marc, I think this can go in as fix for 4.13. Please review. Thanks, -Robert On 12.07.17 15:25:09, Robert Richter wrote: > The version check was added due to dependency to > > a618c7f89a02 ACPICA: Add support for new SRAT subtable > > Now, that this code is in the kernel, r

Re: [PATCH v4] acpi/iort: numa: Add numa node mapping for smmuv3 devices

On 25.07.17 10:32:37, Ganapatrao Kulkarni wrote: > ARM IORT specification(rev. C) has added provision to define proximity > domain in SMMUv3 IORT table. Adding required code to parse Proximity > domain and set numa_node of smmv3 platform devices. > > Add code to parse proximity domain in SMMUv3

Re: [PATCH v4] acpi/iort: numa: Add numa node mapping for smmuv3 devices

On 25.07.17 10:32:37, Ganapatrao Kulkarni wrote: > ARM IORT specification(rev. C) has added provision to define proximity > domain in SMMUv3 IORT table. Adding required code to parse Proximity > domain and set numa_node of smmv3 platform devices. > > Add code to parse proximity domain in SMMUv3

Re: [PATCH v2] irqchip: gicv3-its: Use NUMA aware memory allocation for ITS tables

On 10.07.17 10:53:45, Shanker Donthineni wrote: > The NUMA node information is visible to ITS driver but not being used > other than handling hardware errata. ITS/GICR hardware accesses to the > local NUMA node is usually quicker than the remote NUMA node. How slow > the remote NUMA accesses are

Re: [PATCH v2] irqchip: gicv3-its: Use NUMA aware memory allocation for ITS tables

On 10.07.17 10:53:45, Shanker Donthineni wrote: > The NUMA node information is visible to ITS driver but not being used > other than handling hardware errata. ITS/GICR hardware accesses to the > local NUMA node is usually quicker than the remote NUMA node. How slow > the remote NUMA accesses are

Re: [PATCH] irqchip: gicv3-its: Use NUMA aware memory allocation for ITS tables

On 11.07.17 08:48:56, Jayachandran C wrote: > On Mon, Jul 10, 2017 at 04:15:28PM +0100, Marc Zyngier wrote: > > On 10/07/17 15:57, Shanker Donthineni wrote: > > > I believe ITS driver should provide NUMA aware allocations just like x86 > > > Linux drivers. How much > > > performance improvement

Re: [PATCH] irqchip: gicv3-its: Use NUMA aware memory allocation for ITS tables

On 11.07.17 08:48:56, Jayachandran C wrote: > On Mon, Jul 10, 2017 at 04:15:28PM +0100, Marc Zyngier wrote: > > On 10/07/17 15:57, Shanker Donthineni wrote: > > > I believe ITS driver should provide NUMA aware allocations just like x86 > > > Linux drivers. How much > > > performance improvement

[PATCH] irqchip/gic-v3-its: Remove ACPICA version check for ACPI NUMA

The version check was added due to dependency to a618c7f89a02 ACPICA: Add support for new SRAT subtable Now, that this code is in the kernel, remove the check. This is esp. useful to enable backports. Signed-off-by: Robert Richter <rrich...@cavium.com> --- drivers/irqchip/irq-gic-v3-its

[PATCH] irqchip/gic-v3-its: Remove ACPICA version check for ACPI NUMA

The version check was added due to dependency to a618c7f89a02 ACPICA: Add support for new SRAT subtable Now, that this code is in the kernel, remove the check. This is esp. useful to enable backports. Signed-off-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its.c | 2 +- 1 file changed

Re: [PATCH v3 2/2] acpi/iort: numa: Add numa node mapping for smmuv3 devices

On 04.07.17 11:07:59, Lorenzo Pieralisi wrote: > On Wed, Jun 28, 2017 at 07:47:50PM +0200, Robert Richter wrote: > > On 15.06.17 14:46:03, Lorenzo Pieralisi wrote: > > > On Thu, Jun 08, 2017 at 10:14:19AM +0530, Ganapatrao Kulkarni wrote: > > > > Add code to parse p

Re: [PATCH v3 2/2] acpi/iort: numa: Add numa node mapping for smmuv3 devices

On 04.07.17 11:07:59, Lorenzo Pieralisi wrote: > On Wed, Jun 28, 2017 at 07:47:50PM +0200, Robert Richter wrote: > > On 15.06.17 14:46:03, Lorenzo Pieralisi wrote: > > > On Thu, Jun 08, 2017 at 10:14:19AM +0530, Ganapatrao Kulkarni wrote: > > > > Add code to parse p

Re: [PATCH V17 01/11] acpi: apei: read ack upon ghes record consumption

Tyler, On 19.05.17 14:32:03, Tyler Baicar wrote: > A RAS (Reliability, Availability, Serviceability) controller > may be a separate processor running in parallel with OS > execution, and may generate error records for consumption by > the OS. If the RAS controller produces multiple error records,

<    1   2   3   4   5   6   7   8   9   10   >