On Mon, Jun 08, 2020 at 04:42:54PM +0300, Andy Shevchenko wrote:
> Some devices would need to have a hierarchy of properties and
> child nodes passed to the child or children of MFD. For such case
> we may utilize software nodes, which is superior on device properties.
>
> Add support of software
On Tue, Jun 16, 2020 at 10:02:42PM +0530, Vinod Koul wrote:
> Hi Serge,
>
> On 02-06-20, 12:27, Serge Semin wrote:
> > Vinod, Viresh
> >
> > Andy's finished his review. So all the patches of the series (except one
> > rather
> > decorative, which we have
, Serge Semin wrote:
> On Tue, Jun 02, 2020 at 11:12:31AM +0100, Marc Zyngier wrote:
> > On 2020-06-02 11:09, Serge Semin wrote:
> > > Add Thomas and myself as maintainers of the MIPS CPU and GIC IRQchip,
> > > MIPS
> > > GIC timer and MIPS CPS CPUidle drivers.
>
On Tue, Jun 02, 2020 at 01:10:30PM +0100, Colin King wrote:
> From: Colin Ian King
>
> There is a spelling mistake in a pr_err error message. Fix it.
Thanks!
Reviewed-by: Serge Semin
>
> Signed-off-by: Colin Ian King
> ---
> drivers/clk/baikal-t1/clk-ccu-div.c | 2 +-
and Volt-to-N polynomials with __maybe_unused attribute.
Note gcc with W=1 doesn't notice the problem.
Fixes: 87976ce2825d ("hwmon: Add Baikal-T1 PVT sensor driver")
Reported-by: kbuild test robot
Signed-off-by: Serge Semin
Cc: Maxim Kaurkin
Cc: Alexey Malahov
---
Link:
https://lore.
On Tue, Jun 02, 2020 at 11:12:31AM +0100, Marc Zyngier wrote:
> On 2020-06-02 11:09, Serge Semin wrote:
> > Add Thomas and myself as maintainers of the MIPS CPU and GIC IRQchip,
> > MIPS
> > GIC timer and MIPS CPS CPUidle drivers.
> >
>
On Tue, Jun 02, 2020 at 10:18:28AM +0200, Lars Povlsen wrote:
>
> Serge Semin writes:
>
> > Hello Lars,
> >
> > On Wed, May 13, 2020 at 04:00:21PM +0200, Lars Povlsen wrote:
> >> This is an add-on series to the main SoC Sparx5 series
> >> (
On Tue, Jun 02, 2020 at 07:07:46AM -0700, Guenter Roeck wrote:
> On Tue, Jun 02, 2020 at 12:12:19PM +0300, Serge Semin wrote:
> > Clang-based kernel building with W=1 warns that some static const
> > variables are unused:
> >
> > drivers/hwmon/bt1-pvt.c:67:3
anks.
Reviewed-by: Serge Semin
>
> Addresses-Coverity: ("Unused value")
> Signed-off-by: Colin Ian King
> ---
> drivers/clk/baikal-t1/ccu-div.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/baikal-t1/ccu-div.c b/dri
On Wed, May 13, 2020 at 04:00:28PM +0200, Lars Povlsen wrote:
> This adds support for the Sparx5 SoC in the spi-dw-mchp SPI controller.
>
> Reviewed-by: Alexandre Belloni
> Signed-off-by: Lars Povlsen
> ---
> drivers/spi/spi-dw-mchp.c | 211 ++
> 1 file
On Wed, May 13, 2020 at 04:00:27PM +0200, Lars Povlsen wrote:
> This add DT bindings for the Sparx5 SPI driver.
This whole file can be easily merged in to the generic DW APB SSI DT
binding file. Just use "if: properties: compatible: const: ..." construction
to distinguish ocelot, jaguar, sparx5
On Tue, May 19, 2020 at 02:05:19PM +0200, Lars Povlsen wrote:
> On 13/05/20 16:18, Mark Brown wrote:
> > Date: Wed, 13 May 2020 16:18:11 +0100
> > From: Mark Brown
> > To: Lars Povlsen
> > Cc: SoC Team , Microchip Linux Driver Support
> > , linux-...@vger.kernel.org,
> >
On Wed, May 13, 2020 at 04:00:25PM +0200, Lars Povlsen wrote:
> This add DT bindings for the Microsemi/Microchip SPI controller used
> in various SoC's. It describes the "mscc,ocelot-spi" and
> "mscc,jaguar2-spi" bindings.
As I see it, there is no need in this patch at all. Current DT binding
On Wed, May 13, 2020 at 04:00:23PM +0200, Lars Povlsen wrote:
> This add support for the RX_SAMPLE_DLY register. If enabled in the
> Designware IP, it allows tuning of the rx data signal by means of an
> internal rx sample fifo.
>
> The register is located at offset 0xf0, and if the option is not
On Wed, May 13, 2020 at 04:00:22PM +0200, Lars Povlsen wrote:
> With this change a SPI controller can be added without having a IRQ
> associated, and causing all transfers to be polled. For SPI controllers
> without DMA, this can significantly improve performance by less
> interrupt handling
-sergey.se...@baikalelectronics.ru
Changelog v3:
- Keep F: MAINTAINERS section alphabetically ordered.
- Add Thomas as the co-maintainer of the MIPS CPU and GIC IRQchip, MIPS
GIC timer and MIPS CPS CPUidle drivers.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Paul Burton
Cc: Rob Herring
Cc: Arnd Bergmann
It's a Common Device Memory Map controller embedded into the MIPS IP
cores, which dts node is supposed to have compatible and reg properties.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
---
Changelog prev:
- Lowercase the example hex'es.
---
.../bindings/bus/mti,mips-cdmm.yaml
C also includes a free-running global timer, per-CPU count/compare
timers, and a watchdog. Since currently the GIC Timer is only supported the
DT schema expects an IRQ and clock-phandler charged timer sub-node with
"mti,mips-gic-timer" compatible string.
Signed-off-by: Serge Semin
Review
It's a Cluster Power Controller embedded into the MIPS IP cores.
Currently the corresponding dts node is supposed to have compatible
and reg properties.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
---
Changelog prev:
- Reword the changelog summary - use shorter version.
- Lowercase
Add Thomas and myself as maintainers of the MIPS CPU and GIC IRQchip, MIPS
GIC timer and MIPS CPS CPUidle drivers.
Signed-off-by: Serge Semin
---
Changelog v3:
- Keep the files list alphabetically ordered.
- Add Thomas as the co-maintainer of the designated drivers.
---
MAINTAINERS | 11
CDMM may be available not only on MIPS R2 architectures, but also on
newer MIPS R5 chips. For instance our P5600 chip has one. Let's mark
the CDMM bus being supported for that MIPS arch too.
Signed-off-by: Serge Semin
Reviewed-by: Thomas Bogendoerfer
---
drivers/bus/Kconfig | 2 +-
1 file
platforms by default.
Signed-off-by: Serge Semin
---
Changelog prev:
- Use alphabetical order for the include pre-processor operator.
---
drivers/bus/mips_cdmm.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/bus/mips_cdmm.c b/drivers/bus/mips_cdmm.c
index
Hello Joe
On Mon, Jun 01, 2020 at 11:22:58AM -0700, Joe Perches wrote:
> On Mon, 2020-06-01 at 19:04 +0300, Andy Shevchenko wrote:
> > On Mon, Jun 1, 2020 at 6:52 PM Serge Semin
> > wrote:
> > > On Mon, Jun 01, 2020 at 06:30:22PM +0300, Andy Shevchenko wrote:
> > &
the noLLP-problem fix for the Dw APB SSI
in 5.8.
-Sergey
On Fri, May 29, 2020 at 05:40:43PM +0300, Serge Semin wrote:
> Baikal-T1 SoC has an DW DMAC on-board to provide a Mem-to-Mem, low-speed
> peripherals Dev-to-Mem and Mem-to-Dev functionality. Mostly it's compatible
> with currently im
and Volt-to-N polynomials only if the PVT alarms are
switched on at compile-time.
Note gcc with W=1 doesn't notice the problem.
Fixes: 87976ce2825d ("hwmon: Add Baikal-T1 PVT sensor driver")
Reported-by: kbuild test robot
Signed-off-by: Serge Semin
Cc: Maxim Kaurkin
Cc: Alex
On Tue, Jun 02, 2020 at 10:18:28AM +0200, Lars Povlsen wrote:
>
> Serge Semin writes:
>
> > Hello Lars,
> >
> > On Wed, May 13, 2020 at 04:00:21PM +0200, Lars Povlsen wrote:
> >> This is an add-on series to the main SoC Sparx5 series
> >> (
On Thu, May 28, 2020 at 06:26:50PM +0930, Joel Stanley wrote:
> The i2c bindings in the kernel tree describe support for 10 bit
> addressing, which must be indicated with the I2C_TEN_BIT_ADDRESS flag.
> When this is set the address can be up to 10 bits. When it is not set
> the address is a
On Mon, Jun 01, 2020 at 06:56:46PM +0200, Thomas Bogendoerfer wrote:
> On Mon, Jun 01, 2020 at 06:24:49PM +0300, Serge Semin wrote:
> > Hello Marc,
> >
> > On Mon, Jun 01, 2020 at 01:31:27PM +0100, Marc Zyngier wrote:
> > > On 2020-
On Mon, Jun 01, 2020 at 06:30:22PM +0300, Andy Shevchenko wrote:
> On Mon, Jun 1, 2020 at 6:19 PM Serge Semin
> wrote:
> > On Mon, Jun 01, 2020 at 04:56:21PM +0300, Andy Shevchenko wrote:
> > > On Mon, Jun 1, 2020 at 3:26 PM Serge Semin
> > > wrote:
> > &g
Hello Marc,
On Mon, Jun 01, 2020 at 01:31:27PM +0100, Marc Zyngier wrote:
> On 2020-06-01 13:21, Serge Semin wrote:
>
> [...]
>
> > Since Paul isn't looking after the MIPS arch code anymore, Ralf hasn't
> > been seen maintaining MIPS for a long time, Thomas is only resp
On Mon, Jun 01, 2020 at 04:56:21PM +0300, Andy Shevchenko wrote:
> On Mon, Jun 1, 2020 at 3:26 PM Serge Semin
> wrote:
> >
> > Add myself as a maintainer of MIPS CPU and GIC IRQchip, MIPS GIC timer
> > and MIPS CPS CPUidle drivers.
> ...
> > +MIPS CORE DRIVER
The following commit has been merged into the timers/core branch of tip:
Commit-ID: e69bc8999662a3fa6d856820dd09717afff1cbb0
Gitweb:
https://git.kernel.org/tip/e69bc8999662a3fa6d856820dd09717afff1cbb0
Author:Serge Semin
AuthorDate:Thu, 21 May 2020 23:48:11 +03:00
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 7d7de1a65349811b24971c5e8e040e6aac192dd4
Gitweb:
https://git.kernel.org/tip/7d7de1a65349811b24971c5e8e040e6aac192dd4
Author:Serge Semin
AuthorDate:Thu, 21 May 2020 23:48:17 +03:00
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 65e0f876405ef4f0ff25eb1c5ff3e9b536d68805
Gitweb:
https://git.kernel.org/tip/65e0f876405ef4f0ff25eb1c5ff3e9b536d68805
Author:Serge Semin
AuthorDate:Thu, 21 May 2020 23:48:14 +03:00
The following commit has been merged into the timers/core branch of tip:
Commit-ID: cee43dbf2ee3f430434e2b66994eff8a1aeda889
Gitweb:
https://git.kernel.org/tip/cee43dbf2ee3f430434e2b66994eff8a1aeda889
Author:Serge Semin
AuthorDate:Thu, 21 May 2020 23:48:13 +03:00
The following commit has been merged into the timers/core branch of tip:
Commit-ID: b33aaf5cd68d0fa0f0d6aa15831a1e82e2ef98e1
Gitweb:
https://git.kernel.org/tip/b33aaf5cd68d0fa0f0d6aa15831a1e82e2ef98e1
Author:Serge Semin
AuthorDate:Thu, 21 May 2020 23:48:10 +03:00
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 6d2e16a3181bafb77b535095c39ad1c8b9558c8c
Gitweb:
https://git.kernel.org/tip/6d2e16a3181bafb77b535095c39ad1c8b9558c8c
Author:Serge Semin
AuthorDate:Thu, 21 May 2020 23:48:15 +03:00
CDMM may be available not only on MIPS R2 architectures, but also on
newer MIPS R5 chips. For instance our P5600 chip has one. Let's mark
the CDMM bus being supported for that MIPS arch too.
Signed-off-by: Serge Semin
Reviewed-by: Thomas Bogendoerfer
---
drivers/bus/Kconfig | 2 +-
1 file
i,mips-cpc to DT schema.
- Use a shorter summary describing the bindings modification patches.
- Rearrange the SoBs with adding Alexey' co-development tag.
- Lowercase the hex numbers in the dt-bindings.
Changelog v2:
- Resend.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Paul Burton
Cc: R
It's a Cluster Power Controller embedded into the MIPS IP cores.
Currently the corresponding dts node is supposed to have compatible
and reg properties.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
---
Changelog prev:
- Reword the changelog summary - use shorter version.
- Lowercase
platforms by default.
Signed-off-by: Serge Semin
---
Changelog prev:
- Use alphabetical order for the include pre-processor operator.
---
drivers/bus/mips_cdmm.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/bus/mips_cdmm.c b/drivers/bus/mips_cdmm.c
index
Add myself as a maintainer of MIPS CPU and GIC IRQchip, MIPS GIC timer
and MIPS CPS CPUidle drivers.
Signed-off-by: Serge Semin
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2926327e4976..f21e51c4a0d5 100644
--- a/MAINTAINERS
C also includes a free-running global timer, per-CPU count/compare
timers, and a watchdog. Since currently the GIC Timer is only supported the
DT schema expects an IRQ and clock-phandler charged timer sub-node with
"mti,mips-gic-timer" compatible string.
Signed-off-by: Serge Semin
Review
It's a Common Device Memory Map controller embedded into the MIPS IP
cores, which dts node is supposed to have compatible and reg properties.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
---
Changelog prev:
- Lowercase the example hex'es.
---
.../bindings/bus/mti,mips-cdmm.yaml
On Sat, May 30, 2020 at 11:31:52AM +0200, Wolfram Sang wrote:
>
> > + addr = reg & 0x3FFFU;
> > + snprintf(unit_addr, sizeof(unit_addr), "%x", addr);
>
> Hmm, this hardcoded value will not work if we ever need to add another
> bit. I hope this will never happen, though.
>
> > +
On Sat, May 30, 2020 at 11:05:54PM +0200, Wolfram Sang wrote:
> On Sat, May 30, 2020 at 01:09:30PM +0200, Wolfram Sang wrote:
> > On Thu, May 28, 2020 at 12:33:18PM +0300, Serge Semin wrote:
> > > Seeing the DW I2C driver is using flags-based accessors with two
> > > c
Hello Wolfram
On Sat, May 30, 2020 at 11:39:42AM +0200, Wolfram Sang wrote:
>
> Just double checking:
>
> > Signed-off-by: Serge Semin
> > Reviewed-by: Rob Herring
>
> Rob, what about this checkpatch warning?
>
> WARNING: DT binding documents should be l
rt the new timeouts data
structure.
Signed-off-by: Serge Semin
Reviewed-by: Guenter Roeck
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
Changelog v2:
- Rearrange SoBs.
- Add "ms" suffix to t
happens, the IRQ lane will be left pending until
it's cleared by the timer restart.
Signed-off-by: Serge Semin
Reviewed-by: Guenter Roeck
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
Changelog v2
references clock source, optional reset line and
pre-timeout interrupt.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
Reviewed-by: Guenter Roeck
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: linux-m...@vger.kernel.org
---
Changelog v2:
- Rearrange SoBs.
- Discard
4402-1-sergey.se...@baikalelectronics.ru
Changelog v4:
- Add Guenter's Reviewed-by tags.
- IRQ > 0 is only valid in Linux so make sure we request IRQ only if valid
number is returned from platform_get_irq_optional().
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Maxim Kaurkin
Cc: Pavel Pa
In case if DW Watchdog IP core is built with WDT_USE_FIX_TOP == false,
a custom timeout periods are used to preset the timer counter. In
this case that periods should be specified in a new "snps,watchdog-tops"
property of the DW watchdog dts node.
Signed-off-by: Serge Semin
Review
For the sake of the easier device-driver debug procedure, we added a
DebugFS file with the controller registers state. It's available only if
kernel is configured with DebugFS support.
Signed-off-by: Serge Semin
Reviewed-by: Guenter Roeck
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd
the optional APB3 bus clock specified along
with the mandatory watchdog timer reference clock.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
Reviewed-by: Guenter Roeck
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: linux-m...@vger.kernel.org
---
Changelog v2:
- It's
ynchronous configuration.
Signed-off-by: Serge Semin
Reviewed-by: Guenter Roeck
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
Changelog v2:
- Rearrange SoBs.
---
drivers/watchdog/dw_
On Fri, May 29, 2020 at 04:02:19PM -0700, Guenter Roeck wrote:
> On Tue, May 26, 2020 at 06:41:22PM +0300, Serge Semin wrote:
> > DW Watchdog can rise an interrupt in case if IRQ request mode is enabled
> > and timer reaches the zero value. In this case the IRQ lane is left
&g
On Fri, May 29, 2020 at 09:45:37PM +0300, Serge Semin wrote:
> On Fri, May 29, 2020 at 09:42:01PM +0300, Andy Shevchenko wrote:
> > On Fri, May 29, 2020 at 09:22:56PM +0300, Serge Semin wrote:
> > > On Fri, May 29, 2020 at 12:13:38PM -0600, Rob Herring wrote:
> > > >
On Fri, May 29, 2020 at 09:42:01PM +0300, Andy Shevchenko wrote:
> On Fri, May 29, 2020 at 09:22:56PM +0300, Serge Semin wrote:
> > On Fri, May 29, 2020 at 12:13:38PM -0600, Rob Herring wrote:
> > > On Wed, May 27, 2020 at 06:33:51PM +0300, Serge Semin wrote:
>
> >
, DMA and slave device
sub-nodes are optional.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
Cc: Georgy Vlasov
Cc: Ramil Zaripov
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Feng Tang
Cc: Andy Shevchenko
Cc: Arnd Bergmann
Cc: linux-m...@vger.kernel.org
---
Changelog v7:
- Rebase
On Fri, May 29, 2020 at 12:13:38PM -0600, Rob Herring wrote:
> On Wed, May 27, 2020 at 06:33:51PM +0300, Serge Semin wrote:
> > Rob,
> > Could you pay attention to this patch? The patchset review procedure is
> > nearly over, while the DT part is only partly reviewed by you
On Fri, May 29, 2020 at 08:43:12PM +0300, Andy Shevchenko wrote:
> On Fri, May 29, 2020 at 08:26:42PM +0300, Serge Semin wrote:
> > On Fri, May 29, 2020 at 06:18:32PM +0100, Mark Brown wrote:
> > > On Fri, 29 May 2020 16:11:49 +0300, Serge Semin wrote:
> > > > B
Mark
On Fri, May 29, 2020 at 06:18:32PM +0100, Mark Brown wrote:
> On Fri, 29 May 2020 16:11:49 +0300, Serge Semin wrote:
> > Baikal-T1 SoC provides a DW DMA controller to perform low-speed peripherals
> > Mem-to-Dev and Dev-to-Mem transaction. This is also applicable to the
On Fri, May 29, 2020 at 06:33:25PM +0100, Mark Brown wrote:
> On Fri, May 29, 2020 at 08:26:42PM +0300, Serge Semin wrote:
>
> > You must have missed the patch 16:
> > 0e8332aaf059 dt-bindings: spi: Convert DW SPI binding to DT schema
> > As you can see it has been acked
Hello Lars,
On Wed, May 13, 2020 at 04:00:21PM +0200, Lars Povlsen wrote:
> This is an add-on series to the main SoC Sparx5 series
> (Message-ID: <20200513125532.24585-1-lars.povl...@microchip.com>).
>
> The series add support for Sparx5 on top of the existing
> ocelot/jaguar2 spi driver.
>
>
overrides in the next commits.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
Changelog v3:
- This is a new patch created as a result of the discussion with Vinud and
Andy
will cause less dw_desc allocations, less LLP reinitializations,
better DMA device performance.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
then the LLP register is hardcoded to
zero, so the blocks chaining based on the LLPs is unsupported.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
. The channels and
controller-specific max_burst length initialization will be introduced
by the follow-up patches.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
Changelog
capability
we make sure a DMA consumer will get the channel-specific max burst
length.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
Changelog v2
" and
"interrupts", which will be used by the driver to correctly find the
controller memory region and handle its events. The rest of the properties
are optional, since in case if either "dma-channels" or "dma-masters" isn't
specified, the driver will attempt to auto-d
DMA transaction.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
Changelog v3:
- This is a new patch created as a result of the discussion
with 0 if there is no limitation for the number of SG entries
atomically executed and with non-zero value if there is such constraints,
so the upper limit is determined by the number set to the property.
Suggested-by: Andy Shevchenko
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc
if provided it gets called from the dma_get_slave_caps() method and is
able to override the generic DMA-device capabilities.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Andy Shevchenko
Cc: Rob Herring
Cc: linux-m
Some hardware aside from default 0/1 may have greater minimum burst
transactions length constraints. Here we introduce the DMA device
and slave capability, which if required can be initialized by the DMA
engine driver with the device-specific value.
Signed-off-by: Serge Semin
Reviewed-by: Andy
r
Cc: Arnd Bergmann
Cc: Andy Shevchenko
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: dmaeng...@vger.kernel.org
Cc: devicet...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Serge Semin (11):
dt-bindings: dma: dw: Convert DW DMAC to DT binding
dt-bindings: dma: dw: Add max burst transacti
This array property is used to indicate the maximum burst transaction
length supported by each DMA channel.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Andy Shevchenko
Cc: linux-m...@vger.kernel.org
---
Changelog v2:
- Rearrange SoBs.
- Move
On Fri, May 29, 2020 at 03:12:03PM +0300, Andy Shevchenko wrote:
> On Fri, May 29, 2020 at 01:23:55AM +0300, Serge Semin wrote:
> > There are DMA devices (like ours version of Synopsys DW DMAC) which have
> > DMA capabilities non-uniformly redistributed amongst the device channel
the
SPI_CONTROLLER_MUST_TX flag for DMA-capable platform.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Georgy Vlasov
Cc: Ramil Zaripov
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Feng Tang
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
-off-by: Georgy Vlasov
Co-developed-by: Ramil Zaripov
Signed-off-by: Ramil Zaripov
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Maxim Kaurkin
Cc: Pavel Parkhomenko
Cc: Ekaterina Skachko
Cc: Vadim Vlasov
Cc: Alexey Kolotnikov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Andy Shevchenko
. Especially seeing that we don't use anything DW DMAC
specific in the new driver.
Co-developed-by: Georgy Vlasov
Signed-off-by: Georgy Vlasov
Co-developed-by: Ramil Zaripov
Signed-off-by: Ramil Zaripov
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Alexey Malahov
Cc: Thomas
DebugFS kernel interface provides a dedicated method to create the
registers dump file. Use it instead of creating a generic DebugFS
file with manually written read callback function.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Georgy Vlasov
Cc: Ramil Zaripov
Cc: Alexey
, DMA and slave device
sub-nodes are optional.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
Cc: Georgy Vlasov
Cc: Ramil Zaripov
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Feng Tang
Cc: Andy Shevchenko
Cc: Arnd Bergmann
Cc: linux-m...@vger.kernel.org
---
.../bindings/spi/snps,dw-apb
-off-by: Ramil Zaripov
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Feng Tang
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
Changelog v3:
- Discard the dws->fifo_len utilizat
Signed-off-by: Ramil Zaripov
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Feng Tang
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
Changelog v2:
- Leave the DMA setup method suffixes
for generic "snps,dw-apb-ssi" and "snps,dwc-ssi-1.01a"
devices.
Co-developed-by: Georgy Vlasov
Signed-off-by: Georgy Vlasov
Co-developed-by: Ramil Zaripov
Signed-off-by: Ramil Zaripov
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Alexey Malahov
Cc: Thomas Bogendoerfe
Signed-off-by: Ramil Zaripov
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Feng Tang
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
drivers/spi/Kconfig | 9 ++---
1 file changed
procedure. This will be needed to fix the problem
when DMA transactions are finished, but there is still data left in
the SPI Tx/Rx FIFOs being sent/received. But for now make dma_transfer
to return 1 as the normal dw_spi_transfer_one() method.
Signed-off-by: Serge Semin
Cc: Georgy Vlasov
Cc: Ramil
at some point of doing their duties.
Fixes: 7063c0d942a1 ("spi/dw_spi: add DMA support")
Co-developed-by: Georgy Vlasov
Signed-off-by: Georgy Vlasov
Signed-off-by: Serge Semin
Cc: Ramil Zaripov
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Andy Shevchenko
Cc: Fen
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Feng Tang
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
Changelog v2:
- Compile the DW SPI DMA module into the DW APB SSI core
Generic DMA support is going to be part of the DW APB SSI core object.
In order to preserve the kernel loadable module name as spi-dw.ko, let's
add the "-core" suffix to the object with generic DW APB SSI code and
build it into the target spi-dw.ko driver.
Signed-off-by: Serge Semin
. By doing so the core will be able to
execute the xfer-related delays with better accuracy.
Signed-off-by: Serge Semin
Cc: Georgy Vlasov
Cc: Ramil Zaripov
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Feng Tang
Cc: Andy Shevchenko
Cc: Rob Herring
Cc: linux-m
pport")
Co-developed-by: Georgy Vlasov
Signed-off-by: Georgy Vlasov
Signed-off-by: Serge Semin
Cc: Ramil Zaripov
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Andy Shevchenko
Cc: Feng Tang
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.
level to be of FIFO depth minus the
maximum burst transactions length. To prevent the Rx buffer underflow
the DMA Rx level should be set to the maximum burst transactions length.
This commit setups the DMA channels and the DW SPI DMA Tx/Rx levels
in accordance with these rules.
Signed-off-by: Serge
with zero
returned signalling to the SPI core that the SPI transfer is finished.
This implementation is fully equivalent to the currently used
DMA-execution-SPI-core-wait algorithm. The SPI-bus transmission/reception
wait methods will be added in the follow-up commits.
Signed-off-by: Serge Semin
Cc
On Fri, May 29, 2020 at 01:50:09PM +0300, Andy Shevchenko wrote:
> On Fri, May 29, 2020 at 01:41:19PM +0300, Serge Semin wrote:
> > On Fri, May 29, 2020 at 01:29:02PM +0300, Andy Shevchenko wrote:
> > > On Fri, May 29, 2020 at 01:25:15PM +0300, Andy Shevchenko wrote:
> >
On Fri, May 29, 2020 at 01:29:02PM +0300, Andy Shevchenko wrote:
> On Fri, May 29, 2020 at 01:25:15PM +0300, Andy Shevchenko wrote:
> > On Fri, May 29, 2020 at 01:23:59AM +0300, Serge Semin wrote:
> > > According to the DW APB DMAC data book the minimum burst transaction
> >
On Fri, May 29, 2020 at 12:46:48PM +0300, Andy Shevchenko wrote:
> On Fri, May 29, 2020 at 06:59:03AM +0300, Serge Semin wrote:
> > Having any data left in the Rx FIFO after the DMA engine claimed it has
> > finished all DMA transactions is an abnormal situation, since the DW SPI
On Fri, May 29, 2020 at 12:26:10PM +0300, Andy Shevchenko wrote:
> On Fri, May 29, 2020 at 11:12:04AM +0300, Serge Semin wrote:
> > On Fri, May 29, 2020 at 10:55:32AM +0300, Andy Shevchenko wrote:
> > > On Fri, May 29, 2020 at 7:02 AM Serge Semin
> > > wrote:
On Fri, May 29, 2020 at 11:49:12AM +0300, Sergei Shtylyov wrote:
> Hello!
>
> On 29.05.2020 6:58, Serge Semin wrote:
>
> > Seeing DW APB SSI controller doesn't support setting the exactly
> > requested SPI bus frequency, but only a rounded frequency determined
> >
On Fri, May 29, 2020 at 10:55:32AM +0300, Andy Shevchenko wrote:
> On Fri, May 29, 2020 at 7:02 AM Serge Semin
> wrote:
> >
> > Even if DMA transactions are finished it doesn't mean that the SPI
> > transfers are also completed. It's specifically concerns the Tx-only
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