On 27/10/16 19:01, Kevin Hilman wrote:
Tero Kristo writes:
On 19/10/16 02:08, Nishanth Menon wrote:
Version 4 of the series is basically a rebase to v4.9-rc1, no functional
changes.
Any final comments on this series, or shall I send a pull-req forward?
Very minimal changes compared to v3
On 19/10/16 02:08, Nishanth Menon wrote:
Version 4 of the series is basically a rebase to v4.9-rc1, no functional
changes.
Hi,
Any final comments on this series, or shall I send a pull-req forward?
Very minimal changes compared to v3 so should be good to go imo.
-Tero
Texas Instruments'
On 08/09/16 20:31, Kevin Hilman wrote:
Nishanth Menon writes:
On 09/07/2016 01:55 PM, Kevin Hilman wrote:
Nishanth Menon writes:
[...] full mail thread in https://lkml.org/lkml/2016/9/6/747
Overall architecture is very similar to SCPI[4] as follows:
Dumb Q: I'm curious about the limita
On 02/09/16 23:27, Dave Gerlach wrote:
On 09/02/2016 12:07 PM, Nishanth Menon wrote:
Rob,
On Fri, Sep 2, 2016 at 10:06 AM, Rob Herring wrote:
On Tue, Aug 30, 2016 at 08:06:43AM -0500, Nishanth Menon wrote:
[...]
+
+TI-SCI Client Device Node:
+
+
+Client nodes refer t
On 01/09/16 01:31, Stephen Boyd wrote:
On 08/31, Tero Kristo wrote:
On 24/08/16 11:34, Stephen Boyd wrote:
On 08/19, Nishanth Menon wrote:
diff --git a/drivers/clk/keystone/sci-clk.c b/drivers/clk/keystone/sci-clk.c
new file mode 100644
index ..6c43e097e6d6
--- /dev/null
+++ b
Hi Santosh,
The following changes since commit 29b4817d4018df78086157ea3a55c1d9424a7cfc:
Linux 4.8-rc1 (2016-08-07 18:18:00 -0700)
are available in the git repository at:
https://github.com/t-kristo/linux-pm.git 4.8-rc1-ti-sci-fw
for you to fetch changes up to 7a2c510cdfa6a4b2f4200c122a37
dex ..6c43e097e6d6
--- /dev/null
+++ b/drivers/clk/keystone/sci-clk.c
@@ -0,0 +1,539 @@
+/*
+ * SCI Clock driver for keystone based devices
+ *
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ * Tero Kristo
+ *
+ * This program is free software; you can
On 29/06/16 19:11, Bin Liu wrote:
Some software alg has cra_priority as higher as 300, so increase
omap-sham priority to 400 to ensure it is on top of any software alg.
You could mention the case where this is causing issues, namely the
arm-neon-sha implementations which currently have priorit
On 25/05/16 19:09, Nishanth Menon wrote:
On 05/25/2016 07:53 AM, Ravikumar Kattekola wrote:
DRA72x devices have a sixth i2c ocntroller instance.
Following patches add the required hwmod structure and
device tree nodes.
Reference doc: DRA72x TRM [ SPRUHP2Q ]
Tested on :
DRA72x Rev B EVM
Raviku
On 09/05/16 16:52, Peter Ujfalusi wrote:
On 05/09/16 15:46, Peter Ujfalusi wrote:
On 05/09/16 15:32, Peter Ujfalusi wrote:
On 05/09/16 15:10, Peter Ujfalusi wrote:
finally I found some time to apply your patches. Sorry for the long time.
Unfortunately, it does not work. Neither on omap5evm n
On 09/05/16 14:18, H. Nikolaus Schaller wrote:
Hi,
Am 28.04.2016 um 15:23 schrieb Tero Kristo :
On 28/04/16 12:12, H. Nikolaus Schaller wrote:
Hi Tero,
Am 28.04.2016 um 10:03 schrieb Tero Kristo :
On 27/04/16 17:35, H. Nikolaus Schaller wrote:
HI,
Am 27.04.2016 um 16:23 schrieb Peter
On 03/05/16 20:49, J.D. Schroeder wrote:
On 05/03/2016 12:32 PM, Tero Kristo wrote:
Personally I would not recommend using this clock for any timing sensitive
applications. May I ask why you are interested in the exact clock rate of this
clock anyway?
I'm not interested in using this
On 03/05/16 19:43, Tony Lindgren wrote:
* J.D. Schroeder [160503 06:32]:
On 05/03/2016 03:16 AM, Tero Kristo wrote:
On 02/05/16 20:12, J.D. Schroeder wrote:
From: "J.D. Schroeder"
This commit updates the OSC_32K_CLK (secure_32k_clk_src_ck) frequency
from the precise 32kHz freq
On 02/05/16 20:12, J.D. Schroeder wrote:
From: "J.D. Schroeder"
This commit updates the OSC_32K_CLK (secure_32k_clk_src_ck) frequency
from the precise 32kHz frequency (i.e., 32.768 kHz) to a more
accurate frequency of ~34.6 kHz. Actual measured frequencies of the
clock vary from processor to pr
On 28/04/16 12:12, H. Nikolaus Schaller wrote:
Hi Tero,
Am 28.04.2016 um 10:03 schrieb Tero Kristo :
On 27/04/16 17:35, H. Nikolaus Schaller wrote:
HI,
Am 27.04.2016 um 16:23 schrieb Peter Ujfalusi :
On 04/27/2016 05:10 PM, Tero Kristo wrote:
On 27/04/16 16:10, H. Nikolaus Schaller wrote
On 27/04/16 17:35, H. Nikolaus Schaller wrote:
HI,
Am 27.04.2016 um 16:23 schrieb Peter Ujfalusi :
On 04/27/2016 05:10 PM, Tero Kristo wrote:
On 27/04/16 16:10, H. Nikolaus Schaller wrote:
Am 27.04.2016 um 14:31 schrieb Tero Kristo :
On 27/04/16 09:04, H. Nikolaus Schaller wrote:
Am
On 27/04/16 17:06, J.D. Schroeder wrote:
On 04/27/2016 06:40 AM, Tero Kristo wrote:
On 26/04/16 20:54, J.D. Schroeder wrote:
This commit fixes the 32kHz clock (sys_32k_ck) calculation to be
correctly based on the SYS_CLK1 (sys_clkin1) frequency. Based on the
TRM CTRL_CORE_BOOTSTRAP[9:8
On 27/04/16 16:10, H. Nikolaus Schaller wrote:
Am 27.04.2016 um 14:31 schrieb Tero Kristo :
On 27/04/16 09:04, H. Nikolaus Schaller wrote:
Am 26.04.2016 um 19:27 schrieb Tony Lindgren :
Tero,
* H. Nikolaus Schaller [160418 11:23]:
OMAP5 has a register to control if the ckobuffer is
shouldn't remove the old entries.
Signed-off-by: Franklin S Cooper Jr
Acked-by: Stephen Boyd
I don't like adding new clock aliases to the list as I am trying to get
rid of them, but in this case we can't avoid it I believe. Thus,
Acked-by: Tero Kristo
---
drivers/clk/ti
On 27/04/16 09:04, H. Nikolaus Schaller wrote:
Am 26.04.2016 um 19:27 schrieb Tony Lindgren :
Tero,
* H. Nikolaus Schaller [160418 11:23]:
OMAP5 has a register to control if the ckobuffer is enabled
and defines the polarity. ckobuffer is required to drive a twl6040
with the system clock. He
On 26/04/16 20:54, J.D. Schroeder wrote:
From: "J.D. Schroeder"
This commit updates the OSC_32K_CLK (secure_32k_clk_src_ck) frequency
from the precise 32kHz frequency (i.e., 32.768 kHz) to the more
accurate frequency of ~34.6 kHz. Actual measured frequencies of the
clock vary from board to boar
On 26/04/16 20:54, J.D. Schroeder wrote:
From: "J.D. Schroeder"
This commit fixes the 32kHz clock (sys_32k_ck) calculation to be
correctly based on the SYS_CLK1 (sys_clkin1) frequency. Based on the
TRM CTRL_CORE_BOOTSTRAP[9:8] SPEEDSELECT, set by the SYSBOOT[9:8]
board jumpers according to the
nce in our
clock data across SoCs. Good catch.
Acked-by: Tero Kristo
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index d0bae06..9d1a
On 22/04/16 14:52, Peter Ujfalusi wrote:
On 04/22/16 01:29, Stephen Boyd wrote:
The first issue with converting the McASP to use CCF internally for clock
selection, muxing and rate configuration is that the daVinci platform does not
use CCF at all. Given that the davinci-mcasp driver is used by
On 18/04/16 14:59, Mark Brown wrote:
On Mon, Apr 18, 2016 at 02:49:53PM +0300, Tero Kristo wrote:
suspend_prepare can be called during regulator init time also, where
It can be? That seems unexpected...
regulator_register()
-> set_machine_constraints()
-> suspend_prepare()
Cal
other problems (some APIs used during init
will attempt to lock the mutex also, causing deadlock.)
Signed-off-by: Tero Kristo
Reported-by: Tomi Valkeinen
---
drivers/regulator/core.c |2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
On 04/01/2016 06:36 PM, Tony Lindgren wrote:
Hi,
* Tony Lindgren [160331 10:04]:
* Keerthy [160331 02:26]:
On Thursday 31 March 2016 12:00 PM, Tero Kristo wrote:
On 03/31/2016 12:32 AM, Tony Lindgren wrote:
* Tony Lindgren [160330 14:19]:
* Keerthy [160314 05:04]:
This is w.r.t J6
seudo clock naming here. So dropping for now.
The patch is fine for me, I didn't comment anything before as I thought
you already applied it.
Acked-by: Tero Kristo
Regards,
Tony
On 03/21/2016 08:43 PM, Stephen Boyd wrote:
On 03/17, Franklin S Cooper Jr wrote:
Add tblck to the pwm nodes. This insures that the ehrpwm driver has access
to the time-based clk.
Do not remove similar entries for ehrpwm node. Later patches will switch
from using ehrpwm node name to pwm. But to
The last one looks like a real bug because we don't return an
error on allocation failure.
Yeah nice, that's a real bug:
Tested-by: Tony Lindgren
Looks good to me also.
Acked-by: Tero Kristo
On 03/01/2016 09:00 PM, Stephen Boyd wrote:
This flag is a no-op now. Remove usage of the flag.
Cc: Tero Kristo
Signed-off-by: Stephen Boyd
Acked-by: Tero Kristo
---
drivers/clk/ti/clk.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/ti/clk.c b
On 03/01/2016 01:23 AM, Tony Lindgren wrote:
* Franklin S Cooper Jr [160225 14:37]:
From: Vignesh R
tbclk is used by ehrpwm to generate PWM waveform on DRA7 SoC. Add Linux
clock to control ehrpwm tbclk.
The TRM says, tbclk is derived from SYSCLKOUT. SYSCLKOUT is nothing but
ehrpwm functional
On 12/08/2015 10:11 PM, Tony Lindgren wrote:
* Tero Kristo [151208 11:25]:
On 12/08/2015 06:57 PM, Tony Lindgren wrote:
Anybody from the clock department care to ack this one?
Sorry been rather busy lately...
I'd like to
get this series into Linux next as it fixes some some i
On 12/08/2015 06:57 PM, Tony Lindgren wrote:
* Tony Lindgren [151201 15:43]:
The timer clock aliases are needed early on dm814x. Let's also
add the aliases for the interconnects and MMC.
Cc: Michael Turquette
Cc: Stephen Boyd
Cc: Tero Kristo
Signed-off-by: Tony Lindgren
Anybody fro
On 11/13/2015 06:29 PM, Neil Armstrong wrote:
Add missing clkdev dmtimer related entries for dm816x.
32Khz and ext sources were missing.
Cc: Brian Hutchinson
Acked-by: Tony Lindgren
Signed-off-by: Neil Armstrong
Your own sign-off should be at the top of the list, fixed this locally
myself.
becomes 0x0a instead of the expected 0x10.
Fix by moving the +1 addition within the bin2bcd call also.
Fixes: 1d1945d261a2 ("drivers/rtc/rtc-ds1307.c: add alarm support for mcp7941x
chips")
Signed-off-by: Tero Kristo
---
drivers/rtc/rtc-ds1307.c |4 ++--
1 file changed, 2 insert
On 09/30/2015 01:37 AM, Suman Anna wrote:
The default clock enabling functions for TI clocks -
omap2_dflt_clk_enable() and omap2_dflt_clk_disable() perform a
NULL check for the enable_reg field of the clk_hw_omap structure.
This enable_reg field however is merely a combination of the index
of the
On 09/30/2015 01:06 PM, Peter Ujfalusi wrote:
Paul,
On 09/27/2015 10:02 AM, Paul Walmsley wrote:
/*
+ * 'mcasp' class
+ *
+ */
+static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
+ .sysc_offs = 0x0004,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes
On 09/25/2015 09:59 AM, Peter Ujfalusi wrote:
Tero,
On 09/16/2015 09:42 AM, Tero Kristo wrote:
On 09/14/2015 11:52 AM, Peter Ujfalusi wrote:
Hi Tero,
On 08/24/2015 10:35 AM, Peter Ujfalusi wrote:
The ABE related clocks should be configured via DT and not have it wired
inside of the kernel
On 09/14/2015 11:52 AM, Peter Ujfalusi wrote:
Hi Tero,
On 08/24/2015 10:35 AM, Peter Ujfalusi wrote:
The ABE related clocks should be configured via DT and not have it wired
inside of the kernel.
can you take a look at this patch? It will not cause any regression since we
do not have audio su
oards accessible to me, and seems to work fine.
So, once the subject is fixed, for TI relevant parts for patches 2, 5,
7, 8, 23:
Acked-by: Tero Kristo
-Tero
Cc: Tero Kristo
Signed-off-by: Stephen Boyd
---
drivers/clk/ti/autoidle.c | 8
drivers/clk/ti/clkt_dpll.c | 11 ++-
dr
On 07/27/2015 01:27 PM, Roger Quadros wrote:
Hi,
This series cleans up the scm_conf node.
v2:
- split patch. use only core_sma_sw registers for the new scm_conf child.
Series looks ok to me, so:
Acked-by: Tero Kristo
cheers,
-roger
Roger Quadros (3):
ARM: dts: dra7: Remove ctrl_core
On 07/17/2015 04:47 PM, Roger Quadros wrote:
This register is required to be passed to the SATA PHY driver
to workaround errata i783 (SATA Lockup After SATA DPLL Unlock/Relock).
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/dra7.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/a
On 07/17/2015 04:47 PM, Roger Quadros wrote:
scm_conf1 maps the control register address space after the
padconf till the end.
Fix the scm_conf and pmx_core resource lengths. We need to add
4 bytes to include the last 32-bit register space.
Remove the redundant dra7_ctrl_core and dra7_ctrl_gene
-3xxx.c | 10 --
drivers/clk/ti/clk.c | 6 --
2 files changed, 4 insertions(+), 12 deletions(-)
For the whole set:
Acked-by: Tero Kristo
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uct.
Anyway, I guess we can fix the ssi/usb clocks later if we find some
issues with them, its been at least 3 years since these have been used.
-Tero
Cc: Tero Kristo
Signed-off-by: Stephen Boyd
---
drivers/clk/ti/clk-3xxx.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/dr
On 07/15/2015 04:47 PM, Roger Quadros wrote:
Hi,
On 15/07/15 15:07, Tony Lindgren wrote:
* Kishon Vijay Abraham I [150715 04:24]:
Hi Roger,
On Tuesday 02 June 2015 02:40 PM, Roger Quadros wrote:
This register is required to be passed to the SATA PHY driver
to workaround errata i783 (SATA Lo
: Mugunthan V N
Thanks Mugunthan.
A gentle ping on this series.
Tero, care to review this series?
Acked-by: Tero Kristo
I guess this should go through your tree as this is mostly dts changes?
-Tero
Regards,
Tony
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On 07/11/2015 02:33 AM, Stephen Boyd wrote:
This clock provider uses the consumer API, so include clk.h
explicitly.
Cc: Tero Kristo
Signed-off-by: Stephen Boyd
Acked-by: Tero Kristo
---
drivers/clk/ti/apll.c| 1 +
drivers/clk/ti/clk-33xx.c| 1 +
drivers/clk/ti/clk
On 07/11/2015 02:33 AM, Stephen Boyd wrote:
This file isn't a clock provider but uses the consumer API, so
include clk.h instead of clk-provider.h.
Cc: Tero Kristo
Signed-off-by: Stephen Boyd
Acked-by: Tero Kristo
---
drivers/clk/ti/clk-2xxx.c | 2 +-
1 file changed, 1 insertion(
On 07/11/2015 01:45 AM, Stephen Boyd wrote:
These files use the consumer API, so include clk.h explicitly.
Cc: Tero Kristo
Cc: Tony Lindgren
Signed-off-by: Stephen Boyd
---
Please ack so this can be routed through clk-tree. Otherwise
when clk.h is removed from clk-provider.h these files
milio López"
CC: Maxime Ripard
CC: Tero Kristo
CC: Peter De Schrijver
CC: Prashant Gaikwad
CC: Stephen Warren
CC: Thierry Reding
CC: Alexandre Courbot
CC: linux-...@vger.kernel.org
CC: linux-kernel@vger.kernel.org
CC: linux-arm-ker...@lists.infradead.org
CC: linux-o...@vger.kernel.org
CC:
to me, not going to try to review patch 5 as I
have no clue about PWM driver itself. So, for 1-4:
Acked-by: Tero Kristo
Some of the patches cause trivial merge conflicts with 4.2-rc1 though.
-Tero
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the bo
On 06/22/2015 09:22 AM, Keerthy wrote:
Add the PRM IRQ register offsets.
This patch doesn't apply cleanly to 4.2-rc1.
-Tero
Signed-off-by: Keerthy
---
arch/arm/mach-omap2/prcm43xx.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-o
On 06/22/2015 09:22 AM, Keerthy wrote:
The register offsets of IRQENABLE_MPU_2 and IRQSTATUS_MPU_2 are hardcoded.
This makes it difficult to reuse the code for single core SoCs like AM437x.
Single core vs. having two sets of IRQENABLE / IRQSTATUS registers do
not have any relation to each othe
_mask = (1 << 25), /* WAKEUPEVENT */
};
Tero, care to take a look at this one and ack if OK?
Looks fine to me.
Acked-by: Tero Kristo
Regards,
Tony
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please. Or use a mailer that doesn't convert tabs to
spaces. This patch seems to have something else that is strange also.
Cc: Paul Walmsley mailto:p...@pwsan.com>>
Cc: Tero Kristo mailto:t-kri...@ti.com>>
Cc: Tony Lindgren mailto:t...@atomide.com>>
Signed-off-by: Brian Hu
only.
-Tero
Cc: Paul Walmsley mailto:p...@pwsan.com>>
Cc: Tero Kristo mailto:t-kri...@ti.com>>
Cc: Tony Lindgren mailto:t...@atomide.com>>
Signed-off-by: Brian Hutchinson mailto:b.hutch...@gmail.com><mailto:t...@atomide.com>>
--- arch/arm/mach-omap2/omap_hwmod_81
On 06/01/2015 02:53 PM, Vignesh R wrote:
tbclk is used by ehrpwm to generate PWM waveform on DRA7 SoC. Add Linux
clock to control ehrpwm tbclk.
Care to add TRM reference here?
-Tero
Signed-off-by: Vignesh R
---
arch/arm/boot/dts/dra7.dtsi | 5 +
arch/arm/boot/dts/dra7xx-cl
On 06/01/2015 02:53 PM, Vignesh R wrote:
Add hwmod entries for the PWMSS on DRA7.
Can you provide some documentation references for this data?
I was looking at the TRM and at least the main_clk selection is somewhat
unclear to me.
-Tero
Signed-off-by: Vignesh R
---
arch/arm/mach-omap2
On 05/25/2015 05:24 PM, Bartosz Golaszewski wrote:
Hi Tero,
I tried booting a BeagleBone Black Rev C with current git, but got no
output after u-boot's "Starting kernel ...". Bisect points at commit
e3bc5358 ARM: dts: am33xx: add minimal l4 bus layout with control
module support. Let me know if
On 05/13/2015 09:54 AM, Krzysztof Kozlowski wrote:
Hi,
clk_get_sys() may return ERR_PTR but the drivers immediately
dereferenced the return value. This could lead to oops.
I tried only to fix possible ERR_PTR dereference and to not change
the logic. This is why some of the patches look quite c
On 05/07/2015 09:18 PM, Stephen Boyd wrote:
On 05/07/15 01:22, Tero Kristo wrote:
On 05/02/2015 02:40 AM, Stephen Boyd wrote:
On 05/01/15 15:07, Heiko Stübner wrote:
Am Freitag, 1. Mai 2015, 13:52:47 schrieb Stephen Boyd:
Instead I guess we could hook it less deep into clk_get_sys, like
in
t with
my patch and a note that it's based on an earlier patch from you.
FWIW, just gave a try for these two patches on all TI boards I have
access to.
Tested-by: Tero Kristo
I didn't try your evolved patch though, as you don't seem to have made
your mind yet.
-Tero
T
tl_clk_ops' was not
declared. Should it be static?
drivers/clk/ti/clk-dra7-atl.c:170:39: warning: Using plain integer as NULL
pointer
Cc: Peter Ujfalusi
Cc: Tero Kristo
Signed-off-by: Stephen Boyd
Acked-by: Peter Ujfalusi
Yes looks good to me also.
Acked-by: Tero Kristo
---
dri
, 2015 at 07:32:32AM +0300, Tero Kristo wrote:
On 04/15/2015 11:51 PM, Michael Welling wrote:
On Wed, Apr 15, 2015 at 01:45:53PM -0700, Mike Turquette wrote:
On Wed, Apr 15, 2015 at 12:47 PM, Michael Welling wrote:
[...]
There is still an issue with the si5351.
I had to comment out the clk_put
On 04/15/2015 11:51 PM, Michael Welling wrote:
On Wed, Apr 15, 2015 at 01:45:53PM -0700, Mike Turquette wrote:
On Wed, Apr 15, 2015 at 12:47 PM, Michael Welling wrote:
On Wed, Apr 15, 2015 at 09:43:30PM +0300, Tero Kristo wrote:
On 04/15/2015 05:09 PM, Michael Welling wrote:
On Wed, Apr 15
On 04/15/2015 05:09 PM, Michael Welling wrote:
On Wed, Apr 15, 2015 at 09:34:48AM +0300, Tero Kristo wrote:
On 04/15/2015 12:17 AM, Michael Welling wrote:
Greetings,
I have developed an AM3354 based SoM and it uses an external SI5351 clock
generator to drive the clock inputs for an external
On 04/15/2015 12:17 AM, Michael Welling wrote:
Greetings,
I have developed an AM3354 based SoM and it uses an external SI5351 clock
generator to drive the clock inputs for an external duart and I2S audio
master clock. With the registration according to the documentation the
reference clock is no
On 03/24/2015 06:37 PM, Tony Lindgren wrote:
* Tony Lindgren [150323 08:58]:
* Tero Kristo [150323 06:25]:
This code is generating these compile time warnings for me:
CC drivers/clk/ti/fapll.o
drivers/clk/ti/fapll.c: In function ‘ti_fapll_synth_set_rate’:
drivers/clk/ti/fapll.c:394
On 03/14/2015 12:58 AM, Suman Anna wrote:
Hi Tero,
Please find couple of cleanup/fixes on the DT clock aliases
for the GPTimers. Patches are based on 4.0-rc1 and following
is the summary of the changes,
1. Patch 1 is a cleanup for OMAP4
2. Patch 2 fixes the failures for OMAP5 if omap_dm_timer_s
On 03/16/2015 12:40 PM, Peter Ujfalusi wrote:
Hi,
This series will fix the following error during boot (both DT and legacy boot):
[0.307739] omap_hwmod: mcbsp2: _wait_target_ready failed: -16
[0.307769] omap_hwmod: mcbsp2: cannot be enabled for reset (3)
The clock definitions/aliases fo
d a define for the fixed SYNTH_PHASE_K instead of using 8.
Cc: Brian Hutchinson
Cc: Matthijs van Duin
Cc: Tero Kristo
Signed-off-by: Tony Lindgren
---
drivers/clk/ti/fapll.c | 134 -
1 file changed, 132 insertions(+), 2 deletions(-)
diff --git
On 03/20/2015 11:54 PM, Eduardo Valentin wrote:
On Fri, Mar 20, 2015 at 02:47:39PM -0500, Nishanth Menon wrote:
From: Tero Kristo
OMAP4 has a finer counter granularity, which allows for a delay of 1000ms
in the thermal zone polling intervals. OMAP5/DRA7 have different counter
mechanism, which
, sorry about that.
Acked-by: Tero Kristo
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+--
2 files changed, 118 insertions(+), 13 deletions(-)
Hi Benoit,
Can these fixes be looked into for 3.20-rc?
Seem like valid fixes to me. Tero, care to take a look at these and ack
if OK?
Yes, both are good to go.
Acked-by: Tero Kristo
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On 02/03/2015 09:03 AM, Tomeu Vizoso wrote:
On 02/02/2015 11:41 PM, Mike Turquette wrote:
Quoting Tero Kristo (2015-02-02 11:32:01)
On 02/01/2015 11:24 PM, Mike Turquette wrote:
Quoting Tomeu Vizoso (2015-01-23 03:03:30)
Moves clock state to struct clk_core, but takes care to change as
rate constraints patch broke boot for me completely, but sounds
like you reverted it already.
-Tero
Author: Tero Kristo
Date: Mon Feb 2 17:19:17 2015 +0200
ARM: OMAP3+: clock: dpll: fix logic for comparing parent clocks
DPLL code uses reference and bypass cloc
On 12/17/2014 05:53 PM, Nishanth Menon wrote:
On 17:45-20141217, Tero Kristo wrote:
On 12/17/2014 05:27 PM, Lennart Sorensen wrote:
On Wed, Dec 17, 2014 at 09:22:25AM -0600, Nishanth Menon wrote:
A clock mux might do the job?
value 1, 2 , 3 will imply sysclk1 / 610
value of 0 implies fixed
On 12/17/2014 05:27 PM, Lennart Sorensen wrote:
On Wed, Dec 17, 2014 at 09:22:25AM -0600, Nishanth Menon wrote:
A clock mux might do the job?
value 1, 2 , 3 will imply sysclk1 / 610
value of 0 implies fixed 32768
soemthing like
sys_clk32_crystal {
compatible = "fixed-clock";
On 12/16/2014 04:58 PM, Nishanth Menon wrote:
On 17:05-20141216, Lokesh Vutla wrote:
[...]
@@ -545,6 +546,16 @@ static void __init realtime_counter_init(void)
break;
}
+ if (soc_is_dra7xx()) {
+ reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
+
based on struct
clk_divider.
Signed-off-by: Mike Turquette
[james.ho...@imgtec.com: forward port, fix new uses of width]
Signed-off-by: James Hogan
Tested-by: Shawn Guo
Tested-by: Heiko Stuebner
Reviewed-by: Heiko Stuebner
Cc: "Emilio López"
Cc: Sascha Hauer
Cc: Shawn Guo
Cc: Tero
On 11/14/2014 01:58 AM, Tony Lindgren wrote:
* Paul Walmsley [141113 15:01]:
Hi
On Thu, 13 Nov 2014, Tony Lindgren wrote:
* Tomi Valkeinen [141113 03:33]:
On 12/11/14 17:02, Tony Lindgren wrote:
And, with a quick grep, I see CONTROL_DEVCONF1 touched in multiple
places in the kernel. I wo
Hi Tomeu,
Please add a changelog to this patch. Also, just replace the
clk-private.h includes with clk-provider.h, do not add the include to
the generic header. Rest of the kernel does that where needed.
Other than that, looks good to me.
-Tero
On 10/03/2014 06:51 PM, Tomeu Vizoso wrote:
S
On 09/30/2014 09:16 PM, Tony Lindgren wrote:
* Tero Kristo [140930 00:41]:
On 09/30/2014 09:54 AM, Mike Turquette wrote:
Quoting Stephen Boyd (2014-09-29 18:40:23)
On 09/29/14 11:17, Tomeu Vizoso wrote:
Also moves clock state to struct clk_core, but takes care to change as little
API as
On 09/30/2014 10:03 PM, Mike Turquette wrote:
Quoting Tero Kristo (2014-09-30 01:48:49)
On 09/30/2014 10:07 AM, Mike Turquette wrote:
Quoting Tero Kristo (2014-09-29 01:09:24)
On 09/27/2014 02:24 AM, Mike Turquette wrote:
Quoting Tero Kristo (2014-09-26 00:18:55)
On 09/26/2014 04:35 AM
On 09/30/2014 10:07 AM, Mike Turquette wrote:
Quoting Tero Kristo (2014-09-29 01:09:24)
On 09/27/2014 02:24 AM, Mike Turquette wrote:
Quoting Tero Kristo (2014-09-26 00:18:55)
On 09/26/2014 04:35 AM, Stephen Boyd wrote:
On 09/23/14 06:38, Tero Kristo wrote:
On 09/22/2014 10:18 PM, Stephen
On 09/30/2014 09:54 AM, Mike Turquette wrote:
Quoting Stephen Boyd (2014-09-29 18:40:23)
On 09/29/14 11:17, Tomeu Vizoso wrote:
Also moves clock state to struct clk_core, but takes care to change as little
API as possible.
struct clk_hw still has a pointer to a struct clk, which is the
impleme
On 09/27/2014 03:57 AM, Behan Webster wrote:
On 09/26/14 17:55, Felipe Balbi wrote:
On Fri, Sep 26, 2014 at 05:31:48PM -0700, Behan Webster wrote:
As written, the __init for ti_clk_get_div_table is in the middle of
the return
type.
The gcc documentation indicates that section attributes should
On 09/29/2014 11:10 AM, Peter Ujfalusi wrote:
It is safe to call the pm sync calls in interrupt context in this driver.
Signed-off-by: Peter Ujfalusi
Thanks, applied to for-v3.18/ti-clk-drv.
-Tero
---
drivers/clk/ti/clk-dra7-atl.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/driv
On 09/27/2014 02:24 AM, Mike Turquette wrote:
Quoting Tero Kristo (2014-09-26 00:18:55)
On 09/26/2014 04:35 AM, Stephen Boyd wrote:
On 09/23/14 06:38, Tero Kristo wrote:
On 09/22/2014 10:18 PM, Stephen Boyd wrote:
On 08/21, Tero Kristo wrote:
/* Skip children who will be
On 09/26/2014 04:35 AM, Stephen Boyd wrote:
On 09/23/14 06:38, Tero Kristo wrote:
On 09/22/2014 10:18 PM, Stephen Boyd wrote:
On 08/21, Tero Kristo wrote:
/* Skip children who will be reparented to another clock */
if (child->new_parent && child->new
On 09/22/2014 10:18 PM, Stephen Boyd wrote:
On 08/21, Tero Kristo wrote:
In some cases, clocks can switch their parent with clk_set_rate, for
example clk_mux can do this in some cases. Current implementation of
clk_change_rate uses un-safe list iteration on the clock children, which
will cause
: Tero Kristo
To: Mike Turquette
Reported-by: Nishanth Menon
---
drivers/clk/clk.c |7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index b76fa69..bacc06f 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1467,6 +1467,7
On 08/18/2014 07:56 PM, Nishanth Menon wrote:
Hi,
The following patches are based on v3.17-rc1
Prior to this series: http://slexy.org/view/s20QH6PW4x (notice the /0 div error
spam at initial boot log)
After this series: http://slexy.org/view/s20tPNXPf4
Yeah, valid findings. However, you did no
On 07/31/2014 04:49 PM, Felipe Balbi wrote:
Hi,
On Thu, Jul 31, 2014 at 10:57:09AM +0300, Tero Kristo wrote:
On 07/31/2014 09:28 AM, Tony Lindgren wrote:
* Felipe Balbi [140730 09:23]:
Hi,
On Wed, Jul 30, 2014 at 10:45:41AM -0500, Nishanth Menon wrote:
On Wed, Jul 30, 2014 at 9:40 AM
On 07/31/2014 09:28 AM, Tony Lindgren wrote:
* Felipe Balbi [140730 09:23]:
Hi,
On Wed, Jul 30, 2014 at 10:45:41AM -0500, Nishanth Menon wrote:
On Wed, Jul 30, 2014 at 9:40 AM, Felipe Balbi wrote:
HI,
On Tue, Jul 29, 2014 at 11:04:21PM -0700, Tony Lindgren wrote:
* Felipe Balbi [140729 0
On 07/31/2014 01:42 AM, Mike Turquette wrote:
Quoting Tero Kristo (2014-07-30 05:27:07)
On 07/30/2014 08:53 AM, Peter Ujfalusi wrote:
On 07/29/2014 07:12 PM, Mike Turquette wrote:
Oh yea, seems this got lost into the myriad of branches I have. I can push
this on top of my for-v3.17/ti-clk-drv
On 07/30/2014 08:53 AM, Peter Ujfalusi wrote:
On 07/29/2014 07:12 PM, Mike Turquette wrote:
Oh yea, seems this got lost into the myriad of branches I have. I can push
this on top of my for-v3.17/ti-clk-drv if you like.
That is the easiest thing for me. I think that Peter wanted to take
this as
On 07/29/2014 09:27 AM, Mike Turquette wrote:
Quoting Peter Ujfalusi (2014-07-14 03:10:28)
On 05/06/2014 04:39 PM, Peter Ujfalusi wrote:
Tero: can I have your ack for this patch or do you have further concerns?
Yea looks good to me, except for the fact that there is some work on getting
defau
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