On 01-12-20, 18:09, Marek Szyprowski wrote:
> Exynos5420 variant of USB2 PHY is handled by the same code as the
> Exynos5250 one. Introducing a separate Kconfig symbol for it was an
> over-engineering, which turned out to cause build break for certain
> configurations:
>
> ERROR: modpost: "exynos5
On 01-12-20, 12:20, Sergio Paracuellos wrote:
> Hi Vinod,
>
> After merging the phy-next tree, today's linux-next build (x86_64
> allmodconfig) failed like this:
>
> drivers/phy/ralink/phy-mt7621-pci.c:17:10: fatal error: mt7621.h: No such
> file or directory
> 17 | #include
> | ^
On 01-12-20, 11:47, Sergio Paracuellos wrote:
> Hi Vinod,
>
> On Tue, Dec 1, 2020 at 11:42 AM Vinod Koul wrote:
> >
> > On 01-12-20, 11:16, Sergio Paracuellos wrote:
> > > This driver includes the following two files directly:
> > > - mt7621.h
> >
On 01-12-20, 11:16, Sergio Paracuellos wrote:
> This driver includes the following two files directly:
> - mt7621.h
> - ralink_regs.h
>
> Compilation for its related platform properly works because
> its real path is included in 'arch/mips/ralink/Platform' as
> cflags.
>
> This driver depends on
On 01-12-20, 07:45, Sergio Paracuellos wrote:
> Hi Stephen,
>
> On Tue, Dec 1, 2020 at 7:07 AM Stephen Rothwell wrote:
> >
> > Hi all,
> >
> > After merging the phy-next tree, today's linux-next build (x86_64
> > allmodconfig) failed like this:
> >
> > drivers/phy/ralink/phy-mt7621-pci.c:17:10: f
Add the compatible string for SM8250 SoC from Qualcomm. This compatible
is used already in DTS files but not documented yet
Signed-off-by: Vinod Koul
---
.../devicetree/bindings/interrupt-controller/qcom,pdc.txt| 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation
gpi_dma0 can be used for spi and i2c transfers on db845c, so enable it
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
index
This add the device node for gpi_dma0 and gpi_dma1 instances found in
sdm845.
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 50
1 file changed, 50 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom
On 01-12-20, 02:42, Liao, Bard wrote:
> Hi Vinod/Mark,
>
> Could we take this series into Vinod's tree with Mark's Acked-by?
> It failed to build on Mark's tree.
I see Mark has already applied 1-3 ..
Thanks
--
~Vinod
On 30-11-20, 21:20, Bjorn Andersson wrote:
> On Mon 30 Nov 00:39 CST 2020, Vinod Koul wrote:
>
> > This add the device node for gpi_dma0 and gpi_dma1 instances found in
> > sdm845.
> >
> > Signed-off-by: Vinod Koul
> > ---
> >
On 16-11-20, 08:46, Rafał Miłecki wrote:
> From: Rafał Miłecki
>
> 1. Change syntax from txt to yaml
> 2. Drop "Driver for" from the title
> 3. Drop "reg = <0x0>;" from example (noticed by dt_binding_check)
> 4. Specify license
>
> Signed-off-by: Rafał Miłecki
> ---
> I think this should go thr
On 25-11-20, 15:37, Tiezhu Yang wrote:
> devm_ioremap_resource() will be not built in lib/devres.c if
> CONFIG_HAS_IOMEM is not set, of_address_to_resource() will be
> not built in drivers/of/address.c if CONFIG_OF_ADDRESS is not
> set, and then there exists two build errors about undefined
> refer
On 17-11-20, 16:38, JC Kuo wrote:
> In commit "phy: tegra: xusb: Add usb-phy support", an OTG capable PHY
> device, such as phy-usb2.0 device of Jetson-TX1 platform, will be
> bound to the tegra-xusb-padctl driver by the following line in
> tegra_xusb_setup_usb_role_switch().
>
> port->usb_p
Hi Florian,
On 21-11-20, 19:29, Florian Fainelli wrote:
> Update the Broadcom SATA PHY Device Tree binding to a YAML format.
>
> Suggested-by: Vinod Koul
> Signed-off-by: Florian Fainelli
I am getting these warns:
Documentation/devicetree/bindings/phy/brcm,sata-phy.yaml:19
On 18-11-20, 10:36, Yejune Deng wrote:
> devm_reset_control_array_get_exclusive() looks more readable
Applied, thanks
--
~Vinod
On 20-11-20, 16:38, Neil Armstrong wrote:
> In order to keep OTG ID detection even when in Host mode, the ID line of
> the PHY (if the current phy is an OTG one) pull-up should be kept
> enable in both modes.
>
> This fixes OTG switch on GXL, GXM & AXG platforms, otherwise once switched
> to Host,
On 20-11-20, 16:03, Neil Armstrong wrote:
> For consistency, replace DSI_LANE definitions with BIT() macro and remove the
> unused
> DSI_LANE_MASK definition.
Applied, thanks
--
~Vinod
On 20-11-20, 09:56, Marek Szyprowski wrote:
> Exynos5420 differs a bit from Exynos5250 in USB2 PHY related registers in
> the PMU region. Add a variant for the Exynos5420 case. Till now, USB2 PHY
> worked only because the bootloader enabled the PHY, but then driver messed
> USB 3.0 DRD related regi
On 21-11-20, 16:50, Sergio Paracuellos wrote:
> This series adds support for the PCIe PHY found in the Mediatek
> MT7621 SoC.
>
> There is also a 'mt7621-pci' driver which is the controller part
> which is still in staging and is a client of this phy.
>
> Both drivers have been tested together in
On 17-11-20, 07:14, Chun-Kuang Hu wrote:
> mtk_mipi_dsi_phy is currently placed inside mediatek drm driver, but it's
> more suitable to place a phy driver into phy driver folder, so move
> mtk_mipi_dsi_phy driver into phy driver folder.
Acked-By: Vinod Koul
I am thinking this wou
On 16-11-20, 13:59, Mauro Carvalho Chehab wrote:
> +#define CTRL7_USB2_REFCLKSEL_MASK(3 << 3)
> +#define CTRL7_USB2_REFCLKSEL_ABB (3 << 3)
> +#define CTRL7_USB2_REFCLKSEL_PAD (2 << 3)
This should use GENMASK()
> +
> +#define CFG50_USB3_PHY_TEST_POWERDOWNBIT(23)
> +
> +#define
On 16-11-20, 20:08, Wan Ahmad Zainie wrote:
> Hi.
>
> Intel Keem Bay USB subsystem incorporates DesignWare USB3.1 controller,
> an USB3.1 (Gen1/2) PHY and an USB2.0 PHY. It is a Dual Role Device
> (DRD), operating as either a USB host or a USB device.
Applied all, thanks
--
~Vinod
This add the device node for gpi_dma0 and gpi_dma1 instances found in
sdm845.
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 45
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom
On 26-11-20, 09:52, Vinod Koul wrote:
> > > > @@ -154,7 +163,12 @@ int sdw_master_device_add(struct sdw_bus *bus,
> > > struct device *parent,
> > > > bus->dev = &md->dev;
> > > > bus->md = md;
> > &g
Add support from RPMH regulators found in SDX55 platform
Signed-off-by: Vinod Koul
---
drivers/regulator/qcom-rpmh-regulator.c | 31 +
1 file changed, 31 insertions(+)
diff --git a/drivers/regulator/qcom-rpmh-regulator.c
b/drivers/regulator/qcom-rpmh-regulator.c
index
Add PMX55 compatibles for PMIC found in SDX55 platform
Signed-off-by: Vinod Koul
---
.../devicetree/bindings/regulator/qcom,rpmh-regulator.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.txt
b/Documentation
This adds the power domains found in SDX55 SoC. Downstream code tells me
that we have 3 power domains so add them
Signed-off-by: Vinod Koul
---
drivers/soc/qcom/rpmhpd.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c
Add RPM power domain bindings for the SDX55 SoC
Signed-off-by: Vinod Koul
---
Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 +
include/dt-bindings/power/qcom-rpmpd.h | 5 +
2 files changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/power
PM55 pmic support gpio controller so add compatible and comment for gpio
holes
Signed-off-by: Vinod Koul
---
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
index
Add support for the PMX55 GPIO support to the Qualcomm PMIC GPIO
binding.
Signed-off-by: Vinod Koul
---
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt
b
On 25-11-20, 18:39, Reddy, MallikarjunaX wrote:
> > > > > desc needs to be configure for each dma channel and the remapped
> > > > > address of
> > > > > the IGP & EGP is desc base adress.
> > > > Why should this address not passed as src_addr/dst_addr?
> > > src_addr/dst_addr is the data pointer
On 25-11-20, 09:31, Randy Dunlap wrote:
> On 11/24/20 9:51 PM, Vinod Koul wrote:
> > From: Vinod Koul
> > Date: Wed, 25 Nov 2020 11:15:22 +0530
> > Subject: [PATCH] soundwire: qcom: Fix build failure when slimbus is module
> >
> > Commit 5bd773242f75 (&quo
On 26-11-20, 03:11, Liao, Bard wrote:
> > -Original Message-
> > From: Vinod Koul
> > Sent: Wednesday, November 25, 2020 1:05 PM
> > To: Bard Liao
> > Cc: alsa-de...@alsa-project.org; linux-kernel@vger.kernel.org;
> > gre...@linuxfoundation.org; j.
ode. Per the
Documentation if we are using imply we should use IS_REACHABLE() rather
than IS_ENABLED.
This seems to take care of build failure for me on arm64 and x64 builds.
Can you confirm with below patch:
---><8---
From: Vinod Koul
Date: Wed, 25 Nov 2020 11:15:22 +0530
Subject: [PATCH]
On 24-11-20, 21:07, Bard Liao wrote:
> From: Pierre-Louis Bossart
>
> The 'master' device acts as a glue layer used during bus
> initialization only, and it needs to be 'transparent' for pm_runtime
> management. Its behavior should be that it becomes active when one of
> its children becomes acti
On 24-11-20, 09:33, Bard Liao wrote:
> We wrote 1 to the handled interrupts bits along with 0 to all other bits
> to the SoundWire DPx interrupt register. However, DP0 has reserved fields
> and the read-only SDCA_CASCADE bit. DPN also has reserved fields. We should
> not try to write values in thes
On 24-11-20, 20:38, Bjorn Andersson wrote:
> The PON block in the PMIC provides, among other things, support for
> "reboot reason", power key and reset "key" handling. Let's enable the
> driver for this block.
Reviewed-by: Vinod Koul
--
~Vinod
On 20-11-20, 17:22, Krzysztof Kozlowski wrote:
> The driver can match only via the DT table so the table should be always
> used and the of_match_ptr does not have any sense (this also allows ACPI
> matching via PRP0001, even though it is not relevant here). This fixes
> compile warning (!CONFIG_O
On 24-11-20, 09:08, Zhihao Cheng wrote:
> Return the corresponding error code when first_msi_entry() returns
> NULL in mv_xor_v2_probe().
Applied, thanks
--
~Vinod
On 24-11-20, 00:30, Reddy, MallikarjunaX wrote:
> Hi Vinod,
>
> Thanks for your valuable review. My comments inline.
>
> On 11/21/2020 8:19 PM, Vinod Koul wrote:
> > On 20-11-20, 19:30, Reddy, MallikarjunaX wrote:
> > > Hi Vinod,
> > > Thanks for the revi
On 24-11-20, 00:29, Reddy, MallikarjunaX wrote:
> Hi Vinod,
>
> Thanks for your valuable review comments. Please see my comments inline.
>
> On 11/21/2020 8:17 PM, Vinod Koul wrote:
> > On 20-11-20, 19:30, Reddy, MallikarjunaX wrote:
> > > Hi Vinod,
> >
Hello Vitaly,
On 24-11-20, 09:23, Vitaly Mayatskih wrote:
> On Wed, Nov 18, 2020 at 7:20 AM Vinod Koul wrote:
>
> > this should be single line
>
> Vinod, do you see any obvious functional defects still present in the
> driver, or can it be finally merged for us to start te
On 15-11-20, 18:12, Jonathan McDowell wrote:
> Converts the device tree bindings for the Qualcomm Application Data
> Mover (ADM) DMA controller over to YAML schemas.
Rob ?
>
> Signed-off-by: Jonathan McDowell
> ---
> .../devicetree/bindings/dma/qcom,adm.yaml | 102 ++
> ...
On 17-11-20, 12:56, Peter Ujfalusi wrote:
> Hi,
>
> The series have build dependency on ti_sci/soc series (v2):
> https://lore.kernel.org/lkml/20201008115224.1591-1-peter.ujfal...@ti.com/
>
> Santosh kindly created immutable branch holdinf the series:
> git://git.kernel.org/pub/scm/linux/kernel/g
On 24-11-20, 10:39, Bjorn Andersson wrote:
> On Tue 24 Nov 09:34 CST 2020, Vinod Koul wrote:
>
> > On 22-11-20, 23:21, Bjorn Andersson wrote:
> > > Every now and then it's convenient to be able to inspect the content of
> > > SMEM items. Rather than carrying
On 22-11-20, 23:21, Bjorn Andersson wrote:
> Every now and then it's convenient to be able to inspect the content of
> SMEM items. Rather than carrying some hack locally let's upstream a
> driver that when inserted exposes a debugfs interface for dumping
> available items.
>
> Signed-off-by: Bjorn
On 20-11-20, 21:58, Bjorn Andersson wrote:
> From: Jonathan Marek
>
> Enable the WiFi node and specify its supply regulators.
Reviewed-by: Vinod Koul
--
~Vinod
On 20-11-20, 21:58, Bjorn Andersson wrote:
> From: Jonathan Marek
>
> Add a node for the WCN3990 WiFi module.
Reviewed-by: Vinod Koul
--
~Vinod
On 20-11-20, 21:56, Bjorn Andersson wrote:
> Point the various remoteprocs of SM8150 MTP to a place with the platform
> specific firmware.
Reviewed-by: Vinod Koul
--
~Vinod
On 04-11-20, 23:23, Bard Liao wrote:
> From: Pierre-Louis Bossart
>
> The SoundWire 1.2 specification defines an "SDCA cascade" bit which
> handles a logical OR of all SDCA interrupt sources (up to 30 defined).
>
> Due to limitations of the addressing space, this bit is located in the
> SDW_DP0_
On 04-11-20, 11:29, Srinivas Kandagatla wrote:
> running kernel with CONFIG_DEBUG_LOCKS_ALLOC enabled will below warning:
>
> BUG: key 502e09807098 has not been registered!
> DEBUG_LOCKS_WARN_ON(1)
> WARNING: CPU: 5 PID: 129 at kernel/locking/lockdep.c:4623
> lockdep_init_map_waits+0xe8/
that CONFIG_REGMAP would not
> be selected with CONFIG_REGMAP_MBQ selected. However there's no
> functional dependency between the two modules so they can be selected
> separately.
Reviewed-by: Vinod Koul
--
~Vinod
(((ctl) & 0x30) << 15) |
> \
> + (((ctl) & 0x0f) << 3) |
> \
> + (((ch) & 0x38) << 12) |
> \
> + ((ch) & 0x07))
> +
> +#define SDW_SDCA_MBQ_CTL(reg)((reg) | BIT(13))
> +#define SDW_SDCA_NEXT_CTL(reg) ((reg) | BIT(14))
Ideally would have liked to use defines with GENMASK etc instead of
numbers, but this is not a strong issue so:
Acked-By: Vinod Koul
--
~Vinod
Hello Chen-Yu,
On 24-11-20, 13:36, Chen-Yu Tsai wrote:
> Hi,
>
> On Tue, Nov 24, 2020 at 1:28 PM Vinod Koul wrote:
> >
> > Hello Olof, Rob,
> >
> > We have Qualcomm arm platform which uses PMIC PM8150B. This PMIC was
> > also used in SM8150 board a
Hello Olof, Rob,
We have Qualcomm arm platform which uses PMIC PM8150B. This PMIC was
also used in SM8150 board and is already upstream [1] but in arm64.
So, what is the guidance to share DTS files between 32 and 64 variants?
Does a solution already exist which I may not be aware of..?
I can thi
the right SID and mask so this works.
Reviewed-by: Vinod Koul
on DB845c with GSI DMA:
Tested-by: Vinod Koul
--
~Vinod
On 23-11-20, 11:46, Robert Foss wrote:
> 4k requires two dsi pipes, so don't report MODE_OK when only a
> single pipe is configured. But rather report MODE_PANEL to
> signal that requirements of the panel are not being met.
Acked-By: Vinod Koul
> Reported-by: Peter Collingbourn
On 20-11-20, 19:30, Reddy, MallikarjunaX wrote:
> Hi Vinod,
> Thanks for the review. My comments inline.
>
> On 11/18/2020 11:55 PM, Vinod Koul wrote:
> > On 12-11-20, 13:38, Amireddy Mallikarjuna reddy wrote:
> > > Add DT bindings YAML schema for DMA controller driver
On 20-11-20, 19:30, Reddy, MallikarjunaX wrote:
> Hi Vinod,
>
> Thanks for the review. My comments inline.
>
> On 11/19/2020 1:38 AM, Vinod Koul wrote:
> > On 12-11-20, 13:38, Amireddy Mallikarjuna reddy wrote:
> > > Add DMA controller driver for Lightning
On 20-11-20, 17:20, Sergio Paracuellos wrote:
> Hi Vinod,
>
> On Thu, Nov 19, 2020 at 4:43 PM Sergio Paracuellos
> wrote:
> >
> > This series adds support for the PCIe PHY found in the Mediatek
> > MT7621 SoC.
> >
> > There is also a 'mt7621-pci' driver which is the controller part
> > which is s
Hello Linus
Please consider pull to receive the dmaengine subsystem fixes for
v5.10-rc5
The includes a solitary core fixes and few driver fixes. All the patches
are in linux-next
The following changes since commit 3650b228f83adda7e5ee532e2b90429c03f7b9ec:
Linux 5.10-rc1 (2020-10-25 15:14:11 -
Hello Greg
Please consider PULL to recive fixes for 5.10 for Generic phy.
All minor fixes to drivers, already in linux-next
The following changes since commit 3650b228f83adda7e5ee532e2b90429c03f7b9ec:
Linux 5.10-rc1 (2020-10-25 15:14:11 -0700)
are available in the Git repository at:
git://
anks
My scripts found a typo, have applied fix for that as well
From: Vinod Koul
Date: Fri, 20 Nov 2020 16:04:01 +0530
Subject: [PATCH] phy: samsung: phy-exynos-pcie: fix typo 'tunning'
Fix the typo s/tunning/tuning
Fixes: 496db029142f ("phy: samsung: phy-exynos-pcie: rewor
On 20-11-20, 10:58, Marek Szyprowski wrote:
> Hi Vinod,
>
> On 20.11.2020 10:41, Vinod Koul wrote:
> > On 13-11-20, 18:01, Marek Szyprowski wrote:
> >> From: Jaehoon Chung
> >>
> >> Exynos5440 SoC support has been dropped since commit 8c83315da1cf
On 09-11-20, 20:12, Frank Lee wrote:
> From: Yangtao Li
>
> The debounce and poll time is generally quite long and the work not
> performance critical so allow the scheduler to run the work anywhere
> rather than in the normal per-CPU workqueue.
Applied, thanks
--
~Vinod
On 16-11-20, 18:19, Amelie Delaunay wrote:
> Convert the STM32 USB PHY Controller (USBPHYC) bindings to DT schema format
> using json-schema.
Applied, thanks
--
~Vinod
On 16-11-20, 11:16, Neil Armstrong wrote:
> The AXG Analog MIPI-DSI PHY also provides functions to the PCIe PHY,
> thus we need to have inclusive support for both interfaces at runtime.
>
> This fixes the regmap get from parent node, removes cell param
> to select a mode and implement runtime conf
On 16-11-20, 11:13, Neil Armstrong wrote:
> The Amlogic AXg SoCs embeds a MIPI D-PHY to communicate with DSI
> panels, this adds the bindings.
>
> This D-PHY depends on a separate analog PHY.
Applied, thanks
--
~Vinod
On 16-11-20, 11:16, Neil Armstrong wrote:
> The AXG Analog MIPI-DSI PHY also provides functions to the PCIe PHY,
> thus we need to have inclusive support for both interfaces at runtime.
>
> This fixes the regmap get from parent node, removes cell param
> to select a mode and implement runtime conf
ng this series to go thru PCI tree, so:
Acked-By: Vinod Koul
--
~Vinod
system locking up as soon as any form of data
> transfer is attempted from any of the affected peripherals.
>
> Mark QCOM_SCM as builtin, to avoid this.
Reviewed-by: Vinod Koul
--
~Vinod
On 16-11-20, 08:46, Rafał Miłecki wrote:
> From: Rafał Miłecki
>
> 1. Change syntax from txt to yaml
> 2. Drop "Driver for" from the title
> 3. Drop "reg = <0x0>;" from example (noticed by dt_binding_check)
> 4. Specify license
You missed Ccing Rob
>
> Signed-off-by: Rafał Miłecki
> ---
> I t
On 13-11-20, 12:34, Rafał Miłecki wrote:
> From: Rafał Miłecki
>
> Initially this PHY driver was implementing MDIO access on its own. It
> was caused by lack of proper hardware design understanding.
>
> It has been changed back in 2017. DT bindings were changed and driver
> was updated to use MD
On 10-11-20, 14:35, Frank Lee wrote:
> From: Yangtao Li
>
> Use the devm_platform_ioremap_resource_byname() and
> devm_platform_ioremap_resource helper to simplify the code.
This fails to apply for me, pls rebase
--
~Vinod
On 10-11-20, 14:32, Frank Lee wrote:
> From: Yangtao Li
>
> For the current code, enable_pmu_unk1 only works in non-a83t and non-h6
> types. So let's delete it from the sun50i_h6_cfg.
Applied, thanks
--
~Vinod
On 10-11-20, 15:49, Steen Hegelund wrote:
> Provide a new ethernet phy configuration structure, that
> allow PHYs used for ethernet to be configured with
> speed, media type and clock information.
>
> Signed-off-by: Lars Povlsen
> Signed-off-by: Steen Hegelund
> ---
> include/linux/phy/phy-ethe
On 10-11-20, 15:49, Steen Hegelund wrote:
> Document the Sparx5 ethernet serdes phy driver bindings.
Rob ..?
Also pls cc devicet...@vger.kernel.org
>
> Signed-off-by: Lars Povlsen
> Signed-off-by: Steen Hegelund
> ---
> .../bindings/phy/microchip,sparx5-serdes.yaml | 283 ++
>
On 12-11-20, 13:38, Amireddy Mallikarjuna reddy wrote:
> Add DMA controller driver for Lightning Mountain (LGM) family of SoCs.
>
> The main function of the DMA controller is the transfer of data from/to any
> peripheral to/from the memory. A memory to memory copy capability can also
> be configur
On 12-11-20, 13:38, Amireddy Mallikarjuna reddy wrote:
> Add DT bindings YAML schema for DMA controller driver
> of Lightning Mountain (LGM) SoC.
>
> Signed-off-by: Amireddy Mallikarjuna reddy
>
> ---
> v1:
> - Initial version.
>
> v2:
> - Fix bot errors.
>
> v3:
> - No change.
>
> v4:
> - Ad
On 14-11-20, 14:02, Jonathan McDowell wrote:
> Add the DMA engine driver for the QCOM Application Data Mover (ADM) DMA
> controller found in the MSM8x60 and IPQ/APQ8064 platforms.
>
> The ADM supports both memory to memory transactions and memory
> to/from peripheral device transactions. The cont
On 16-10-20, 02:39, Sanjay R Mehta wrote:
> diff --git a/drivers/dma/ptdma/ptdma-dmaengine.c
> b/drivers/dma/ptdma/ptdma-dmaengine.c
> new file mode 100644
> index 000..9b9b77c
> --- /dev/null
> +++ b/drivers/dma/ptdma/ptdma-dmaengine.c
> @@ -0,0 +1,554 @@
> +// SPDX-License-Identifier: GPL-2
On 16-10-20, 02:39, Sanjay R Mehta wrote:
> From: Sanjay R Mehta
>
> Adding support for AMD PTDMA controller. It performs high-bandwidth
Add support or Adds support.. would be apt!
> memory to memory and IO copy operation. Device commands are managed
> via a circular queue of 'descriptors', eac
On 10-11-20, 14:26, Frank Lee wrote:
> From: Yangtao Li
>
> Add a binding for A100's dma controller.
Applied, thanks
--
~Vinod
On 10-11-20, 14:28, Frank Lee wrote:
> From: Yangtao Li
>
> The dma of a100 is similar to h6, with some minor changes to
> support greater addressing capabilities.
>
> Add support for it.
Applied, thanks
--
~Vinod
On 07-11-20, 20:20, 周琰杰 (Zhou Yanjie) wrote:
> Add the dmaengine bindings for the JZ4775 SoC and the X2000 SoC from Ingenic.
>
> 周琰杰 (Zhou Yanjie) (2):
> dt-bindings: dmaengine: Add JZ4775 bindings.
> dt-bindings: dmaengine: Add X2000 bindings.
Applied, thanks
--
~Vinod
On 10-11-20, 08:54, Paul Cercueil wrote:
> Hi Zhou,
>
> Le sam. 7 nov. 2020 à 20:20, 周琰杰 (Zhou Yanjie)
> a écrit :
> > Add the dmaengine bindings for the JZ4775 SoC and the X2000 SoC from
> > Ingenic.
> >
> > 周琰杰 (Zhou Yanjie) (2):
> > dt-bindings: dmaengine: Add JZ4775 bindings.
> > dt-bind
On 18-11-20, 13:56, Stephen Rothwell wrote:
> Hi Vinod,
>
> On Tue, 17 Nov 2020 15:30:56 +0530 Vinod Koul wrote:
> >
> > On 17-11-20, 13:40, Stephen Rothwell wrote:
> > > Hi all,
> > >
> > > After merging the phy-next tree, today's linux-
Hello Stephen,
On 17-11-20, 13:40, Stephen Rothwell wrote:
> Hi all,
>
> After merging the phy-next tree, today's linux-next build (arm
> multi_v7_defconfig) failed like this:
>
> drivers/soc/amlogic/meson-ee-pwrc.c: In function 'meson_ee_pwrc_init_domain':
> drivers/soc/amlogic/meson-ee-pwrc.c:
On 17-11-20, 07:55, Mauro Carvalho Chehab wrote:
> Em Mon, 16 Nov 2020 09:31:06 -0600
> Rob Herring escreveu:
>
> > On Mon, Nov 16, 2020 at 01:59:27PM +0100, Mauro Carvalho Chehab wrote:
> > > The phy USB3 driver for Hisilicon 970 (hi3670) is ready
> > > for mainstream. Mode it from staging into
On 14-11-20, 11:55, Sugar Zhang wrote:
> Actually, burst size is equal to '1 << desc->rqcfg.brst_size'.
> we should use burst size, not desc->rqcfg.brst_size.
>
> dma memcpy performance on Rockchip RV1126
> @ 1512MHz A7, 1056MHz LPDDR3, 200MHz DMA:
>
> dmatest:
>
> /# echo dma0chan0 > /sys/modul
On 13-11-20, 09:12, Lukas Bulwahn wrote:
> Commit 7f832645d0e5 ("dmaengine: ioatdma: remove ioatdma v2 registration")
> missed to remove dca2_tag_map_valid() during its removal. Hence, since
> then, dca2_tag_map_valid() is unused and make CC=clang W=1 warns:
>
> drivers/dma/ioat/dca.c:44:19:
>
On 17-11-20, 00:17, Chun-Kuang Hu wrote:
> Hi, Vinod:
>
> Vinod Koul 於 2020年11月16日 週一 下午3:25寫道：
> >
> > On 02-11-20, 07:08, Chun-Kuang Hu wrote:
> > > + Vinod:
> > >
> > > Hi, Chunfeng:
> > >
> > > Chunfeng Yun 於 2020年10月30日 週五
On 16-11-20, 09:02, Amelie DELAUNAY wrote:
> Hi Vinod,
>
> On 11/16/20 8:37 AM, Vinod Koul wrote:
> > On 10-11-20, 11:23, Amelie Delaunay wrote:
> > > Change stm32-usbphyc driver to not print an error message when the device
> > > probe operation is defer
On 16-11-20, 09:47, Neil Armstrong wrote:
> Hi Vinod, Kishon,
>
>
> On 04/11/2020 14:47, Neil Armstrong wrote:
> > The Amlogic AXg SoCs embeds a MIPI D-PHY to communicate with DSI
> > panels, this adds the bindings.
> >
> > This D-PHY depends on a separate analog PHY.
Am not sure why but these
On 16-11-20, 17:11, xiakaixu1...@gmail.com wrote:
> From: Kaixu Xia
>
> The value of variable error is overwritten by the following call
> devm_request_threaded_irq() in phy_mdm6600_device_power_on(), actually
> we should return error when timed out powering up.
>
> Reported-by: Tosk Robot
> Si
On 13-11-20, 15:12, Bryan O'Donoghue wrote:
> kernel build robot fired this email at me about an hour ago
> https://lkml.org/lkml/2020/11/13/414
>
> The build robot has flagged the super-speed PHY driver but both Kconfig
> entries have the same error. Fix those now.
>
> verified with "make menuco
On 14-11-20, 12:05, Colin King wrote:
> From: Colin Ian King
>
> There is a spelling mistake in the Kconfig. Fix it.
Applied, thanks
--
~Vinod
On 13-11-20, 16:34, xiakaixu1...@gmail.com wrote:
> From: Kaixu Xia
>
> The value of variable error is overwritten by the following call
> devm_request_threaded_irq() in phy_mdm6600_device_power_on(), so here the
> value assignment is useless. Remove it.
>
> Reported-by: Tosk Robot
> Signed-off
On 11-11-20, 10:37, Jon Hunter wrote:
> Deferred probe is an expected return value for devm_regulator_bulk_get().
> Given that the driver deals with it properly, there's no need to output a
> warning that may potentially confuse users.
Applied, thanks
--
~Vinod
On 22-10-20, 13:50, Florian Fainelli wrote:
> Hi Vinod, Kishon,
>
> This patch series allows the configuration of the Broadcom SATA PHY TX
> amplitude which may be required in order to meet specific tests.
Applied, thanks
Btw please do convert the binding doc to yaml
Thanks
--
~Vinod
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