Re: [PATCH] ARM: decompressor: remove unused cache flush code

2015-01-22 Thread Russell King - ARM Linux
On Thu, Jan 22, 2015 at 09:06:47AM +0100, Uwe Kleine-König wrote: > Hello, > > On Thu, Jan 22, 2015 at 02:22:58PM +0900, Masahiro Yamada wrote: > > As ARM ARM says, the bit 19-16 of ID_MMFR1 is always 0b because > > ARMv7 requires a hierarchical cache implementation. > > The line "mcrp15,

Re: [PATCH] ARM: decompressor: remove unused cache flush code

2015-01-22 Thread Uwe Kleine-König
Hello, On Thu, Jan 22, 2015 at 02:22:58PM +0900, Masahiro Yamada wrote: > As ARM ARM says, the bit 19-16 of ID_MMFR1 is always 0b because > ARMv7 requires a hierarchical cache implementation. > The line "mcrp15, 0, r10, c7, c14, 0" is not reachable. > > Moreover, the v7_flush_dcache_all

Re: [PATCH] ARM: decompressor: remove unused cache flush code

2015-01-22 Thread Uwe Kleine-König
Hello, On Thu, Jan 22, 2015 at 02:22:58PM +0900, Masahiro Yamada wrote: As ARM ARM says, the bit 19-16 of ID_MMFR1 is always 0b because ARMv7 requires a hierarchical cache implementation. The line mcrp15, 0, r10, c7, c14, 0 is not reachable. Moreover, the v7_flush_dcache_all in

Re: [PATCH] ARM: decompressor: remove unused cache flush code

2015-01-22 Thread Russell King - ARM Linux
On Thu, Jan 22, 2015 at 09:06:47AM +0100, Uwe Kleine-König wrote: Hello, On Thu, Jan 22, 2015 at 02:22:58PM +0900, Masahiro Yamada wrote: As ARM ARM says, the bit 19-16 of ID_MMFR1 is always 0b because ARMv7 requires a hierarchical cache implementation. The line mcrp15, 0, r10,

[PATCH] ARM: decompressor: remove unused cache flush code

2015-01-21 Thread Masahiro Yamada
As ARM ARM says, the bit 19-16 of ID_MMFR1 is always 0b because ARMv7 requires a hierarchical cache implementation. The line "mcrp15, 0, r10, c7, c14, 0" is not reachable. Moreover, the v7_flush_dcache_all in arch/arm/mm/cache-v7.S does not check the ID_MMFR1. Signed-off-by: Masahiro

[PATCH] ARM: decompressor: remove unused cache flush code

2015-01-21 Thread Masahiro Yamada
As ARM ARM says, the bit 19-16 of ID_MMFR1 is always 0b because ARMv7 requires a hierarchical cache implementation. The line mcrp15, 0, r10, c7, c14, 0 is not reachable. Moreover, the v7_flush_dcache_all in arch/arm/mm/cache-v7.S does not check the ID_MMFR1. Signed-off-by: Masahiro