On Thu, Jan 22, 2015 at 09:06:47AM +0100, Uwe Kleine-König wrote:
> Hello,
>
> On Thu, Jan 22, 2015 at 02:22:58PM +0900, Masahiro Yamada wrote:
> > As ARM ARM says, the bit 19-16 of ID_MMFR1 is always 0b because
> > ARMv7 requires a hierarchical cache implementation.
> > The line "mcrp15,
Hello,
On Thu, Jan 22, 2015 at 02:22:58PM +0900, Masahiro Yamada wrote:
> As ARM ARM says, the bit 19-16 of ID_MMFR1 is always 0b because
> ARMv7 requires a hierarchical cache implementation.
> The line "mcrp15, 0, r10, c7, c14, 0" is not reachable.
>
> Moreover, the v7_flush_dcache_all
Hello,
On Thu, Jan 22, 2015 at 02:22:58PM +0900, Masahiro Yamada wrote:
As ARM ARM says, the bit 19-16 of ID_MMFR1 is always 0b because
ARMv7 requires a hierarchical cache implementation.
The line mcrp15, 0, r10, c7, c14, 0 is not reachable.
Moreover, the v7_flush_dcache_all in
On Thu, Jan 22, 2015 at 09:06:47AM +0100, Uwe Kleine-König wrote:
Hello,
On Thu, Jan 22, 2015 at 02:22:58PM +0900, Masahiro Yamada wrote:
As ARM ARM says, the bit 19-16 of ID_MMFR1 is always 0b because
ARMv7 requires a hierarchical cache implementation.
The line mcrp15, 0, r10,
As ARM ARM says, the bit 19-16 of ID_MMFR1 is always 0b because
ARMv7 requires a hierarchical cache implementation.
The line "mcrp15, 0, r10, c7, c14, 0" is not reachable.
Moreover, the v7_flush_dcache_all in arch/arm/mm/cache-v7.S does not
check the ID_MMFR1.
Signed-off-by: Masahiro
As ARM ARM says, the bit 19-16 of ID_MMFR1 is always 0b because
ARMv7 requires a hierarchical cache implementation.
The line mcrp15, 0, r10, c7, c14, 0 is not reachable.
Moreover, the v7_flush_dcache_all in arch/arm/mm/cache-v7.S does not
check the ID_MMFR1.
Signed-off-by: Masahiro
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