Re: [PATCH] clk: rockchip: Add 1.6GHz PLL rate

Am Dienstag, 13. März 2018, 21:37:19 CET schrieb Derek Basehore: > We need this rate to generate 100, 200, and 228.57MHz from the same > PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for > and external display. > > Signed-off-by: Derek Basehore applied for 4.17 Thanks Heiko

Re: [PATCH] clk: rockchip: Add 1.6GHz PLL rate

Hi, On Tue, Mar 13, 2018 at 1:37 PM, Derek Basehore wrote: > We need this rate to generate 100, 200, and 228.57MHz from the same > PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for > and external display. > > Signed-off-by: Derek Basehore > --- > drivers/clk/rockchip/clk-rk33

[PATCH] clk: rockchip: Add 1.6GHz PLL rate

We need this rate to generate 100, 200, and 228.57MHz from the same PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for and external display. Signed-off-by: Derek Basehore --- drivers/clk/rockchip/clk-rk3399.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockc