On Tue, Oct 18, 2016 at 01:42:09PM +0800, Chen-Yu Tsai wrote:
> On the A31, the DMA engine only works if AHB1 is clocked from PLL6.
> In addition, the hstimer is clocked from AHB1, and if AHB1 is clocked
> from the CPU clock, and cpufreq is working, we get an unstable timer.
>
> Force the AHB1 clo
On Tue, Oct 18, 2016 at 3:50 PM, Jean-Francois Moine wrote:
> On Tue, 18 Oct 2016 13:42:09 +0800
> Chen-Yu Tsai wrote:
>
>> On the A31, the DMA engine only works if AHB1 is clocked from PLL6.
>> In addition, the hstimer is clocked from AHB1, and if AHB1 is clocked
>> from the CPU clock, and cpufr
On Tue, 18 Oct 2016 13:42:09 +0800
Chen-Yu Tsai wrote:
> On the A31, the DMA engine only works if AHB1 is clocked from PLL6.
> In addition, the hstimer is clocked from AHB1, and if AHB1 is clocked
> from the CPU clock, and cpufreq is working, we get an unstable timer.
>
> Force the AHB1 clock to
On the A31, the DMA engine only works if AHB1 is clocked from PLL6.
In addition, the hstimer is clocked from AHB1, and if AHB1 is clocked
from the CPU clock, and cpufreq is working, we get an unstable timer.
Force the AHB1 clock to use PLL6 as its parent. Previously this was done
in the device tre
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