Re: [PATCH] clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parent

2016-10-19 Thread Maxime Ripard
On Tue, Oct 18, 2016 at 01:42:09PM +0800, Chen-Yu Tsai wrote: > On the A31, the DMA engine only works if AHB1 is clocked from PLL6. > In addition, the hstimer is clocked from AHB1, and if AHB1 is clocked > from the CPU clock, and cpufreq is working, we get an unstable timer. > > Force the AHB1 clo

Re: [PATCH] clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parent

2016-10-18 Thread Chen-Yu Tsai
On Tue, Oct 18, 2016 at 3:50 PM, Jean-Francois Moine wrote: > On Tue, 18 Oct 2016 13:42:09 +0800 > Chen-Yu Tsai wrote: > >> On the A31, the DMA engine only works if AHB1 is clocked from PLL6. >> In addition, the hstimer is clocked from AHB1, and if AHB1 is clocked >> from the CPU clock, and cpufr

Re: [PATCH] clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parent

2016-10-18 Thread Jean-Francois Moine
On Tue, 18 Oct 2016 13:42:09 +0800 Chen-Yu Tsai wrote: > On the A31, the DMA engine only works if AHB1 is clocked from PLL6. > In addition, the hstimer is clocked from AHB1, and if AHB1 is clocked > from the CPU clock, and cpufreq is working, we get an unstable timer. > > Force the AHB1 clock to

[PATCH] clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parent

2016-10-17 Thread Chen-Yu Tsai
On the A31, the DMA engine only works if AHB1 is clocked from PLL6. In addition, the hstimer is clocked from AHB1, and if AHB1 is clocked from the CPU clock, and cpufreq is working, we get an unstable timer. Force the AHB1 clock to use PLL6 as its parent. Previously this was done in the device tre