Hi,
On Mon, Aug 01, 2016 at 09:39:34PM +0800, Chen-Yu Tsai wrote:
> Hi,
>
> On Sat, Jul 30, 2016 at 11:20 PM, maxime.rip...@free-electrons.com
> wrote:
> > On Sat, Jul 30, 2016 at 10:52:45PM +0800, Icenowy Zheng wrote:
> >> > + if
Hi,
On Mon, Aug 01, 2016 at 09:39:34PM +0800, Chen-Yu Tsai wrote:
> Hi,
>
> On Sat, Jul 30, 2016 at 11:20 PM, maxime.rip...@free-electrons.com
> wrote:
> > On Sat, Jul 30, 2016 at 10:52:45PM +0800, Icenowy Zheng wrote:
> >> > + if (of_device_is_compatible(pdev->dev.of_node,
> >> > +
Hi,
On Sat, Jul 30, 2016 at 11:20 PM, maxime.rip...@free-electrons.com
wrote:
> On Sat, Jul 30, 2016 at 10:52:45PM +0800, Icenowy Zheng wrote:
>> > + if (of_device_is_compatible(pdev->dev.of_node,
>> > + "allwinner,sun6i-a31-spdif")) {
>> > + host->rst =
Hi,
On Sat, Jul 30, 2016 at 11:20 PM, maxime.rip...@free-electrons.com
wrote:
> On Sat, Jul 30, 2016 at 10:52:45PM +0800, Icenowy Zheng wrote:
>> > + if (of_device_is_compatible(pdev->dev.of_node,
>> > + "allwinner,sun6i-a31-spdif")) {
>> > + host->rst = devm_reset_control_get_optional(>dev,
On Sat, Jul 30, 2016 at 10:52:45PM +0800, Icenowy Zheng wrote:
> > + if (of_device_is_compatible(pdev->dev.of_node,
> > + "allwinner,sun6i-a31-spdif")) {
> > + host->rst = devm_reset_control_get_optional(>dev, NULL);
> > + if (IS_ERR(host->rst) && PTR_ERR(host->rst) == -EPROBE_DEFER) {
> > + ret =
On Sat, Jul 30, 2016 at 10:52:45PM +0800, Icenowy Zheng wrote:
> > + if (of_device_is_compatible(pdev->dev.of_node,
> > + "allwinner,sun6i-a31-spdif")) {
> > + host->rst = devm_reset_control_get_optional(>dev, NULL);
> > + if (IS_ERR(host->rst) && PTR_ERR(host->rst) == -EPROBE_DEFER) {
> > + ret =
On Sun, Jul 31, 2016 at 12:40:48AM +1000, Julian Calaby wrote:
> Hi Marcus,
>
> On Sun, Jul 31, 2016 at 12:27 AM, wrote:
> > From: Marcus Cooper
> >
> > The A31 SoC uses the same SPDIF block as found in earlier SoCs, but its
> > reset is controlled
On Sun, Jul 31, 2016 at 12:40:48AM +1000, Julian Calaby wrote:
> Hi Marcus,
>
> On Sun, Jul 31, 2016 at 12:27 AM, wrote:
> > From: Marcus Cooper
> >
> > The A31 SoC uses the same SPDIF block as found in earlier SoCs, but its
> > reset is controlled via a separate reset controller.
> >
> > The
On Sat, Jul 30, 2016 at 04:27:16PM +0200, codekip...@gmail.com wrote:
> From: Marcus Cooper
>
> The A31 SoC uses the same SPDIF block as found in earlier SoCs, but its
> reset is controlled via a separate reset controller.
>
> The DMA also complains when the maxburst is
On Sat, Jul 30, 2016 at 04:27:16PM +0200, codekip...@gmail.com wrote:
> From: Marcus Cooper
>
> The A31 SoC uses the same SPDIF block as found in earlier SoCs, but its
> reset is controlled via a separate reset controller.
>
> The DMA also complains when the maxburst is set to 4 so it's been
Hi Marcus,
On Sun, Jul 31, 2016 at 12:27 AM, wrote:
> From: Marcus Cooper
>
> The A31 SoC uses the same SPDIF block as found in earlier SoCs, but its
> reset is controlled via a separate reset controller.
>
> The DMA also complains when the maxburst
Hi Marcus,
On Sun, Jul 31, 2016 at 12:27 AM, wrote:
> From: Marcus Cooper
>
> The A31 SoC uses the same SPDIF block as found in earlier SoCs, but its
> reset is controlled via a separate reset controller.
>
> The DMA also complains when the maxburst is set to 4 so it's been adjusted
> to 8
From: Marcus Cooper
The A31 SoC uses the same SPDIF block as found in earlier SoCs, but its
reset is controlled via a separate reset controller.
The DMA also complains when the maxburst is set to 4 so it's been adjusted
to 8 which suites both the older and newer SoCs.
From: Marcus Cooper
The A31 SoC uses the same SPDIF block as found in earlier SoCs, but its
reset is controlled via a separate reset controller.
The DMA also complains when the maxburst is set to 4 so it's been adjusted
to 8 which suites both the older and newer SoCs.
Signed-off-by: Marcus
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