Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

2016-04-22 Thread Marc Zyngier
On 22/04/16 08:53, Minghuan Lian wrote: > Hi Marc, > > Please see the link: > https://patchwork.kernel.org/patch/8649241/ > > Rob Herring has given the ACK. > > I have submitted the v6 patch: https://patchwork.kernel.org/patch/8649251/ > Please apply the latest the patch after you review.

Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

2016-04-22 Thread Marc Zyngier
On 22/04/16 08:53, Minghuan Lian wrote: > Hi Marc, > > Please see the link: > https://patchwork.kernel.org/patch/8649241/ > > Rob Herring has given the ACK. > > I have submitted the v6 patch: https://patchwork.kernel.org/patch/8649251/ > Please apply the latest the patch after you review.

RE: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

2016-04-22 Thread Minghuan Lian
as Gleixner <t...@linutronix.de>; Jason Cooper > <ja...@lakedaemon.net>; Roy Zang <roy.z...@nxp.com>; Mingkai Hu > <mingkai...@nxp.com>; Stuart Yoder <stuart.yo...@nxp.com>; Yang-Leo Li > <leoyang...@nxp.com>; Rob Herring <robh...@kernel.org>; M

RE: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

2016-04-22 Thread Minghuan Lian
o Li > ; Rob Herring ; Mark Rutland > > Subject: Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller > support > > On 22/04/16 06:33, Leo Li wrote: > > On Mon, Mar 7, 2016 at 3:50 AM, Marc Zyngier > wrote: > >> On Mon, 7 Mar 2016 11:36:22 +0800 > &

Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

2016-04-22 Thread Marc Zyngier
On 22/04/16 06:33, Leo Li wrote: > On Mon, Mar 7, 2016 at 3:50 AM, Marc Zyngier wrote: >> On Mon, 7 Mar 2016 11:36:22 +0800 >> Minghuan Lian wrote: >> >>> Some kind of NXP Layerscape SoC provides a MSI >>> implementation which uses two SCFG registers

Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

2016-04-22 Thread Marc Zyngier
On 22/04/16 06:33, Leo Li wrote: > On Mon, Mar 7, 2016 at 3:50 AM, Marc Zyngier wrote: >> On Mon, 7 Mar 2016 11:36:22 +0800 >> Minghuan Lian wrote: >> >>> Some kind of NXP Layerscape SoC provides a MSI >>> implementation which uses two SCFG registers MSIIR and >>> MSIR to support 32 MSI

Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

2016-04-21 Thread Leo Li
On Mon, Mar 7, 2016 at 3:50 AM, Marc Zyngier wrote: > On Mon, 7 Mar 2016 11:36:22 +0800 > Minghuan Lian wrote: > >> Some kind of NXP Layerscape SoC provides a MSI >> implementation which uses two SCFG registers MSIIR and >> MSIR to support 32 MSI

Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

2016-04-21 Thread Leo Li
On Mon, Mar 7, 2016 at 3:50 AM, Marc Zyngier wrote: > On Mon, 7 Mar 2016 11:36:22 +0800 > Minghuan Lian wrote: > >> Some kind of NXP Layerscape SoC provides a MSI >> implementation which uses two SCFG registers MSIIR and >> MSIR to support 32 MSI interrupts for each PCIe controller. >> The patch

Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

2016-03-23 Thread Marc Zyngier
On 23/03/16 11:19, Alexander Stein wrote: > On Wednesday 23 March 2016 11:08:04, Marc Zyngier wrote: >>> Using an intel e1000e card which uses 3 MSIs. But the IRQ numbers are a bit >>> strange though: grep eth3 /proc/interrupts 63: 49 0 MSI 134742016 Edge

Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

2016-03-23 Thread Marc Zyngier
On 23/03/16 11:19, Alexander Stein wrote: > On Wednesday 23 March 2016 11:08:04, Marc Zyngier wrote: >>> Using an intel e1000e card which uses 3 MSIs. But the IRQ numbers are a bit >>> strange though: grep eth3 /proc/interrupts 63: 49 0 MSI 134742016 Edge

Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

2016-03-23 Thread Alexander Stein
On Wednesday 23 March 2016 11:08:04, Marc Zyngier wrote: > > Using an intel e1000e card which uses 3 MSIs. But the IRQ numbers are a bit > > strange though: > >> grep eth3 /proc/interrupts > >> > >> 63: 49 0 MSI 134742016 Edge eth3-rx-0 > >> 64: 3 0

Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

2016-03-23 Thread Alexander Stein
On Wednesday 23 March 2016 11:08:04, Marc Zyngier wrote: > > Using an intel e1000e card which uses 3 MSIs. But the IRQ numbers are a bit > > strange though: > >> grep eth3 /proc/interrupts > >> > >> 63: 49 0 MSI 134742016 Edge eth3-rx-0 > >> 64: 3 0

Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

2016-03-23 Thread Marc Zyngier
On 23/03/16 09:18, Alexander Stein wrote: > On Monday 07 March 2016 11:36:22, Minghuan Lian wrote: >> Some kind of NXP Layerscape SoC provides a MSI >> implementation which uses two SCFG registers MSIIR and >> MSIR to support 32 MSI interrupts for each PCIe controller. >> The patch is to support

Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

2016-03-23 Thread Marc Zyngier
On 23/03/16 09:18, Alexander Stein wrote: > On Monday 07 March 2016 11:36:22, Minghuan Lian wrote: >> Some kind of NXP Layerscape SoC provides a MSI >> implementation which uses two SCFG registers MSIIR and >> MSIR to support 32 MSI interrupts for each PCIe controller. >> The patch is to support

RE: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

2016-03-23 Thread Minghuan Lian
; <mingkai...@nxp.com>; Stuart Yoder <stuart.yo...@nxp.com>; Yang-Leo Li > <leoyang...@nxp.com> > Subject: Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller > support > > On Monday 07 March 2016 11:36:22, Minghuan Lian wrote: > > Some kind

RE: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

2016-03-23 Thread Minghuan Lian
vger.kernel.org > Cc: Minghuan Lian ; > linux-arm-ker...@lists.infradead.org; Marc Zyngier ; > Thomas Gleixner ; Jason Cooper > ; Roy Zang ; Mingkai Hu > ; Stuart Yoder ; Yang-Leo Li > > Subject: Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller > support > &

Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

2016-03-23 Thread Alexander Stein
On Monday 07 March 2016 11:36:22, Minghuan Lian wrote: > Some kind of NXP Layerscape SoC provides a MSI > implementation which uses two SCFG registers MSIIR and > MSIR to support 32 MSI interrupts for each PCIe controller. > The patch is to support it. > > Signed-off-by: Minghuan Lian

Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

2016-03-23 Thread Alexander Stein
On Monday 07 March 2016 11:36:22, Minghuan Lian wrote: > Some kind of NXP Layerscape SoC provides a MSI > implementation which uses two SCFG registers MSIIR and > MSIR to support 32 MSI interrupts for each PCIe controller. > The patch is to support it. > > Signed-off-by: Minghuan Lian

Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

2016-03-07 Thread Marc Zyngier
On Mon, 7 Mar 2016 11:36:22 +0800 Minghuan Lian wrote: > Some kind of NXP Layerscape SoC provides a MSI > implementation which uses two SCFG registers MSIIR and > MSIR to support 32 MSI interrupts for each PCIe controller. > The patch is to support it. > > Signed-off-by:

Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

2016-03-07 Thread Marc Zyngier
On Mon, 7 Mar 2016 11:36:22 +0800 Minghuan Lian wrote: > Some kind of NXP Layerscape SoC provides a MSI > implementation which uses two SCFG registers MSIIR and > MSIR to support 32 MSI interrupts for each PCIe controller. > The patch is to support it. > > Signed-off-by: Minghuan Lian

[PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

2016-03-06 Thread Minghuan Lian
Some kind of NXP Layerscape SoC provides a MSI implementation which uses two SCFG registers MSIIR and MSIR to support 32 MSI interrupts for each PCIe controller. The patch is to support it. Signed-off-by: Minghuan Lian --- Change log v5: 1. drop nr_irqs from struct

[PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

2016-03-06 Thread Minghuan Lian
Some kind of NXP Layerscape SoC provides a MSI implementation which uses two SCFG registers MSIIR and MSIR to support 32 MSI interrupts for each PCIe controller. The patch is to support it. Signed-off-by: Minghuan Lian --- Change log v5: 1. drop nr_irqs from struct ls_scfg_msi v4: 1. do not