On Mon, Jul 28, 2014 at 05:09:11PM +0200, Maxime Ripard wrote:
> On Sun, Jul 27, 2014 at 07:49:42PM +0100, Mark Brown wrote:
> > There's supposed to be facilities appearing in the generic clock code
> > for specifying default clock tree configurations via the DT - it's quite
> > a common
On Mon, Jul 28, 2014 at 05:09:11PM +0200, Maxime Ripard wrote:
On Sun, Jul 27, 2014 at 07:49:42PM +0100, Mark Brown wrote:
There's supposed to be facilities appearing in the generic clock code
for specifying default clock tree configurations via the DT - it's quite
a common requirement
Hi Mark,
On Sun, Jul 27, 2014 at 07:49:42PM +0100, Mark Brown wrote:
> On Tue, Jul 01, 2014 at 01:48:52PM +0100, Mark Rutland wrote:
> > On Tue, Jul 01, 2014 at 08:21:19AM +0100, Maxime Ripard wrote:
>
> > > > It feels a little fragile to rely on the organisation of the clock tree
> > > > and
Hi Mark,
On Sun, Jul 27, 2014 at 07:49:42PM +0100, Mark Brown wrote:
On Tue, Jul 01, 2014 at 01:48:52PM +0100, Mark Rutland wrote:
On Tue, Jul 01, 2014 at 08:21:19AM +0100, Maxime Ripard wrote:
It feels a little fragile to rely on the organisation of the clock tree
and the naming
On Tue, Jul 01, 2014 at 01:48:52PM +0100, Mark Rutland wrote:
> On Tue, Jul 01, 2014 at 08:21:19AM +0100, Maxime Ripard wrote:
> > > It feels a little fragile to rely on the organisation of the clock tree
> > > and the naming thereof. If the IP block is ever reused on an SoC with a
> > >
On Tue, Jul 01, 2014 at 01:48:52PM +0100, Mark Rutland wrote:
On Tue, Jul 01, 2014 at 08:21:19AM +0100, Maxime Ripard wrote:
It feels a little fragile to rely on the organisation of the clock tree
and the naming thereof. If the IP block is ever reused on an SoC with a
different clock
On Sun, Jul 06, 2014 at 05:22:00PM +0200, Arnd Bergmann wrote:
> On Friday 04 July 2014, Maxime Ripard wrote:
> > > > > It feels a little fragile to rely on the organisation of the clock
> > > > > tree
> > > > > and the naming thereof. If the IP block is ever reused on an SoC with
> > > > > a
>
On Friday 04 July 2014, Maxime Ripard wrote:
> > > > It feels a little fragile to rely on the organisation of the clock tree
> > > > and the naming thereof. If the IP block is ever reused on an SoC with a
> > > > different clock tree layout then we have to handle things differently.
> > >
> > >
On Friday 04 July 2014, Maxime Ripard wrote:
It feels a little fragile to rely on the organisation of the clock tree
and the naming thereof. If the IP block is ever reused on an SoC with a
different clock tree layout then we have to handle things differently.
What do you suggest
On Sun, Jul 06, 2014 at 05:22:00PM +0200, Arnd Bergmann wrote:
On Friday 04 July 2014, Maxime Ripard wrote:
It feels a little fragile to rely on the organisation of the clock
tree
and the naming thereof. If the IP block is ever reused on an SoC with
a
different clock
Hi Maxime,
El 30/06/14 10:20, Maxime Ripard escribió:
The Allwinner A31 has a 16 channels DMA controller that it shares with the
newer A23. Although sharing some similarities with the DMA controller of the
older Allwinner SoCs, it's significantly different, I don't expect it to be
possible to
Hi Maxime,
El 30/06/14 10:20, Maxime Ripard escribió:
The Allwinner A31 has a 16 channels DMA controller that it shares with the
newer A23. Although sharing some similarities with the DMA controller of the
older Allwinner SoCs, it's significantly different, I don't expect it to be
possible to
Hi Mark,
On Tue, Jul 01, 2014 at 01:48:52PM +0100, Mark Rutland wrote:
> On Tue, Jul 01, 2014 at 08:21:19AM +0100, Maxime Ripard wrote:
> > On Mon, Jun 30, 2014 at 04:33:05PM +0100, Mark Rutland wrote:
> > > On Mon, Jun 30, 2014 at 04:19:06PM +0100, Maxime Ripard wrote:
> > > > On Mon, Jun 30,
Hi Mark,
On Tue, Jul 01, 2014 at 01:48:52PM +0100, Mark Rutland wrote:
On Tue, Jul 01, 2014 at 08:21:19AM +0100, Maxime Ripard wrote:
On Mon, Jun 30, 2014 at 04:33:05PM +0100, Mark Rutland wrote:
On Mon, Jun 30, 2014 at 04:19:06PM +0100, Maxime Ripard wrote:
On Mon, Jun 30, 2014 at
On Tue, Jul 01, 2014 at 08:21:19AM +0100, Maxime Ripard wrote:
> On Mon, Jun 30, 2014 at 04:33:05PM +0100, Mark Rutland wrote:
> > On Mon, Jun 30, 2014 at 04:19:06PM +0100, Maxime Ripard wrote:
> > > On Mon, Jun 30, 2014 at 03:20:54PM +0100, Mark Rutland wrote:
> > > > Hi Maxime,
> > > >
> > > >
On Mon, Jun 30, 2014 at 04:33:05PM +0100, Mark Rutland wrote:
> On Mon, Jun 30, 2014 at 04:19:06PM +0100, Maxime Ripard wrote:
> > On Mon, Jun 30, 2014 at 03:20:54PM +0100, Mark Rutland wrote:
> > > Hi Maxime,
> > >
> > > On Mon, Jun 30, 2014 at 02:20:54PM +0100, Maxime Ripard wrote:
> > > > The
On Mon, Jun 30, 2014 at 04:33:05PM +0100, Mark Rutland wrote:
On Mon, Jun 30, 2014 at 04:19:06PM +0100, Maxime Ripard wrote:
On Mon, Jun 30, 2014 at 03:20:54PM +0100, Mark Rutland wrote:
Hi Maxime,
On Mon, Jun 30, 2014 at 02:20:54PM +0100, Maxime Ripard wrote:
The Allwinner A31
On Tue, Jul 01, 2014 at 08:21:19AM +0100, Maxime Ripard wrote:
On Mon, Jun 30, 2014 at 04:33:05PM +0100, Mark Rutland wrote:
On Mon, Jun 30, 2014 at 04:19:06PM +0100, Maxime Ripard wrote:
On Mon, Jun 30, 2014 at 03:20:54PM +0100, Mark Rutland wrote:
Hi Maxime,
On Mon, Jun 30,
On Mon, Jun 30, 2014 at 04:19:06PM +0100, Maxime Ripard wrote:
> On Mon, Jun 30, 2014 at 03:20:54PM +0100, Mark Rutland wrote:
> > Hi Maxime,
> >
> > On Mon, Jun 30, 2014 at 02:20:54PM +0100, Maxime Ripard wrote:
> > > The Allwinner A31 has a 16 channels DMA controller that it shares with the
> >
On Mon, Jun 30, 2014 at 03:20:54PM +0100, Mark Rutland wrote:
> Hi Maxime,
>
> On Mon, Jun 30, 2014 at 02:20:54PM +0100, Maxime Ripard wrote:
> > The Allwinner A31 has a 16 channels DMA controller that it shares with the
> > newer A23. Although sharing some similarities with the DMA controller of
Hi Maxime,
On Mon, Jun 30, 2014 at 02:20:54PM +0100, Maxime Ripard wrote:
> The Allwinner A31 has a 16 channels DMA controller that it shares with the
> newer A23. Although sharing some similarities with the DMA controller of the
> older Allwinner SoCs, it's significantly different, I don't
The Allwinner A31 has a 16 channels DMA controller that it shares with the
newer A23. Although sharing some similarities with the DMA controller of the
older Allwinner SoCs, it's significantly different, I don't expect it to be
possible to share the driver for these two.
The A31 Controller is
The Allwinner A31 has a 16 channels DMA controller that it shares with the
newer A23. Although sharing some similarities with the DMA controller of the
older Allwinner SoCs, it's significantly different, I don't expect it to be
possible to share the driver for these two.
The A31 Controller is
Hi Maxime,
On Mon, Jun 30, 2014 at 02:20:54PM +0100, Maxime Ripard wrote:
The Allwinner A31 has a 16 channels DMA controller that it shares with the
newer A23. Although sharing some similarities with the DMA controller of the
older Allwinner SoCs, it's significantly different, I don't expect
On Mon, Jun 30, 2014 at 03:20:54PM +0100, Mark Rutland wrote:
Hi Maxime,
On Mon, Jun 30, 2014 at 02:20:54PM +0100, Maxime Ripard wrote:
The Allwinner A31 has a 16 channels DMA controller that it shares with the
newer A23. Although sharing some similarities with the DMA controller of the
On Mon, Jun 30, 2014 at 04:19:06PM +0100, Maxime Ripard wrote:
On Mon, Jun 30, 2014 at 03:20:54PM +0100, Mark Rutland wrote:
Hi Maxime,
On Mon, Jun 30, 2014 at 02:20:54PM +0100, Maxime Ripard wrote:
The Allwinner A31 has a 16 channels DMA controller that it shares with the
newer A23.
26 matches
Mail list logo
