Re: [PATCH v2] clk: sunxi: pll2: Fix clock running too fast

2015-12-02 Thread Stephen Boyd
On 12/01, Maxime Ripard wrote: > Contrary to what the datasheet says, the pre divider doesn't seem to be > incremented by one in the PLL2, but just uses the value from the register, > with 0 being a bypass. > > This fixes the audio playing too fast. > > Since we now have the same pre-divider

Re: [PATCH v2] clk: sunxi: pll2: Fix clock running too fast

2015-12-02 Thread Stephen Boyd
On 12/01, Maxime Ripard wrote: > Contrary to what the datasheet says, the pre divider doesn't seem to be > incremented by one in the PLL2, but just uses the value from the register, > with 0 being a bypass. > > This fixes the audio playing too fast. > > Since we now have the same pre-divider

[PATCH v2] clk: sunxi: pll2: Fix clock running too fast

2015-12-01 Thread Maxime Ripard
Contrary to what the datasheet says, the pre divider doesn't seem to be incremented by one in the PLL2, but just uses the value from the register, with 0 being a bypass. This fixes the audio playing too fast. Since we now have the same pre-divider flags, and the only difference with the A10 is

[PATCH v2] clk: sunxi: pll2: Fix clock running too fast

2015-12-01 Thread Maxime Ripard
Contrary to what the datasheet says, the pre divider doesn't seem to be incremented by one in the PLL2, but just uses the value from the register, with 0 being a bypass. This fixes the audio playing too fast. Since we now have the same pre-divider flags, and the only difference with the A10 is