On Fri, Feb 06, 2015 at 11:38:59AM -0800, Brian Norris wrote:
> > > An alternative would be to move this part into the read/write_buf
> > > functions, but that's a lot of work...
> > >
> >
> > Yeah, indeed. This also has other benefits. As we discussed on IRC, it
> > would allow to support raw
On Fri, Feb 06, 2015 at 11:17:15AM -0300, Ezequiel Garcia wrote:
> On 02/06/2015 05:13 AM, Boris Brezillon wrote:
> > On Thu, 5 Feb 2015 17:08:35 -0800
> > Brian Norris wrote:
> >> On Wed, Feb 04, 2015 at 11:10:28AM +0100, Boris Brezillon wrote:
> >>> I know the datasheet says this bit should be
On 02/06/2015 05:13 AM, Boris Brezillon wrote:
> Hi Brian,
>
> On Thu, 5 Feb 2015 17:08:35 -0800
> Brian Norris wrote:
>
>> + Rob
>>
>> This patch has conflicts with an ARM64-preparation from Rob. I'd like to
>> get this patch in first, as it's a bugfix. But I'd like to settle
>> Boris's
On Fri, Feb 06, 2015 at 09:13:07AM +0100, Boris Brezillon wrote:
> Hi Brian,
>
> On Thu, 5 Feb 2015 17:08:35 -0800
> Brian Norris wrote:
> > On Wed, Feb 04, 2015 at 11:10:28AM +0100, Boris Brezillon wrote:
> > > On Mon, 26 Jan 2015 15:56:03 +0100
> > > Maxime Ripard wrote:
> > > > +
Hi Brian,
On Thu, 5 Feb 2015 17:08:35 -0800
Brian Norris wrote:
> + Rob
>
> This patch has conflicts with an ARM64-preparation from Rob. I'd like to
> get this patch in first, as it's a bugfix. But I'd like to settle
> Boris's comments first.
>
> (Regarding the request to get this into 3.19:
On Fri, Feb 06, 2015 at 09:13:07AM +0100, Boris Brezillon wrote:
Hi Brian,
On Thu, 5 Feb 2015 17:08:35 -0800
Brian Norris computersforpe...@gmail.com wrote:
On Wed, Feb 04, 2015 at 11:10:28AM +0100, Boris Brezillon wrote:
On Mon, 26 Jan 2015 15:56:03 +0100
Maxime Ripard
Hi Brian,
On Thu, 5 Feb 2015 17:08:35 -0800
Brian Norris computersforpe...@gmail.com wrote:
+ Rob
This patch has conflicts with an ARM64-preparation from Rob. I'd like to
get this patch in first, as it's a bugfix. But I'd like to settle
Boris's comments first.
(Regarding the request to
On Fri, Feb 06, 2015 at 11:17:15AM -0300, Ezequiel Garcia wrote:
On 02/06/2015 05:13 AM, Boris Brezillon wrote:
On Thu, 5 Feb 2015 17:08:35 -0800
Brian Norris computersforpe...@gmail.com wrote:
On Wed, Feb 04, 2015 at 11:10:28AM +0100, Boris Brezillon wrote:
I know the datasheet says this
On Fri, Feb 06, 2015 at 11:38:59AM -0800, Brian Norris wrote:
An alternative would be to move this part into the read/write_buf
functions, but that's a lot of work...
Yeah, indeed. This also has other benefits. As we discussed on IRC, it
would allow to support raw writes (i.e. ECC
On 02/06/2015 05:13 AM, Boris Brezillon wrote:
Hi Brian,
On Thu, 5 Feb 2015 17:08:35 -0800
Brian Norris computersforpe...@gmail.com wrote:
+ Rob
This patch has conflicts with an ARM64-preparation from Rob. I'd like to
get this patch in first, as it's a bugfix. But I'd like to settle
+ Rob
This patch has conflicts with an ARM64-preparation from Rob. I'd like to
get this patch in first, as it's a bugfix. But I'd like to settle
Boris's comments first.
(Regarding the request to get this into 3.19: not likely. Judging by the
age of the "bug", it's not massively critical, and we
+ Rob
This patch has conflicts with an ARM64-preparation from Rob. I'd like to
get this patch in first, as it's a bugfix. But I'd like to settle
Boris's comments first.
(Regarding the request to get this into 3.19: not likely. Judging by the
age of the bug, it's not massively critical, and we
Hi Maxime,
On Mon, 26 Jan 2015 15:56:03 +0100
Maxime Ripard wrote:
> The NDDB register holds the data that are needed by the read and write
> commands.
>
> However, during a read PIO access, the datasheet specifies that after each 32
> bits read in that register, when BCH is enabled, we have
Hi Brian,
On Mon, Jan 26, 2015 at 03:56:03PM +0100, Maxime Ripard wrote:
> The NDDB register holds the data that are needed by the read and write
> commands.
>
> However, during a read PIO access, the datasheet specifies that after each 32
> bits read in that register, when BCH is enabled, we
Hi Brian,
On Mon, Jan 26, 2015 at 03:56:03PM +0100, Maxime Ripard wrote:
The NDDB register holds the data that are needed by the read and write
commands.
However, during a read PIO access, the datasheet specifies that after each 32
bits read in that register, when BCH is enabled, we have to
Hi Maxime,
On Mon, 26 Jan 2015 15:56:03 +0100
Maxime Ripard maxime.rip...@free-electrons.com wrote:
The NDDB register holds the data that are needed by the read and write
commands.
However, during a read PIO access, the datasheet specifies that after each 32
bits read in that register,
The NDDB register holds the data that are needed by the read and write
commands.
However, during a read PIO access, the datasheet specifies that after each 32
bits read in that register, when BCH is enabled, we have to make sure that the
RDDREQ bit is set in the NDSR register.
This fixes an
The NDDB register holds the data that are needed by the read and write
commands.
However, during a read PIO access, the datasheet specifies that after each 32
bits read in that register, when BCH is enabled, we have to make sure that the
RDDREQ bit is set in the NDSR register.
This fixes an
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