Hi Priit,
On 27 March 2017 at 04:20, Priit Laes wrote:
> +static struct ccu_nkmp pll_ve_clk = {
> + .enable = BIT(31),
> + .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
> + .k = _SUNXI_CCU_MULT(4, 2),
> + .m =
Hi Priit,
On 27 March 2017 at 04:20, Priit Laes wrote:
> +static struct ccu_nkmp pll_ve_clk = {
> + .enable = BIT(31),
> + .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
> + .k = _SUNXI_CCU_MULT(4, 2),
> + .m = _SUNXI_CCU_DIV(0, 2),
>
Hi Priit,
On 27 March 2017 at 04:20, Priit Laes wrote:
> Introduce a clock controller driver for sun4i A10 and sun7i A20
> series SoCs.
>
> Signed-off-by: Priit Laes
> ---
> drivers/clk/sunxi-ng/Kconfig | 13 +-
>
Hi Priit,
On 27 March 2017 at 04:20, Priit Laes wrote:
> Introduce a clock controller driver for sun4i A10 and sun7i A20
> series SoCs.
>
> Signed-off-by: Priit Laes
> ---
> drivers/clk/sunxi-ng/Kconfig | 13 +-
> drivers/clk/sunxi-ng/Makefile |1 +-
>
On Fri, Apr 21, 2017 at 3:59 AM, Priit Laes wrote:
> On Fri, Apr 07, 2017 at 03:38:05PM +0200, Maxime Ripard wrote:
>> Hi Priit,
>>
>> On Tue, Apr 04, 2017 at 08:09:19PM +, Priit Laes wrote:
>> > > > +/* Not documented on A10 */
>> > > > +static
On Fri, Apr 21, 2017 at 3:59 AM, Priit Laes wrote:
> On Fri, Apr 07, 2017 at 03:38:05PM +0200, Maxime Ripard wrote:
>> Hi Priit,
>>
>> On Tue, Apr 04, 2017 at 08:09:19PM +, Priit Laes wrote:
>> > > > +/* Not documented on A10 */
>> > > > +static SUNXI_CCU_GATE(pll_periph_sata_clk,
On Fri, Apr 07, 2017 at 03:38:05PM +0200, Maxime Ripard wrote:
> Hi Priit,
>
> On Tue, Apr 04, 2017 at 08:09:19PM +, Priit Laes wrote:
> > > > +/* Not documented on A10 */
> > > > +static SUNXI_CCU_GATE(pll_periph_sata_clk, "pll-periph-sata",
> > > > "pll-periph",
> > > > +
On Fri, Apr 07, 2017 at 03:38:05PM +0200, Maxime Ripard wrote:
> Hi Priit,
>
> On Tue, Apr 04, 2017 at 08:09:19PM +, Priit Laes wrote:
> > > > +/* Not documented on A10 */
> > > > +static SUNXI_CCU_GATE(pll_periph_sata_clk, "pll-periph-sata",
> > > > "pll-periph",
> > > > +
Hi Priit,
On Tue, Apr 04, 2017 at 08:09:19PM +, Priit Laes wrote:
> > > +/* Not documented on A10 */
> > > +static SUNXI_CCU_GATE(pll_periph_sata_clk, "pll-periph-sata",
> > > "pll-periph",
> > > + 0x028, BIT(14), 0);
> >
> > The rate doesn't come from pll-periph directly,
Hi Priit,
On Tue, Apr 04, 2017 at 08:09:19PM +, Priit Laes wrote:
> > > +/* Not documented on A10 */
> > > +static SUNXI_CCU_GATE(pll_periph_sata_clk, "pll-periph-sata",
> > > "pll-periph",
> > > + 0x028, BIT(14), 0);
> >
> > The rate doesn't come from pll-periph directly,
On Mon, Mar 27, 2017 at 09:54:38AM +0200, Maxime Ripard wrote:
> Hi,
>
> Thanks a lot for working on this.
>
> On Sun, Mar 26, 2017 at 08:20:16PM +0300, Priit Laes wrote:
> > Introduce a clock controller driver for sun4i A10 and sun7i A20
> > series SoCs.
> >
> > Signed-off-by: Priit Laes
On Mon, Mar 27, 2017 at 09:54:38AM +0200, Maxime Ripard wrote:
> Hi,
>
> Thanks a lot for working on this.
>
> On Sun, Mar 26, 2017 at 08:20:16PM +0300, Priit Laes wrote:
> > Introduce a clock controller driver for sun4i A10 and sun7i A20
> > series SoCs.
> >
> > Signed-off-by: Priit Laes
> >
Hi,
Thanks a lot for working on this.
On Sun, Mar 26, 2017 at 08:20:16PM +0300, Priit Laes wrote:
> Introduce a clock controller driver for sun4i A10 and sun7i A20
> series SoCs.
>
> Signed-off-by: Priit Laes
> ---
> drivers/clk/sunxi-ng/Kconfig | 13 +-
>
Hi,
Thanks a lot for working on this.
On Sun, Mar 26, 2017 at 08:20:16PM +0300, Priit Laes wrote:
> Introduce a clock controller driver for sun4i A10 and sun7i A20
> series SoCs.
>
> Signed-off-by: Priit Laes
> ---
> drivers/clk/sunxi-ng/Kconfig | 13 +-
>
Introduce a clock controller driver for sun4i A10 and sun7i A20
series SoCs.
Signed-off-by: Priit Laes
---
drivers/clk/sunxi-ng/Kconfig | 13 +-
drivers/clk/sunxi-ng/Makefile |1 +-
drivers/clk/sunxi-ng/ccu-sunxi-a10-a20.c | 1532
Introduce a clock controller driver for sun4i A10 and sun7i A20
series SoCs.
Signed-off-by: Priit Laes
---
drivers/clk/sunxi-ng/Kconfig | 13 +-
drivers/clk/sunxi-ng/Makefile |1 +-
drivers/clk/sunxi-ng/ccu-sunxi-a10-a20.c | 1532 ++-
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