Re: [PATCH v3 02/11] clk: tegra: retrieve regulator info from framework

On 06/02/18 16:34, Peter De Schrijver wrote: > The CVB table contains calibration data for the CPU DFLL based on > process charaterization. The regulator step and offset parameters depend > on the regulator supplying vdd-cpu , not on the specific Tegra SKU. > Hence than hardcoding those regulator

Re: [PATCH v3 02/11] clk: tegra: retrieve regulator info from framework

On 06/02/18 16:34, Peter De Schrijver wrote: > The CVB table contains calibration data for the CPU DFLL based on > process charaterization. The regulator step and offset parameters depend > on the regulator supplying vdd-cpu , not on the specific Tegra SKU. > Hence than hardcoding those regulator

[PATCH v3 02/11] clk: tegra: retrieve regulator info from framework

The CVB table contains calibration data for the CPU DFLL based on process charaterization. The regulator step and offset parameters depend on the regulator supplying vdd-cpu , not on the specific Tegra SKU. Hence than hardcoding those regulator parameters in the CVB table, retrieve them from the

[PATCH v3 02/11] clk: tegra: retrieve regulator info from framework

The CVB table contains calibration data for the CPU DFLL based on process charaterization. The regulator step and offset parameters depend on the regulator supplying vdd-cpu , not on the specific Tegra SKU. Hence than hardcoding those regulator parameters in the CVB table, retrieve them from the