On Tue, 2014-03-11 at 11:08 +0100, Maxime Ripard wrote:
[]
> > > + spin_lock_irq(&sdev->lock);
> > > + for (pchan_idx = 0; pchan_idx < NR_MAX_CHANNELS; pchan_idx++) {
> > > + pchan = &sdev->pchans[pchan_idx];
> > > +
> > > + if (pchan->vchan == NULL && !list_empty(&sdev->pending))
Hi,
On Tue, Mar 11, 2014 at 09:52:55AM +, Shevchenko, Andriy wrote:
> On Mon, 2014-03-10 at 15:41 +0100, Maxime Ripard wrote:
> > The Allwinner A31 has a 16 channels DMA controller that it shares with the
> > newer A23. Although sharing some similarities with the DMA controller of the
> > olde
On Mon, 2014-03-10 at 15:41 +0100, Maxime Ripard wrote:
> The Allwinner A31 has a 16 channels DMA controller that it shares with the
> newer A23. Although sharing some similarities with the DMA controller of the
> older Allwinner SoCs, it's significantly different, I don't expect it to be
> possibl
On Mon, Mar 10, 2014 at 06:57:00PM +0100, Arnd Bergmann wrote:
> On Monday 10 March 2014 17:51:56 Maxime Ripard wrote:
> > >
> > > Neither "pll6" nor "ahb1_mux" are listed in the DT binding. Also, why
> > > is it the driver's business to set the parent?
> >
> > Those are global clocks, so it's no
On Monday 10 March 2014 17:51:56 Maxime Ripard wrote:
> >
> > Neither "pll6" nor "ahb1_mux" are listed in the DT binding. Also, why
> > is it the driver's business to set the parent?
>
> Those are global clocks, so it's not really part pof the driver
> binding itself. But I can add them.
No bett
Hi Arnd,
On Mon, Mar 10, 2014 at 04:34:04PM +0100, Arnd Bergmann wrote:
> On Monday 10 March 2014 15:41:51 Maxime Ripard wrote:
>
> > +/*
> > + * Hardware representation of the LLI
> > + *
> > + * The hardware will be fed the physical address of this structure,
> > + * and read its content in ord
On Monday 10 March 2014 15:41:51 Maxime Ripard wrote:
> +/*
> + * Hardware representation of the LLI
> + *
> + * The hardware will be fed the physical address of this structure,
> + * and read its content in order to start the transfer.
> + */
> +struct sun6i_dma_lli {
> + u32
The Allwinner A31 has a 16 channels DMA controller that it shares with the
newer A23. Although sharing some similarities with the DMA controller of the
older Allwinner SoCs, it's significantly different, I don't expect it to be
possible to share the driver for these two.
The A31 Controller is able
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