* Andy Lutomirski wrote:
> > What do you want WT for, anyway?
>
> Generically, memory regions in which writes have side effects but reads
> are just reads and should be cached.
>
> In particular, persistent (i.e. nonvolatile) memory. There's an NDA
> involved, but I can safely say (at least
On Wed, May 1, 2013 at 10:54 AM, H. Peter Anvin wrote:
> On 05/01/2013 10:50 AM, Andy Lutomirski wrote:
>>
>> Isn't the upper half incompatible with large pages?
>>
>
> No, just with attributes *on the page tables themselves*.
Thanks :) Now I found the somewhat alarming algorithm in section 4.9.
On 05/01/2013 10:50 AM, Andy Lutomirski wrote:
>
> Isn't the upper half incompatible with large pages?
>
No, just with attributes *on the page tables themselves*.
-hpa
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On Wed, May 1, 2013 at 10:35 AM, H. Peter Anvin wrote:
> On 05/01/2013 09:54 AM, Andy Lutomirski wrote:
>>
>> (Just my luck. I'm currently trying to implement WT via PAT by
>> stealing a slot from either UC or UC-.)
>>
>
> NAK on that. Use a slot in the upper half, perhaps (we already
> blacklis
On 05/01/2013 10:20 AM, Theodore Ts'o wrote:
> On Wed, May 01, 2013 at 09:42:30AM -0700, H. Peter Anvin wrote:
>> The erratum reads seriously, but it only affects crossings between pages
>> of different page types, which is rare in itself. WT and WP are not
>> even used in Linux; the UC case we en
On 05/01/2013 09:54 AM, Andy Lutomirski wrote:
>
> (Just my luck. I'm currently trying to implement WT via PAT by
> stealing a slot from either UC or UC-.)
>
NAK on that. Use a slot in the upper half, perhaps (we already
blacklist the CPUs for which the upper half aren't usable.)
What do you
On 05/01/2013 09:34 AM, Theodore Ts'o wrote:
>
> In fact, there is the question of whether we should be checking to see
> if the CPU stepping is one of the ones with the bug, and if so, to
> have Linux disable fast strings even if the BIOS didn't, instead of
> blindly enabling fast strings
>
On Wed, May 01, 2013 at 09:42:30AM -0700, H. Peter Anvin wrote:
> The erratum reads seriously, but it only affects crossings between pages
> of different page types, which is rare in itself. WT and WP are not
> even used in Linux; the UC case we end up doing 8-byte stores instead of
> the proper s
On Wed, May 1, 2013 at 9:42 AM, H. Peter Anvin wrote:
> On 05/01/2013 09:34 AM, Theodore Ts'o wrote:
>>
>> In fact, there is the question of whether we should be checking to see
>> if the CPU stepping is one of the ones with the bug, and if so, to
>> have Linux disable fast strings even if the BIO
Theodore Ts'o writes:
>
> In fact, there is the question of whether we should be checking to see
> if the CPU stepping is one of the ones with the bug, and if so, to
> have Linux disable fast strings even if the BIOS didn't, instead of
> blindly enabling fast strings
Crossing pages with diffe
On Wed, May 01, 2013 at 01:33:52PM +0200, Borislav Petkov wrote:
> It could be some fast strings erratum like AAJ6 or BD3 (they have
> different names for what apparently is the same erratum in different
> docs). Simply search for "intel fast strings erratum" and sample the
> first couple of pdfs t
On Tue, Apr 30, 2013 at 10:46:00PM -0700, Andy Lutomirski wrote:
> From: Andrew Lutomirski
>
> Intel SDM volume 3A, 8.4.2 says:
>
> Software can disable fast-string operation by clearing the
> fast-string-enable bit (bit 0) of IA32_MISC_ENABLE MSR.
> However, Intel recomments that system s
* Andy Lutomirski wrote:
> From: Andrew Lutomirski
>
> Intel SDM volume 3A, 8.4.2 says:
>
> Software can disable fast-string operation by clearing the
> fast-string-enable bit (bit 0) of IA32_MISC_ENABLE MSR.
> However, Intel recomments that system software always enable
> fast-string
From: Andrew Lutomirski
Intel SDM volume 3A, 8.4.2 says:
Software can disable fast-string operation by clearing the
fast-string-enable bit (bit 0) of IA32_MISC_ENABLE MSR.
However, Intel recomments that system software always enable
fast-string operation.
The Intel DQ67SW board (with la
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