.org;
linux-
> ker...@vger.kernel.org; Christoph Hellwig
> Subject: Re: [RESEND][PATCH 07/10][SCSI]mpt2sas: Added Reply Descriptor
> Post Queue (RDPQ) Array support
>
>
> Sreekanth,
>
> > We need to satisfy this condition on those system where 32 bit dma
> > consistent ma
.org;
linux-
> ker...@vger.kernel.org; Christoph Hellwig
> Subject: Re: [RESEND][PATCH 07/10][SCSI]mpt2sas: Added Reply Descriptor
> Post Queue (RDPQ) Array support
>
>
> Sreekanth,
>
> > We need to satisfy this condition on those system where 32 bit dma
> > consistent ma
Sreekanth,
> We need to satisfy this condition on those system where 32 bit dma
> consistent mask is not supported and it only supports 64 bit dma
> consistent mask. So on these system we can't set
> pci_set_consistent_dma_mask() to DMA_BIT_MASK(32).
Which systems are you talking about?
It
Sreekanth,
> We need to satisfy this condition on those system where 32 bit dma
> consistent mask is not supported and it only supports 64 bit dma
> consistent mask. So on these system we can't set
> pci_set_consistent_dma_mask() to DMA_BIT_MASK(32).
Which systems are you talking about?
It
On Thu, Jul 24, 2014 at 1:16 AM, Martin K. Petersen
wrote:
>> "Sreekanth" == Sreekanth Reddy writes:
>
> Sreekanth,
>
> Sreekanth> 2. As per MPI Spec, each set of 8 reply descriptor post
> Sreekanth> queues must have the same value
On Thu, Jul 24, 2014 at 1:16 AM, Martin K. Petersen
wrote:
>> "Sreekanth" == Sreekanth Reddy writes:
>
> Sreekanth,
>
> Sreekanth> 2. As per MPI Spec, each set of 8 reply descriptor post
> Sreekanth> queues must have the same value for the upper 32-bits of
> Sreekanth> their memory address.
Can you please send me a single big series with all the mpt2 and mpt3
updates? With all the resends I'm losing track.
Please also pick up third party mpt patches like
'[PATCH 3/3] mpt3sas, mpt2sas: fix scsi_add_host error handling problems in
_scsih_probe' from Robert Elliott.
And while I
Can you please send me a single big series with all the mpt2 and mpt3
updates? With all the resends I'm losing track.
Please also pick up third party mpt patches like
'[PATCH 3/3] mpt3sas, mpt2sas: fix scsi_add_host error handling problems in
_scsih_probe' from Robert Elliott.
And while I
Up to now, Driver allocates a single contiguous block of memory
pool for all reply queues and passes down a single address in the
ReplyDescriptorPostQueueAddress field of the IOC Init Request
Message to the firmware.
When firmware receives this address, it will program each of the
Reply
Up to now, Driver allocates a single contiguous block of memory
pool for all reply queues and passes down a single address in the
ReplyDescriptorPostQueueAddress field of the IOC Init Request
Message to the firmware.
When firmware receives this address, it will program each of the
Reply
> "Sreekanth" == Sreekanth Reddy writes:
Sreekanth> Sending the this patch once agin using git send-email. Up to
Sreekanth> now, Driver allocates a single contiguous block of memory
Sreekanth> pool for all reply queues and passes down a single address in
Sreekanth> the
Sreekanth == Sreekanth Reddy sreekanth.re...@avagotech.com writes:
Sreekanth Sending the this patch once agin using git send-email. Up to
Sreekanth now, Driver allocates a single contiguous block of memory
Sreekanth pool for all reply queues and passes down a single address in
Sreekanth the
On Tue, Aug 12, 2014 at 3:07 PM, Joe Perches wrote:
> On Tue, 2014-08-12 at 14:54 +0530, Sreekanth Reddy wrote:
>> So, the proposal is to allocate memory independently for each
>> Reply Queue and pass down all of the addresses to the firmware.
>> Then the firmware will just take each address and
On Tue, 2014-08-12 at 14:54 +0530, Sreekanth Reddy wrote:
> So, the proposal is to allocate memory independently for each
> Reply Queue and pass down all of the addresses to the firmware.
> Then the firmware will just take each address and program the value
> into the correct register.
trivial
Sending the this patch once agin using git send-email.
Up to now, Driver allocates a single contiguous block of memory
pool for all reply queues and passes down a single address in the
ReplyDescriptorPostQueueAddress field of the IOC Init Request
Message to the firmware.
When firmware receives
Sending the this patch once agin using git send-email.
Up to now, Driver allocates a single contiguous block of memory
pool for all reply queues and passes down a single address in the
ReplyDescriptorPostQueueAddress field of the IOC Init Request
Message to the firmware.
When firmware receives
On Tue, 2014-08-12 at 14:54 +0530, Sreekanth Reddy wrote:
So, the proposal is to allocate memory independently for each
Reply Queue and pass down all of the addresses to the firmware.
Then the firmware will just take each address and program the value
into the correct register.
trivial note:
On Tue, Aug 12, 2014 at 3:07 PM, Joe Perches j...@perches.com wrote:
On Tue, 2014-08-12 at 14:54 +0530, Sreekanth Reddy wrote:
So, the proposal is to allocate memory independently for each
Reply Queue and pass down all of the addresses to the firmware.
Then the firmware will just take each
> "Sreekanth" == Sreekanth Reddy writes:
Sreekanth> Please let me known any further changes are required so that
Sreekanth> I can send this patch once again with git send-email.
I'm OK with the latest iteration.
--
Martin K. Petersen Oracle Linux Engineering
--
To unsubscribe from
Hi Martin,
Please let me known any further changes are required so that I can
send this patch once again with git send-email.
Regards,
Sreekanth
On Mon, Aug 11, 2014 at 6:45 PM, Sreekanth Reddy
wrote:
> Hi Martin,
>
> Please let me known any further changes are required so that I can send this
Sreekanth == Sreekanth Reddy sreekanth.re...@avagotech.com writes:
Sreekanth Please let me known any further changes are required so that
Sreekanth I can send this patch once again with git send-email.
I'm OK with the latest iteration.
--
Martin K. Petersen Oracle Linux Engineering
--
To
Hi Martin,
Please let me known any further changes are required so that I can
send this patch once again with git send-email.
Regards,
Sreekanth
On Mon, Aug 11, 2014 at 6:45 PM, Sreekanth Reddy
sreekanth.re...@avagotech.com wrote:
Hi Martin,
Please let me known any further changes are
> "Sreekanth" == Sreekanth Reddy writes:
Sreekanth,
Patch was mangled and I had to apply every single hunk by hand. Please
use git send-email.
+static int dma_mask;
+
+static int
+_base_wait_for_doorbell_int(struct MPT2SAS_ADAPTER *ioc, int timeout,
+int sleep_flag);
Sreekanth == Sreekanth Reddy sreekanth.re...@avagotech.com writes:
Sreekanth,
Patch was mangled and I had to apply every single hunk by hand. Please
use git send-email.
+static int dma_mask;
+
+static int
+_base_wait_for_doorbell_int(struct MPT2SAS_ADAPTER *ioc, int timeout,
+
Hi Martin,
Sorry for the delay as I was on vacation.
Here are the change set when compared to the initial patch
1. Declared the following functions at the beginning of the
mpt2sas_base.c file instead of moving all these functions before
mpt2sas_base_map_resources() function
a.
Hi Martin,
Sorry for the delay as I was on vacation.
Here are the change set when compared to the initial patch
1. Declared the following functions at the beginning of the
mpt2sas_base.c file instead of moving all these functions before
mpt2sas_base_map_resources() function
a.
> "Sreekanth" == Sreekanth Reddy writes:
Sreekanth,
Sreekanth> Following are the changes that I have done in this patch over
Sreekanth> the first RDPQ support patch,
Please, please do the function moves in a different patch. Or use a
simple prototype declaration like I did to avoid moving
Hi Martin,
Following are the changes that I have done in this patch over the
first RDPQ support patch,
1. Reduced the redundancy in the function
_base_release_memory_pools(), _base_allocate_memory_pools().
2. Set pci_set_consistent_dma_mask() to DMA_BIT_MASK(32). still I am
analysing whether
Hi Martin,
Following are the changes that I have done in this patch over the
first RDPQ support patch,
1. Reduced the redundancy in the function
_base_release_memory_pools(), _base_allocate_memory_pools().
2. Set pci_set_consistent_dma_mask() to DMA_BIT_MASK(32). still I am
analysing whether
Sreekanth == Sreekanth Reddy sreekanth.re...@avagotech.com writes:
Sreekanth,
Sreekanth Following are the changes that I have done in this patch over
Sreekanth the first RDPQ support patch,
Please, please do the function moves in a different patch. Or use a
simple prototype declaration like I
> "Sreekanth" == Sreekanth Reddy writes:
Sreekanth,
Sreekanth> 2. As per MPI Spec, each set of 8 reply descriptor post
Sreekanth> queues must have the same value for the upper 32-bits of
Sreekanth> their memory address. So allocated set of eight queues in a
Sreekanth> single pool and added
Hi Martin,
Following are the changes that I have done in this patch over the
first RDPQ support patch,
1. As per your suggestion reduced the redundancy in the function
_base_release_memory_pools(), _base_allocate_memory_pools().
2. As per MPI Spec, each set of 8 reply descriptor post queues must
Hi Martin,
Following are the changes that I have done in this patch over the
first RDPQ support patch,
1. As per your suggestion reduced the redundancy in the function
_base_release_memory_pools(), _base_allocate_memory_pools().
2. As per MPI Spec, each set of 8 reply descriptor post queues must
Sreekanth == Sreekanth Reddy sreekanth.re...@avagotech.com writes:
Sreekanth,
Sreekanth 2. As per MPI Spec, each set of 8 reply descriptor post
Sreekanth queues must have the same value for the upper 32-bits of
Sreekanth their memory address. So allocated set of eight queues in a
Sreekanth
> "Sreekanth" == Sreekanth Reddy writes:
Sreekanth,
>> Why do you need to special case !rdpq? Isn't reply_queue_count = 1 in
>> that case?
Sreekanth> [Sreekanth] we have added this RDPQ support in phase18. So,
Sreekanth> the firmware from less than phase18 doesn't have this RDPQ
Sreekanth>
Sreekanth == Sreekanth Reddy sreekanth.re...@avagotech.com writes:
Sreekanth,
Why do you need to special case !rdpq? Isn't reply_queue_count = 1 in
that case?
Sreekanth [Sreekanth] we have added this RDPQ support in phase18. So,
Sreekanth the firmware from less than phase18 doesn't have this
> "Sreekanth" == Reddy, Sreekanth writes:
Sreekanth,
@@ -2393,15 +2735,39 @@ _base_release_memory_pools(struct MPT2SAS_ADAPTER *ioc)
ioc->reply_free = NULL;
}
- if (ioc->reply_post_free) {
- pci_pool_free(ioc->reply_post_free_dma_pool,
-
Sreekanth == Reddy, Sreekanth sreekanth.re...@avagotech.com writes:
Sreekanth,
@@ -2393,15 +2735,39 @@ _base_release_memory_pools(struct MPT2SAS_ADAPTER *ioc)
ioc-reply_free = NULL;
}
- if (ioc-reply_post_free) {
-
Up to now, Driver allocates a single contiguous block of memory
pool for all reply queues and passes down a single address in the
ReplyDescriptorPostQueueAddress field of the IOC Init Request
Message to the firmware.
When firmware receives this address, it will program each of the
Reply
Up to now, Driver allocates a single contiguous block of memory
pool for all reply queues and passes down a single address in the
ReplyDescriptorPostQueueAddress field of the IOC Init Request
Message to the firmware.
When firmware receives this address, it will program each of the
Reply
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