>This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
>For Micron SPI NOR flash, enabling or disabling quad I/O protocol is
>controlled by
>EVCR (Enhanced Volatile Configuration Register), Quad I/O protocol bit 7.
>When EVCR bit 7 is reset to 0, the SPI NOR flash will
This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
For Micron SPI NOR flash, enabling or disabling quad I/O protocol is
controlled by
EVCR (Enhanced Volatile Configuration Register), Quad I/O protocol bit 7.
When EVCR bit 7 is reset to 0, the SPI NOR flash will operate
>Acked-by: Marek Vasut
Hi,brian
How about this patch? And can be accepted by linux-mtd?
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Please read
Acked-by: Marek Vasut ma...@denx.de
Hi,brian
How about this patch? And can be accepted by linux-mtd?
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>> Signed-off-by: bean huo
>I don't see anything obviously wrong.
>Acked-by: Marek Vasut
Hi,Brian
How do you think about this patch?
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Signed-off-by: bean huo bean...@micron.com
I don't see anything obviously wrong.
Acked-by: Marek Vasut ma...@denx.de
Hi,Brian
How do you think about this patch?
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More
On Wednesday, October 01, 2014 at 04:28:17 PM, bpqw wrote:
> This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
>
> For Micron SPI NOR flash, enabling or disabling quad I/O protocol is
> controlled by EVCR (Enhanced Volatile Configuration Register), Quad I/O
> protocol
On Wednesday, October 01, 2014 at 04:24:41 PM, Bean Huo 霍斌斌 (beanhuo) wrote:
> >> For Micron spi norflash,enables or disables quad I/O protocol ,which
> >> controled by EVCR(Enhanced Volatile Configuration Register) Quad I/O
> >> protocol bit 7.When EVCR bit 7 is reset to 0, the spi norflash will
>> For Micron spi norflash,enables or disables quad I/O protocol ,which
>> controled by EVCR(Enhanced Volatile Configuration Register) Quad I/O
>> protocol bit 7.When EVCR bit 7 is reset to 0, the spi norflash will
>> operate in quad I/O following the next WRITE ENHANCED VOLATILE
>>
For Micron spi norflash,enables or disables quad I/O protocol ,which
controled by EVCR(Enhanced Volatile Configuration Register) Quad I/O
protocol bit 7.When EVCR bit 7 is reset to 0, the spi norflash will
operate in quad I/O following the next WRITE ENHANCED VOLATILE
CONFIGURATION
On Wednesday, October 01, 2014 at 04:24:41 PM, Bean Huo 霍斌斌 (beanhuo) wrote:
For Micron spi norflash,enables or disables quad I/O protocol ,which
controled by EVCR(Enhanced Volatile Configuration Register) Quad I/O
protocol bit 7.When EVCR bit 7 is reset to 0, the spi norflash will
operate
On Wednesday, October 01, 2014 at 04:28:17 PM, bpqw wrote:
This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
For Micron SPI NOR flash, enabling or disabling quad I/O protocol is
controlled by EVCR (Enhanced Volatile Configuration Register), Quad I/O
protocol bit 7.
On Tuesday, September 30, 2014 at 04:47:39 AM, Bean Huo 霍斌斌 (beanhuo) wrote:
> For Micron spi norflash,enables or disables quad I/O
> protocol ,which controled by EVCR(Enhanced
> Volatile Configuration Register) Quad I/O
> protocol bit 7.When EVCR bit 7 is reset to 0,
> the spi norflash will
On Tuesday, September 30, 2014 at 04:47:39 AM, Bean Huo 霍斌斌 (beanhuo) wrote:
For Micron spi norflash,enables or disables quad I/O
protocol ,which controled by EVCR(Enhanced
Volatile Configuration Register) Quad I/O
protocol bit 7.When EVCR bit 7 is reset to 0,
the spi norflash will operate in
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