On 07/03/2019 09:06, Pawel Laszczak wrote:
> Hi,
>
>> Hi,
>>
>> On 21/02/2019 09:14, Felipe Balbi wrote:
>>>
>>> Hi,
>>>
>>> (please break your emails at 80-columns)
>>>
>>> Pawel Laszczak writes:
>> One more thing. Workaround has implemented algorithm that decide for
>> which
>>
Hi,
>Hi,
>
>On 21/02/2019 09:14, Felipe Balbi wrote:
>>
>> Hi,
>>
>> (please break your emails at 80-columns)
>>
>> Pawel Laszczak writes:
> One more thing. Workaround has implemented algorithm that decide for which
> endpoint it should be enabled. e.g for composite device MSC+NCM+ACM
Hi,
On 21/02/2019 09:14, Felipe Balbi wrote:
>
> Hi,
>
> (please break your emails at 80-columns)
>
> Pawel Laszczak writes:
One more thing. Workaround has implemented algorithm that decide for which
endpoint it should be enabled. e.g for composite device MSC+NCM+ACM it
should
Hi,
(please break your emails at 80-columns)
Pawel Laszczak writes:
>>> One more thing. Workaround has implemented algorithm that decide for which
>>> endpoint it should be enabled. e.g for composite device MSC+NCM+ACM it
>>> should work only for ACM OUT endpoint.
>>>
>>
>>If ACM driver
>
>On 20/02/2019 13:18, Pawel Laszczak wrote:
>> Hi Roger.
>>>
>>> On 14/02/2019 21:45, Pawel Laszczak wrote:
Controller for OUT endpoints has shared on-chip buffers for all incoming
packets, including ep0out. It's FIFO buffer, so packets must be handle
by DMA in correct order. If
Pawel,
On 20/02/2019 13:18, Pawel Laszczak wrote:
> Hi Roger.
>>
>> On 14/02/2019 21:45, Pawel Laszczak wrote:
>>> Controller for OUT endpoints has shared on-chip buffers for all incoming
>>> packets, including ep0out. It's FIFO buffer, so packets must be handle
>>> by DMA in correct order. If
Hi Roger.
>
>On 14/02/2019 21:45, Pawel Laszczak wrote:
>> Controller for OUT endpoints has shared on-chip buffers for all incoming
>> packets, including ep0out. It's FIFO buffer, so packets must be handle
>> by DMA in correct order. If the first packet in the buffer will not be
>> handled, then
Pawel,
On 14/02/2019 21:45, Pawel Laszczak wrote:
> Controller for OUT endpoints has shared on-chip buffers for all incoming
> packets, including ep0out. It's FIFO buffer, so packets must be handle
> by DMA in correct order. If the first packet in the buffer will not be
> handled, then the
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