Hi Yixun, thanks for the review
2018-08-03 16:14 GMT+02:00 Yixun Lan :
>> +config MESON_CANVAS
>> + bool "Amlogic Meson Canvas driver"
> shouldn't this a 'tristate'? since you'd make the driver a kernel module..
Yep it should!
I well noted your other feedback and v2 will have fixes for
Hi Yixun, thanks for the review
2018-08-03 16:14 GMT+02:00 Yixun Lan :
>> +config MESON_CANVAS
>> + bool "Amlogic Meson Canvas driver"
> shouldn't this a 'tristate'? since you'd make the driver a kernel module..
Yep it should!
I well noted your other feedback and v2 will have fixes for
HI Maxime
thanks for contributing the patches ;-)
On Thu, Aug 2, 2018 at 2:51 AM, Maxime Jourdan wrote:
> Amlogic SoCs have a repository of 256 canvas which they use to
> describe pixel buffers.
>
> They contain metadata like width, height, block mode, endianness [..]
>
> Many IPs within those
HI Maxime
thanks for contributing the patches ;-)
On Thu, Aug 2, 2018 at 2:51 AM, Maxime Jourdan wrote:
> Amlogic SoCs have a repository of 256 canvas which they use to
> describe pixel buffers.
>
> They contain metadata like width, height, block mode, endianness [..]
>
> Many IPs within those
Hi Neil,
2018-08-02 10:38 GMT+02:00 Neil Armstrong :
> Please switch to the spdx header format here and in the .h.
> In the DRM driver these are updated in IRQ context, we should make sure we
> don't sleep
> in interrupt context if IRQ occurs when the VDEC updates it's canvases.
>
> Could you
Hi Neil,
2018-08-02 10:38 GMT+02:00 Neil Armstrong :
> Please switch to the spdx header format here and in the .h.
> In the DRM driver these are updated in IRQ context, we should make sure we
> don't sleep
> in interrupt context if IRQ occurs when the VDEC updates it's canvases.
>
> Could you
Hi Maxime,
On 01/08/2018 20:51, Maxime Jourdan wrote:
> Amlogic SoCs have a repository of 256 canvas which they use to
> describe pixel buffers.
>
> They contain metadata like width, height, block mode, endianness [..]
>
> Many IPs within those SoCs like vdec/vpu rely on those canvas to
Hi Maxime,
On 01/08/2018 20:51, Maxime Jourdan wrote:
> Amlogic SoCs have a repository of 256 canvas which they use to
> describe pixel buffers.
>
> They contain metadata like width, height, block mode, endianness [..]
>
> Many IPs within those SoCs like vdec/vpu rely on those canvas to
Hi Maxime,
On 01/08/2018 20:51, Maxime Jourdan wrote:
> Amlogic SoCs have a repository of 256 canvas which they use to
> describe pixel buffers.
>
> They contain metadata like width, height, block mode, endianness [..]
>
> Many IPs within those SoCs like vdec/vpu rely on those canvas to
Hi Maxime,
On 01/08/2018 20:51, Maxime Jourdan wrote:
> Amlogic SoCs have a repository of 256 canvas which they use to
> describe pixel buffers.
>
> They contain metadata like width, height, block mode, endianness [..]
>
> Many IPs within those SoCs like vdec/vpu rely on those canvas to
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