From: Punnaiah Choudary Kalluri
Include multi queue support for the ethernet IP version in xilinx ZynqMP
SoC.
Signed-off-by: Punnaiah Choudary Kalluri
Signed-off-by: Michal Simek
---
drivers/net/ethernet/cadence/macb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drive
From: Punnaiah Choudary Kalluri
ZynqMP soc has single interrupt for all the queue events. So,
passing the IRQF_SHARED flag for interrupt registration call.
Signed-off-by: Punnaiah Choudary Kalluri
Signed-off-by: Michal Simek
---
drivers/net/ethernet/cadence/macb.c | 2 +-
1 file changed, 1 i
Avoid the warning below triggered during dmaengine async device
registration.
WARNING: CPU: 1 PID: 1 at linux/drivers/dma/dmaengine.c:863
dma_async_device_register+0x2a8/0x4b8()
this driver doesn't support generic slave capabilities reporting
To do that fill mandatory .directions bit mask,
.src/d
The IRQF_DISABLED is a NOOP and has been scheduled for removal since
Linux v2.6.36 by commit 6932bf37bed4 ("genirq: Remove IRQF_DISABLED from
core code").
According to commit e58aa3d2d0cc ("genirq: Run irq handlers with
interrupts disabled") running IRQ handlers with interrupts enabled can
cause s
Dear Antoine Tenart,
On Thu, 5 Mar 2015 12:31:21 +0100, Antoine Tenart wrote:
> struct pxa3xx_nand_host {
> @@ -253,6 +258,12 @@ static struct pxa3xx_nand_flash builtin_flash_types[] = {
> { "512MiB 8-bit", 0xdc2c, 64, 2048, 8, 8, 4096 },
> { "512MiB 16-bit", 0xcc2c, 64, 2048, 16, 16, 40
On 03/04/2015 07:05 PM, Azael Avalos wrote:
> Hi there,
>
> 2015-03-04 14:52 GMT-07:00 Joseph Salisbury :
> ...
>> + { KE_KEY, 0x140, { KEY_BRIGHTNESSDOWN } },
>> + { KE_KEY, 0x141, { KEY_BRIGHTNESSUP } },
> ...
>
> These two are not neccesary, as they may collide with "previous song"
>
On Wed 04-03-15 13:21:26, Andrew Morton wrote:
> On Wed, 4 Mar 2015 16:13:01 -0500 Johannes Weiner wrote:
>
> > I don't even care about NOMMU, this is just wrong on principle.
>
> Agree. And I do care about nommu ;)
>
> If some nommu person wants to start using memcg and manages to get it
> do
Hi Fabrice,
On 03/05/2015 01:47 PM, Fabrice GASNIER wrote:
This patch adds support to STiH410 SoC.
Actually, the STiH410 support is already here in v4.0-rc1.
The problem is that it is missing the entry in the match table,
and so the L2 cache and other cpus than 0 don't get initialized.
Once f
On Thu, Mar 5, 2015 at 11:17 AM, Will Deacon wrote:
> On Wed, Mar 04, 2015 at 11:14:50PM +, Rafael J. Wysocki wrote:
>> On Monday, March 02, 2015 12:00:21 PM Al Stone wrote:
>> > On 03/02/2015 10:29 AM, Will Deacon wrote:
>> > > On Wed, Feb 25, 2015 at 12:36:24AM +, al.st...@linaro.org wro
On 03/04/2015 05:32 PM, Kirill A. Shutemov wrote:
> Hello everybody,
>
> It's bug-fix update of my thp refcounting work.
>
> The goal of patchset is to make refcounting on THP pages cheaper with
> simpler semantics and allow the same THP compound page to be mapped with
> PMD and PTEs. This is req
Thomas,
On Thu, Mar 05, 2015 at 01:50:23PM +0100, Thomas Petazzoni wrote:
> On Thu, 5 Mar 2015 12:31:20 +0100, Antoine Tenart wrote:
> > Use the nand framework helpers: onfi_get_async_timing_mode() and
> > onfi_async_timing_mode_to_sdr_timings() to retrieve the timing
> > configuration. Then upda
Dear Antoine Tenart,
On Thu, 5 Mar 2015 12:31:20 +0100, Antoine Tenart wrote:
> Use the nand framework helpers: onfi_get_async_timing_mode() and
> onfi_async_timing_mode_to_sdr_timings() to retrieve the timing
> configuration. Then update the pxa3xx timing setup function to use the
> timing confi
This patch adds support to STiH410 SoC.
Signed-off-by: Fabrice Gasnier
---
Documentation/devicetree/bindings/arm/sti.txt | 4
arch/arm/mach-sti/board-dt.c | 1 +
2 files changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/sti.txt
b/Documentation/de
On 2015/3/5 19:36, Ingo Molnar wrote:
>
> * Li, Aubrey wrote:
>
>> On 2015/3/5 4:11, Ingo Molnar wrote:
>>>
>>> * Arjan van de Ven wrote:
>>>
On 3/4/2015 1:50 AM, Borislav Petkov wrote:
> On Wed, Mar 04, 2015 at 12:43:08AM -0800, Arjan van de Ven wrote:
>>>
>>> Using 'acpi_gbl_
Signed-off-by: Fengguang Wu
---
ioremap.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/lib/ioremap.c b/lib/ioremap.c
index 3055ada..1634c53 100644
--- a/lib/ioremap.c
+++ b/lib/ioremap.c
@@ -14,9 +14,9 @@
#include
#ifdef CONFIG_HAVE_ARCH_HUGE_VMAP
-int __read
tree: git://git.cmpxchg.org/linux-mmotm.git master
head: fe8eec967fb5db169b876720a6e0cced026173b6
commit: e4dc2631d6de08fe1ee5421944a71c7c89ed1d90 [126/298] x86, mm: support
huge KVA mappings on x86
reproduce:
# apt-get install sparse
git checkout e4dc2631d6de08fe1ee5421944a71c7c89ed1d90
On 03/05/15 00:45, Emil Medve wrote:
From: Igal Liberman
The Freescale Data Path Acceleration Architecture (DPAA) is a set of
hardware components on specific QorIQ P and T series multicore processors.
This architecture provides the infrastructure to support simplified
sharing of networking inte
On (03/05/15 13:10), Karel Zak wrote:
> > > we upgraded our scripts but landed some bugs there? it's up to particular
> > > implementation. in your example, I assume, someone used zram with
> > > num_devices >= 1000?
> > > that's impossible. current num_devices limitation is 32. and uid-s start
>
On Thu, 05 Mar 2015, Artem Savkov wrote:
> Since commit 0b2712585(linux-next.git) this driver uses regmap_irq and so
> needs
> to select REGMAP_IRQ.
>
> This fixes the following compilation errors:
> ERROR: "regmap_irq_get_domain" [drivers/mfd/rt5033.ko] undefined!
> ERROR: "regmap_add_irq_chip"
On Thu, 2015-03-05 at 01:54 +0100, Ingo Molnar wrote:
> * Daniel Thompson wrote:
>
> > Much of the code sitting in arch/x86/kernel/apic/hw_nmi.c to support
> > safe all-cpu backtracing from NMI has been copied to printk.c to
> > make it accessible to other architectures.
> >
> > Port the x86 N
On 02/23/2015 04:35 PM, jamie.gars...@york.ac.uk wrote:
> From: Jamie Garside
>
> This patch fixes two bugs in the Microblaze syscall trap handler when an
> invalid
> syscall ID is used.
>
> First, the range check on line 351 only checks for syscall IDs greater than
> __NR_syscalls. A negative
When keeping the configuration set by the bootloader (by using
the marvell,nand-keep-config property), the pxa3xx_nand_detect_config()
function is called and set the chunk size to 512 as a default value if
NDCR_PAGE_SZ is not set.
In the other case, when not keeping the bootloader configuration, n
Hi all,
This series introduces the support for the Marvell Berlin nand
controller. It is based on top of v4.0-rc1 and was tested on the
Marvell Berlin BG2Q DMP board.
The support is added into the existing pxa3xx nand controller. Some
additions were done in order to get this controller working:
-
Some controllers (as the coming Berlin nand controller) need to enable
an ECC clock. Add support for this clock in the pxa3xx nand driver, and
leave it as non mandatory.
Signed-off-by: Antoine Tenart
---
drivers/mtd/nand/pxa3xx_nand.c | 32 +++-
1 file changed, 23 ins
On Wed, Mar 04, 2015 at 05:29:14PM +0100, Lino Sanfilippo wrote:
> On 04.03.2015 15:35, Dave Martin wrote:
>
> >
> >Try
> >
> >rm drivers/clk/mvebu/kirkwood.o
> >make ARCH=arm KBUILD_CFLAGS_KERNEL=-save-temps drivers/clk/mvebu/kirkwood.o
> >
> >(abuse of KBUILD_CFLAGS_KERNEL here, but it's empty b
On (03/05/15 13:02), Karel Zak wrote:
> > hm, you never know what people can come up with. that's probably the
> > strongest support argument I can provide. I wish there was something
> > like - my friend Mike has a "device /dev/zram1 is always swap device,
> > device /dev/zram$(id -u) is a per-use
The pxa3xx nand driver requires at least one clock to probe correctly.
A second one, named 'ecc' can be specified if needed. Add the
corresponding documentation.
Signed-off-by: Antoine Tenart
---
Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt | 4
1 file changed, 4 insertions(+)
dif
The BG2Q DMP has a nand controller. Add the corresponding node, but do
not enable it by default because the nand is only available on some BG2Q
DMP.
Signed-off-by: Antoine Tenart
---
arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 25 +
1 file changed, 25 insertions(+)
diff
Use the nand framework helpers: onfi_get_async_timing_mode() and
onfi_async_timing_mode_to_sdr_timings() to retrieve the timing
configuration. Then update the pxa3xx timing setup function to use the
timing configuration retrieved.
Signed-off-by: Antoine Tenart
---
drivers/mtd/nand/pxa3xx_nand.c
On Thu, Mar 05, 2015 at 05:38:23AM +, Chanwoo Choi wrote:
> This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on
> Octal core CPUs (quad Cortex-A57 and quad Cortex-A53). And Exynos5433 supports
> PSCI (Power State Coordination Interface) v0.1.
>
> This patch includes f
Marvell Berlin nand controller support has been added in the pxa3xx nand
driver. Let these SoCs select the driver.
Signed-off-by: Antoine Tenart
---
drivers/mtd/nand/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
in
The Berlin nand controller support was introduced using the existing
pxa3xx nand driver. Add the Berlin specific compatible into the
documentation.
Signed-off-by: Antoine Tenart
---
Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Document
The nand controller on Marvell Berlin SoC reuse the pxa3xx nand driver
as it quite close. The process of sending commands can be compared to
the one of the Marvell armada 370: read and write commands are done in
chunks.
But the Berlin nand controller has some other specificities which
require some
Hi Geert,
On 03/05/2015 07:02 AM, Geert Uytterhoeven wrote:
> Hi Peter,
>
> On Wed, Mar 4, 2015 at 6:24 PM, Peter Hurley wrote:
>> --- a/drivers/tty/serial/earlycon.c
>> +++ b/drivers/tty/serial/earlycon.c
>> @@ -69,6 +69,7 @@ static void __init earlycon_init(struct earlycon_device
>> *device,
On Wed, Mar 04, 2015 at 09:05:04PM -0800, Nicolin Chen wrote:
> According to i.MX6 Series Reference Manual, the formula to calculate
> the sys clock is
Applied, thanks.
signature.asc
Description: Digital signature
Add a node describing the nand controller of the Marvell Berlin BG2Q
SoC. It uses the pxa3xx nand driver, with a dedicated compatible.
Also add the corresponding pinmuxing configuration.
Signed-off-by: Antoine Tenart
---
arch/arm/boot/dts/berlin2q.dtsi | 13 +
1 file changed, 13 ins
On Thu, Mar 05, 2015 at 06:35:36PM +0800, Peter Chen wrote:
> Any good ways at code/dts to show parent/child hierarchy for regulator?
There's plenty of examples in mainline...
> The related regulators at my platforms like below:
> PMIC (SWB 5v) --> Switch Chip (GPIO Regulator) --> USB VBUS
> PM
Hi Peter,
Am 05.03.2015 um 11:35 schrieb Peter Chen:
> Hi lists,
>
> Any good ways at code/dts to show parent/child hierarchy for regulator?
>
> The related regulators at my platforms like below:
> PMIC (SWB 5v) --> Switch Chip (GPIO Regulator) --> USB VBUS
>
> PMIC has one 5V regulator (eg, swbst
The matrix headers are not used anymore, remove them.
Signed-off-by: Alexandre Belloni
---
.../mach-at91/include/mach/at91sam9260_matrix.h| 80 ---
.../mach-at91/include/mach/at91sam9261_matrix.h| 64 -
.../mach-at91/include/mach/at91sam9263_matrix.h| 129 --
Hi,
This series removes more mach/headers.
Then it introduces a more scalable SoC detection infrastructure which allows to
remove the at91_map_io/at91_alt_map_io and iotable_init ugliness.
Changes in v2:
- All the SoC names are lowercased
- Removed the unused compatible string
- Use name/subn
From: Boris BREZILLON
Add new structures and functions to handle AT91 SoC detection.
[alexandre.bell...@free-electrons.com: reworked DBGU detection]
Signed-off-by: Alexandre Belloni
Signed-off-by: Boris BREZILLON
---
arch/arm/Kconfig| 1 +
arch/arm/mach-at91/Makefile | 2 +-
a
Use the soc detection infrastructure for at91sam9 initialization.
Signed-off-by: Alexandre Belloni
---
arch/arm/mach-at91/at91sam9.c | 86 ---
arch/arm/mach-at91/soc.h | 30 +++
2 files changed, 94 insertions(+), 22 deletions(-)
diff --gi
Use the soc detection infrastructure for at91rm9200 initialization.
Signed-off-by: Alexandre Belloni
---
arch/arm/mach-at91/at91rm9200.c | 34 --
arch/arm/mach-at91/soc.h| 3 +++
2 files changed, 23 insertions(+), 14 deletions(-)
diff --git a/arch/arm/ma
The old setup is not used anymore, remove it
Signed-off-by: Alexandre Belloni
---
arch/arm/mach-at91/Makefile | 2 +-
arch/arm/mach-at91/setup.c | 320
2 files changed, 1 insertion(+), 321 deletions(-)
delete mode 100644 arch/arm/mach-at91/setup.c
Use the soc detection infrastructure for sama5 initialization.
Signed-off-by: Alexandre Belloni
---
arch/arm/mach-at91/sama5.c | 54 +-
arch/arm/mach-at91/soc.h | 14
2 files changed, 53 insertions(+), 15 deletions(-)
diff --git a/arch/
On 04/03/15 03:18, Yun Wu wrote:
> This patch series makes some enhancement to ITS configuration in the
> following aspects:
>
> o make allocation of the ITS tables more sensible
> o replace magic numbers with sensible macros
> o guarantees a safe quiescent status before initializing an ITS
>
> T
at91_ioremap_matrix and the at91_matrix.h header are not used anymore, remove
them.
Signed-off-by: Alexandre Belloni
---
arch/arm/mach-at91/generic.h | 4
arch/arm/mach-at91/include/mach/at91_matrix.h | 23 ---
arch/arm/mach-at91/setup.c
The DBGU is not a simple UART and we need to be able to distinguish it from the
other UARTs, in particular to get its address and check the chip id.
Signed-off-by: Alexandre Belloni
---
Documentation/devicetree/bindings/serial/atmel-usart.txt | 3 ++-
arch/arm/boot/dts/at91rm9200.dtsi
From: Arnd Bergmann
The mach/io.h header on at91 is used to support a nonstandard I/O space
window for the cf card driver. This changes the driver to use pci_ioremap_io
in order to have the standard location, and then removes the custom
mach/io.h.
[alexandre.bell...@free-electrons.com: Added PCI
On Wed, 2015-03-04 at 09:21 -0800, Joe Perches wrote:
> On Wed, 2015-03-04 at 16:33 +, Daniel Thompson wrote:
> > On Wed, 2015-03-04 at 11:20 -0500, Steven Rostedt wrote:
> > > On Wed, 04 Mar 2015 08:13:21 -0800
> > > Joe Perches wrote:
> > >
> > > > On Wed, 2015-03-04 at 10:12 +, Daniel
On Thu, Mar 5, 2015 at 5:06 AM, Archit Taneja wrote:
>
> On 02/23/2015 09:09 PM, Daniel Vetter wrote:
>>
>> On Mon, Feb 23, 2015 at 10:03:21AM -0500, Rob Clark wrote:
>>>
>>> On Mon, Feb 23, 2015 at 9:09 AM, Daniel Vetter wrote:
On Mon, Feb 23, 2015 at 08:33:36AM -0500, Rob Clark wrote:
On Thu, Mar 05, 2015 at 11:04:36AM +0900, Minchan Kim wrote:
> On Thu, Mar 05, 2015 at 10:47:52AM +0900, Sergey Senozhatsky wrote:
> > On (03/05/15 10:33), Minchan Kim wrote:
> > > > hm, I can think of a huge build server with tons of users.
> > > > /dev/zram$(id -u)
> > > > created during user lo
On Thu, Mar 05, 2015 at 11:33:06AM +, Alexandre Belloni wrote:
> On 05/03/2015 at 11:04:11 +, Mark Rutland wrote :
> > > > +In rare cases an IRQ can be shared between a wakeup device driver and
> > > > an
> > > > +IRQF_NO_SUSPEND user. In order for this to be safe, the wakeup device
> > >
On 04/03/15 03:18, Yun Wu wrote:
> It's unsafe to change the configurations of an activated ITS directly
> since this will lead to unpredictable results. This patch guarantees
> the ITSes being initialized are quiescent.
>
> Signed-off-by: Yun Wu
> ---
> drivers/irqchip/irq-gic-v3-its.c | 35 +++
Cc Sami Kerola, Timofey Titovets, Karel Zak, util-linux
(don't have Jóhann B. Guðmundsson's email). also published on google+.
On (03/05/15 09:20), Minchan Kim wrote:
> > Make zram-contol/zram_add interface easier to use. Extend it to support
> > read and write operations.
> >
> > Write operation
On Thu, Mar 05, 2015 at 09:58:29AM +0900, Sergey Senozhatsky wrote:
> Hello,
>
> On (03/05/15 09:20), Minchan Kim wrote:
> > I'm not against but I want to know why we should support
> > user-defined device id. What usecase do you have in mind?
> >
>
> hm, you never know what people can come up w
Hi Peter,
On Wed, Mar 4, 2015 at 6:24 PM, Peter Hurley wrote:
> --- a/drivers/tty/serial/earlycon.c
> +++ b/drivers/tty/serial/earlycon.c
> @@ -69,6 +69,7 @@ static void __init earlycon_init(struct earlycon_device
> *device,
> const char *name)
> {
> str
With old Kernels there was a bug in x86 where any unknown
memory chip type would come up BUSY when calling
request_mem_region_exclusive().
So for pmem to work with old Kernels and real NvDIMM chips
we have a new Kconfig option CONFIG_BLK_DEV_PMEM_IGNORE_REQUEST_MEM_RET.
People have been running
One of the current shortcomings of the NVDIMM/PMEM
support is that this memory does not have a page-struct(s)
associated with its memory and therefor cannot be passed
to a block-device or network or DMAed in any way through
another device in the system.
The use of add_persistent_memory() fixes al
On 04/03/15 03:18, Yun Wu wrote:
> Define macros for GITS_CTLR fields to avoid using magic numbers.
>
> Signed-off-by: Yun Wu
Acked-by: Marc Zyngier
M.
> ---
> drivers/irqchip/irq-gic-v3-its.c | 2 +-
> include/linux/irqchip/arm-gic-v3.h | 3 +++
> 2 files changed, 4 insertions(+),
Persistent Memory is not Memory. It is not presented as
a Memory Zone and is not available through the page allocators
for application/kernel volatile usage.
It belongs to A block device just as any other Persistent storage,
the novelty here is that it is directly mapped on the CPU Memory
bus, an
From: Yigal Korman
Refactored the arguments of sparse_add_one_section / sparse_remove_one_section
to use node id instead of struct zone * - A memory section has no direct
connection to zones, all that was needed from zone was the node id.
This is for add_persistent_memory that will want a sectio
> bcma also needs PCI, just like IOMEM and DMA, so let it depend on PCI,
> or will cause building break for allmodconfig under c6x:
>
> CC [M] drivers/bcma/driver_pcie2.o
> drivers/bcma/driver_pcie2.c: In function 'bcma_core_pcie2_up':
> drivers/bcma/driver_pcie2.c:196:8: error: implicit
From: Ross Zwisler
Also fixed a top the initial version
[boaz]
SQUASHME pmem: Micro optimization the hotpath 002
Signed-off-by: Ross Zwisler
Signed-off-by: Boaz Harrosh
---
drivers/block/pmem.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/block/pmem.c b/driv
From: Ross Zwisler
Based on commit a72132c31d58 ("brd: add support for rw_page()")
Signed-off-by: Ross Zwisler
---
drivers/block/pmem.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/block/pmem.c b/drivers/block/pmem.c
index bba53af..750ffdf 100644
--- a/drivers/block
Though this looks revolutionary, it actually does nothing
but removes dead code.
Since the move of pmem to the dynamic BLOCK_EXT_MAJOR
range, by Ross, pmem_major returned from register_blkdev
is not used.
If inspecting the code at add_disk() we can see that
whatever number we will put at
From: Ross Zwisler
PMEM is a new driver That supports any physical contiguous iomem range
as a single block device. The driver has support for as many as needed
iomem ranges each as its own device.
The driver is not only good for NvDIMMs, It is good for any flat memory
mapped device. We've used
Dear Markus,
Am 05.03.2015 um 08:35 schrieb Markus Pargmann:
Good point. The easy way to solve this may be to check in the remove
function if the devicetree node for this device is available. If it is,
we know that platform_data was allocated with devm_* and we can set
platform_data to NULL.
I
Hi Boris,
TL;DR - I guess using IRQF_NO_SUSPEND for now is OK a a best-effort
approach for now, so don't let my comments block this patch.
However, there are still some potential issues in what would already be
a failure case: your usual wakeup mechanism not waking the system up in
time to poke t
On Wed, Mar 04, 2015 at 11:50:36PM +0100, Rafael J. Wysocki wrote:
> On Wednesday, February 25, 2015 04:39:56 PM Hanjun Guo wrote:
> > From: Tomasz Nowicki
> >
> > ACPI kernel uses MADT table for proper GIC initialization. It needs to
> > parse GIC related subtables, collect CPU interface and dis
Commit-ID: c709feda56886c38af3116254f84cbe6a78b3a5d
Gitweb: http://git.kernel.org/tip/c709feda56886c38af3116254f84cbe6a78b3a5d
Author: Ingo Molnar
AuthorDate: Thu, 5 Mar 2015 08:58:44 +0100
Committer: Ingo Molnar
CommitDate: Thu, 5 Mar 2015 09:48:17 +0100
x86/mm/pat: Initialize __cache
Commit-ID: 73c8c861dc5bddf1b24c6aeffee2292c96cf8db2
Gitweb: http://git.kernel.org/tip/73c8c861dc5bddf1b24c6aeffee2292c96cf8db2
Author: Luis R. Rodriguez
AuthorDate: Wed, 4 Mar 2015 17:24:14 -0800
Committer: Ingo Molnar
CommitDate: Thu, 5 Mar 2015 08:02:12 +0100
x86/mm: Use early_param_
Commit-ID: d9fd579c218e22c897f0f1b9e132af9b436cf445
Gitweb: http://git.kernel.org/tip/d9fd579c218e22c897f0f1b9e132af9b436cf445
Author: Luis R. Rodriguez
AuthorDate: Wed, 4 Mar 2015 17:24:11 -0800
Committer: Ingo Molnar
CommitDate: Thu, 5 Mar 2015 08:02:11 +0100
x86/mm: Use IS_ENABLED()
Commit-ID: e5008abe929c160d36e44b8c2b644d4330d2e389
Gitweb: http://git.kernel.org/tip/e5008abe929c160d36e44b8c2b644d4330d2e389
Author: Luis R. Rodriguez
AuthorDate: Wed, 4 Mar 2015 17:24:12 -0800
Committer: Ingo Molnar
CommitDate: Thu, 5 Mar 2015 08:02:12 +0100
x86/mm: Simplify enablin
On Thu, 5 Mar 2015 07:57:09 +0100
Daniel Wagner wrote:
> Hi Jeff,
>
> On 03/05/2015 01:06 AM, Jeff Layton wrote:
> > Commit 8634b51f6ca2 (locks: convert lease handling to file_lock_context)
> > introduced a regression in the handling of lease upgrade/downgrades.
> >
> > In the event that we alr
Commit-ID: bfb33bad83f650f265ed65cbfe8352b7c3ce8c76
Gitweb: http://git.kernel.org/tip/bfb33bad83f650f265ed65cbfe8352b7c3ce8c76
Author: Luis R. Rodriguez
AuthorDate: Wed, 4 Mar 2015 17:24:13 -0800
Committer: Ingo Molnar
CommitDate: Thu, 5 Mar 2015 08:02:12 +0100
init.h: Add early_param_
Commit-ID: 956421fbb74c3a6261903f3836c0740187cf038b
Gitweb: http://git.kernel.org/tip/956421fbb74c3a6261903f3836c0740187cf038b
Author: Andy Lutomirski
AuthorDate: Thu, 5 Mar 2015 01:09:44 +0100
Committer: Ingo Molnar
CommitDate: Thu, 5 Mar 2015 01:12:23 +0100
x86/asm/entry/64: Remove a
On Thu, Mar 05, 2015 at 04:36:38AM -0500, Tejun Heo wrote:
> On Thu, Mar 05, 2015 at 10:24:50AM +0100, Tomeu Vizoso wrote:
> ...
> > [ 317.251001] PC is at bit_waitqueue+0x38/0x6c
> ...
> > [ 317.420658] [] (bit_waitqueue) from []
> > (__cancel_work_timer+0x28/0x1b0)
> > [ 317.430598] [] (__canc
On Wed, Mar 04, 2015 at 11:32:12PM +0100, Paul Bolle wrote:
> Chih-Chiang Chang schreef op wo 04-03-2015 om 20:53 [+0800]:
> > +struct nau8824_platform_data {
> In the future something other than just sound/soc/codecs/nau8824.h is
> going to include this header, right?
It's platform data, that's
Since commit 0b2712585(linux-next.git) this driver uses regmap_irq and so needs
to select REGMAP_IRQ.
This fixes the following compilation errors:
ERROR: "regmap_irq_get_domain" [drivers/mfd/rt5033.ko] undefined!
ERROR: "regmap_add_irq_chip" [drivers/mfd/rt5033.ko] undefined!
Signed-off-by: Artem
On (03/05/15 14:29), Sergey Senozhatsky wrote:
> On (03/04/15 14:02), a...@linux-foundation.org wrote:
> > +What: /sys/block/zram/compact
> > +Date: August 2015
> > +Contact: Minchan Kim
> > +Description:
> > + The compact file is write-only and trigger compac
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Rafał Miłecki writes:
> Kalle, I guess the recent discussion and work on this problem could be
> confusing, so let me try to sum it up it a bit.
>
> First of all, please note there are 3 awaiting bcma patches that
> should be applied independently of what we decide to do with this
> patch. They a
* Li, Aubrey wrote:
> On 2015/3/5 4:11, Ingo Molnar wrote:
> >
> > * Arjan van de Ven wrote:
> >
> >> On 3/4/2015 1:50 AM, Borislav Petkov wrote:
> >>> On Wed, Mar 04, 2015 at 12:43:08AM -0800, Arjan van de Ven wrote:
> >
> > Using 'acpi_gbl_reduced_hardware' flag outside the ACPI cod
On 05/03/2015 at 11:04:11 +, Mark Rutland wrote :
> > > +In rare cases an IRQ can be shared between a wakeup device driver and an
> > > +IRQF_NO_SUSPEND user. In order for this to be safe, the wakeup device
> > > driver
> > > +must be able to discern spurious IRQs from genuine wakeup events
>
On 5 March 2015 at 18:51, Sascha Hauer wrote:
> On Thu, Mar 05, 2015 at 05:39:12PM +0800, Pi-Cheng Chen wrote:
>> On 5 March 2015 at 17:19, Sascha Hauer wrote:
>> > On Thu, Mar 05, 2015 at 02:29:50PM +0530, Viresh Kumar wrote:
>> >> On 5 March 2015 at 13:12, Sascha Hauer wrote:
>> >> > We have c
On 05/03/15 11:27, Paolo Bonzini wrote:
>
>
> On 05/03/2015 11:53, Marc Zyngier wrote:
>>> +#ifdef CONFIG_HAVE_KVM_IRQFD
>>> + case KVM_CAP_IRQFD:
>>> + r = vgic_present;
>>> + break;
>>> +#endif
>>
>> Nitpick: we have "select HAVE_KVM_IRQFD", so we can lose the #ifdef-ery.
On Thu, 5 Mar 2015 12:17:23 +0100
Boris Brezillon wrote:
> Hi Boris,
^ Mark,
I'm suffering from a dual personality disorder :-)
>
> On Thu, 5 Mar 2015 10:53:08 +
> Mark Rutland wrote:
>
> > Hi Boris,
> >
> > I'd missed the fact that this was for SW watchdog as opposed to HW
> > wa
Hi!
> Userland access goes via /dev/cmt_speech. The API is implemented in
> libcmtspeechdata, which is used by ofono and the freesmartphone.org project.
> Apart from that the device is also used by the phone binaries distributed
> with Maemo. So while this is a new userland ABI for the mainline ke
On Thu, Mar 05, 2015 at 04:03:21PM +0800, Hanjun Guo wrote:
> On 2015/3/5 6:46, Rafael J. Wysocki wrote:
> > IMO, you really need to define phys_cpuid_t in a common place or people will
> > forget that it may be 64-bit, because they'll only be looking at their arch.
>
> Since x86 and ARM64 are usi
On 05/03/2015 11:53, Marc Zyngier wrote:
> > +#ifdef CONFIG_HAVE_KVM_IRQFD
> > + case KVM_CAP_IRQFD:
> > + r = vgic_present;
> > + break;
> > +#endif
>
> Nitpick: we have "select HAVE_KVM_IRQFD", so we can lose the #ifdef-ery.
Alternatively, I've just posted a patch to mov
IS_ENABLED gives compile-time checking and keeps the code clearer.
The one exception is inside kvm_vm_ioctl_check_extension, where
the established idiom is to wrap the case labels with an #ifdef.
Signed-off-by: Paolo Bonzini
--
Untested...
---
arch/arm/kvm/arm.c | 17 +
On 2015/3/5 5:52, Rafael J. Wysocki wrote:
> On Wednesday, March 04, 2015 08:21:01 PM Alan Cox wrote:
>> On Wed, 2015-03-04 at 15:05 +0100, Borislav Petkov wrote:
>>> On Wed, Mar 04, 2015 at 03:16:07PM +0100, Rafael J. Wysocki wrote:
Sort of. What we need is a "do not touch PIC/PIT" bit for t
On 04/03/15 03:18, Yun Wu wrote:
> When required size of Device Table is out of the page allocator's
> capability, the whole ITS will fail in probing. This actually is
> not the hardware's problem and is mainly a limitation of the kernel
> page allocator. This patch will keep ITS going on to the ne
Fix coding style to comply with checkpatch.pl
Signed-off-by: Anda-Maria Nicolae
---
drivers/power/bq2415x_charger.c | 24
1 file changed, 8 insertions(+), 16 deletions(-)
diff --git a/drivers/power/bq2415x_charger.c b/drivers/power/bq2415x_charger.c
index e384844..628
Hello,
First patch from patchset fixes coding style issues: removes unnecessary else
after return.
This way, the coding style complies with checkpatch.pl.
Second patch from patchset updates bq2415x driver to support bq24157s charger.
Thanks,
Anda
Anda-Maria Nicolae (2):
bq2415x_charger: Remo
This patch adds bq24157s charger in the list of supported chargers.
bq24157s is similar to bq24158, except for Bit6 from Special Charger
Voltage/Enable Pin Status register, but this register is currently
not used by bq2415x_charger.
Signed-off-by: Anda-Maria Nicolae
---
drivers/power/bq2415x_cha
On 02/20/2015, 04:20 PM, Kalle Valo wrote:
> Josh Cartwright writes:
>
>> From: Kalle Valo
>>
>> commit 31b9cc9a873dcab161999622314f98a75d838975 upstream.
>>
>> Jason noticed that with Yocto GCC 4.8.1 ath6kl crashes with this iperf
>> command:
>>
>> iperf -c $TARGET_IP -i 5 -t 50 -w 1M
>>
>> Th
On 05/03/15 01:07, David Rientjes wrote:
On Wed, 4 Mar 2015, Alex Dowad wrote:
The 'stack_size' argument is never used to pass a stack size. It's only used
when
forking a kernel thread, in which case it is an argument which should be passed
to the 'main' function which the kernel thread execu
Hi Boris,
On Thu, 5 Mar 2015 10:53:08 +
Mark Rutland wrote:
> Hi Boris,
>
> I'd missed the fact that this was for SW watchdog as opposed to HW
> watchdog, which may explain my confusion.
>
> [...]
>
> > > > err = request_irq(wdt->irq, wdt_interrupt,
> > > > -
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