Change the Documentation/vm/zswap.txt doc to indicate that the zpool
and compressor params are now changeable at runtime.
Cc: Vlastimil Babka vba...@suse.cz
Signed-off-by: Dan Streetman ddstr...@ieee.org
---
changes since v1:
update doc on working of zbud per Vlastimil Babka's suggestion
add
On Mon, Aug 24, 2015 at 01:02:17PM -0400, Jeff Moyer wrote:
Ross Zwisler ross.zwis...@linux.intel.com writes:
Only read 32 bits for the BLK status register in read_blk_stat().
The format and size of this register is defined in the
NVDIMM Driver Writer's guide:
On Thu, 20 Aug 2015 18:17:10 +0800
Nan Xiao xiaonan830...@gmail.com wrote:
According to Intel Virtualization Technology for Directed I/O specification,
DRHD stands for DMA Remapping Hardware Unit Definition , not DMA
Engine Reporting Structure.
Applied to the docs tree, thanks.
Note that
On Fri, Aug 21, 2015 at 4:54 PM, Tony Luck tony.l...@gmail.com wrote:
On Fri, Aug 21, 2015 at 1:50 PM, Yinghai Lu ying...@kernel.org wrote:
Still stuff going on that I don't understand here. I increased the amount of
mirrored memory in this machine which moved max_pfn to 0x756
and
Hi,
On 8/25/15 00:32, Bjorn Helgaas wrote:
On Mon, Aug 24, 2015 at 9:41 AM, Suravee Suthikulpanit
suravee.suthikulpa...@amd.com wrote:
Hi,
Ping. Does anyone have any comments or suggestions?
Yes, I sent you some ideas a couple weeks ago. I'll resend them.
Not sure how I missed that one.
Hello, Dave.
On Fri, Aug 21, 2015 at 09:04:51AM +1000, Dave Chinner wrote:
Maybe I'm misunderstanding the code but all xfs_writepage() calls are
from unbound workqueues - the writeback workers - while
xfs_setfilesize() are from bound workqueues, so I wondered why that
was and looked at
24.08.2015 20:43, David Miller пишет:
From: Eugene Shatokhin eugene.shatok...@rosalab.ru
Date: Wed, 19 Aug 2015 14:59:01 +0300
So the following might be possible, although unlikely:
CPU0 CPU1
clear_bit: read dev-flags
clear_bit: clear
On Sun, Aug 23, 2015 at 12:23 PM, H. Peter Anvin h...@zytor.com wrote:
On 08/23/2015 04:45 AM, tip-bot for Andy Lutomirski wrote:
Commit-ID: 47edb65178cb7056c2eea0b6c41a7d8c84547192
Gitweb:
http://git.kernel.org/tip/47edb65178cb7056c2eea0b6c41a7d8c84547192
Author: Andy Lutomirski
Typo fixed - s/succees/success
Signed-off-by: Alexander Kuleshov kuleshovm...@gmail.com
---
mm/memblock.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/mm/memblock.c b/mm/memblock.c
index 87108e7..8742db8 100644
--- a/mm/memblock.c
+++ b/mm/memblock.c
@@ -758,7
This issue was noticed while debugging a CPU hotplug issue. On x86
with (NR_CPUS 1) the cpu_online() define is cpumask_test_cpu().
cpumask_test_cpu() should return 1 if the cpu is set in cpumask and
0 otherwise.
However, cpumask_test_cpu() returns -1 if the cpu in the cpumask is
set and 0
On 8/22/2015 2:24 AM, Ingo Molnar wrote:
* Jonathan (Zhixiong) Zhang zjzh...@codeaurora.org wrote:
From: Jonathan (Zhixiong) Zhang zjzh...@codeaurora.org
With ACPI APEI firmware first handling, generic hardware error
record is updated by firmware in GHES memory region. On an arm64
From: Jonathan (Zhixiong) Zhang zjzh...@codeaurora.org
GHES memory region is used as a communication buffer for reporting
hardware errors from the firmware to kernel. Essentially the
firmware writes hardware error records there, triggers an NMI/interrupt,
then the GHES driver goes off and grabs
Add a binding documentation for the Broadcom BCM7038 PWM controller found in
BCM7xxx chips.
Signed-off-by: Florian Fainelli f.faine...@gmail.com
---
.../devicetree/bindings/pwm/brcm,bcm7038-pwm.txt | 22 ++
1 file changed, 22 insertions(+)
create mode 100644
On Mon, 24 Aug 2015, Shenwei Wang wrote:
That's what you want achieve. Still you save the full content of the
registers and
restore the full content. That saves/restores the enabled and disabled
interrupts.
So enabled_irqs is a misnomer as you save the full state.
How about change
On 08/24, Oleg Nesterov wrote:
I booted the kernel with the additional patch below, and nothing bad has
happened,
Until I tried reboot it once with locktorture.verbose=true paramater.
It didn't boot.
This is because parse_args() just aborts after it hits the error, so other
arguments at the
On 23/08/15 21:36, Masahiro Yamada wrote:
The smp_operations structure is not over-written, so add const
qualifier and replace __initdata with __initconst.
Also, add static to bcm63138_smp_ops.
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
For bcm63xx and brcmstb:
On Sun, Aug 23, 2015 at 11:10:31PM +1000, Aleksa Sarai wrote:
Grab a ref to each source css being migrated from, otherwise it's
possible for the refcount to reach zero between -can_attach() and
-cancel_attach(). This means that operations on the task's old css
(such as container_of(...))
On Mon, 24 Aug 2015, David Miller wrote:
From: Eugene Shatokhin eugene.shatok...@rosalab.ru
Date: Wed, 19 Aug 2015 14:59:01 +0300
So the following might be possible, although unlikely:
CPU0 CPU1
clear_bit: read dev-flags
clear_bit:
On Mon, 24 Aug 2015, Alan Stern wrote:
On Mon, 24 Aug 2015, David Miller wrote:
From: Eugene Shatokhin eugene.shatok...@rosalab.ru
Date: Wed, 19 Aug 2015 14:59:01 +0300
So the following might be possible, although unlikely:
CPU0 CPU1
clear_bit:
-Original Message-
From: Thomas Gleixner [mailto:t...@linutronix.de]
+static int gpcv2_wakeup_source_save(void) {
+ struct gpcv2_irqchip_data *cd;
+ void __iomem *reg;
+ int i;
+
+ cd = imx_gpcv2_instance;
+ if (!cd)
+
Ezequiel Garcia ezequ...@vanguardiasur.com.ar writes:
Should we worry about having two definitions for the same bit?
Would it be too ugly to mix the two meaning? Something like this:
/* This bit has two different meanings on NFCv1 and NFCv2 */
#define NDCR_STOP_ON_UNCOR_ARB_CNTL (0x1 19)
I
On Mon, Aug 24, 2015 at 01:09:46PM +0100, Mel Gorman wrote:
diff --git a/lib/radix-tree.c b/lib/radix-tree.c
index f9ebe1c82060..c3775ee46cd6 100644
--- a/lib/radix-tree.c
+++ b/lib/radix-tree.c
@@ -188,7 +188,7 @@ radix_tree_node_alloc(struct radix_tree_root *root)
* preloading in
Hi,
This patch series add PWM support for the Broadcom BCM7xxx
chips which feature one or more PWM controllers capable of
output periods from 148ns to ~622ms using a combination of
variable and fixed frequency settings.
The controller does not support setting a polarity.
This is based on
Add support for the BCM7038-style PWM controller found in all BCM7xxx STB SoCs.
This controller has a hardcoded 2 channels per controller, and cascades a
variable frequency generator on top of a fixed frequency generator which offers
a range of a 148ns period all the way to ~622ms periods.
Since bits_per_word isn't usually checked during SPI setup the 9-bit
support must be checked manually.
Signed-off-by: Stefan Wahren stefan.wah...@i2se.com
---
drivers/staging/fbtft/fbtft-core.c |7 +++
drivers/staging/fbtft/flexfb.c |7 +++
2 files changed, 14 insertions(+)
Calling the setup of the SPI master directly causes a NULL pointer
dereference with master drivers without a separate setup function.
This problem is reproduceable on ARM MXS platform.
So fix this issue by using spi_setup() instead.
Signed-off-by: Stefan Wahren stefan.wah...@i2se.com
---
This patch series fixes the 9-bit SPI support of fbtft.
Stefan Wahren (2):
staging: fbtft: replace master-setup() with spi_setup()
staging: fbtft: fix 9-bit SPI support detection
drivers/staging/fbtft/fb_uc1611.c|2 +-
drivers/staging/fbtft/fb_watterott.c |4 ++--
Hi,
In linux-next as of today (0824), all h8300 builds fail for me with an internal
compiler error.
Building h8300:allnoconfig ... failed
--
Error log:
In file included from include/linux/rcupdate.h:429:0,
from include/linux/rcusync.h:5,
from
From: Alan Stern st...@rowland.harvard.edu
Date: Mon, 24 Aug 2015 14:06:15 -0400 (EDT)
On Mon, 24 Aug 2015, David Miller wrote:
Atomic operations like clear_bit also will behave that way.
Are you certain about that? I couldn't find any mention of it in
Documentation/atomic_ops.txt.
In
On Thu, Aug 20, 2015 at 11:16:53PM +0100, Eduardo Valentin wrote:
On Mon, Aug 17, 2015 at 06:36:45PM +0100, Javi Merino wrote:
The power allocator governor currently requires that a sustainable power
is passed as part of the thermal zone's thermal zone parameters. If
that parameter is not
On Mon, Aug 24, 2015 at 7:17 PM, Lars-Peter Clausen l...@metafoo.de wrote:
On 08/06/2015 05:19 AM, Punnaiah Choudary Kalluri wrote:
[...]
+Optional properties:
+- xlnx,include-sg: Indicates the controller to operate in simple or scatter
+gather dma mode
+- xlnx,ratectrl:
Now pxa architecture has a dmaengine driver, remove the access to direct
dma registers in favor of the more generic dmaengine code.
This should be also applicable for mmp and orion, provided they work in
device-tree environment.
This patch also removes the previous hack which was necessary to
On Sun, Aug 23, 2015 at 10:29:15PM -0700, Paul E. McKenney wrote:
On Sun, Aug 23, 2015 at 10:07:49PM -0700, David Miller wrote:
1) Doc bug, documentation mentions torture_type such as rcu_sync,
but those don't seem to exist.
2) If you specify an unrecognized type, the module cannot
I am trying to build perf tool on Powerpc and get this:
util/intel-pt-decoder/intel-pt-insn-decoder.c: In function
‘intel_pt_insn_decoder’:
util/intel-pt-decoder/intel-pt-insn-decoder.c:138:3: error: switch missing
default case [-Werror=switch-default]
switch (insn-immediate.nbytes) {
^
On Wed, Aug 5, 2015 at 10:19 PM, Punnaiah Choudary Kalluri
punnaiah.choudary.kall...@xilinx.com wrote:
Device-tree binding documentation for Xilinx zynqmp dma engine used in
Zynq UltraScale+ MPSoC.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
Changes in v4:
- None
On Mon, Aug 24, 2015 at 8:00 PM, Eric B Munson emun...@akamai.com wrote:
On Mon, 24 Aug 2015, Konstantin Khlebnikov wrote:
On Mon, Aug 24, 2015 at 6:55 PM, Eric B Munson emun...@akamai.com wrote:
On Mon, 24 Aug 2015, Konstantin Khlebnikov wrote:
On Mon, Aug 24, 2015 at 6:09 PM, Eric B
old_len is used to store the return value of btrfs_item_size_nr().
The return value of btrfs_item_size_nr() is of type u32.
To improve code correctness and avoid mixing signed and unsigned
integers I've changed old_len to be of type u32 as well.
Signed-off-by: Alexandru Moise
From: Paul E. McKenney paul...@linux.vnet.ibm.com
Date: Mon, 24 Aug 2015 11:50:36 -0700
@@ -695,7 +695,7 @@ static bool __maybe_unused torturing_tasks(void)
#define RCUTORTURE_TASKS_OPS
-static bool torturing_tasks(void)
+static bool __maybe_unused torturing_tasks(void)
{
Driver had coding style issues where spaces were used instead
of tabs. This patch fixes them all.
Signed-off-by: Vaibhav Hiremath vaibhav.hirem...@linaro.org
---
drivers/mfd/88pm800.c | 125 --
1 file changed, 61 insertions(+), 64 deletions(-)
88PM800 family of devices provides multiple buffered 32.768 KHz clock
output.
88PM800 : CLK32k_1, CLK32k_2 and CLK32k_3
88PM860 : CLK32k_1 and CLK32k_2
This patch-series adds new clock provider driver for enabling/disabling
buffered 32Khz clock output from 88PM800 family of device. Adds clock
Driver had coding style issues where spaces were used instead
of tabs. This patch fixes them all.
Signed-off-by: Vaibhav Hiremath vaibhav.hirem...@linaro.org
---
drivers/mfd/88pm800.c | 125 --
1 file changed, 61 insertions(+), 64 deletions(-)
This patch updates the binding documentation for optional
clocks node and related information for buffered 32KHz clock.
Signed-off-by: Vaibhav Hiremath vaibhav.hirem...@linaro.org
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Acked-by: Rob Herring r...@kernel.org
---
Update header file with required macros for 32KHz buffered clock
output of 88PM800 family of device.
These macros will be used in clk provider driver.
Signed-off-by: Vaibhav Hiremath vaibhav.hirem...@linaro.org
---
include/linux/mfd/88pm80x.h | 12
1 file changed, 12 insertions(+)
This patch adds mfd_cell/clk-subdevice for 88PM800 MFD
(and family of devices).
Signed-off-by: Vaibhav Hiremath vaibhav.hirem...@linaro.org
---
drivers/mfd/88pm800.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/mfd/88pm800.c b/drivers/mfd/88pm800.c
index
88PM800 family of devices supports buffered 32KHz clock output,
for example,
88PM800: CLK32k_1, CLK32k_2 and CLK32k_3
88PM860: CLK32K_1 and CLK32K_2
This patch adds new clk provider driver to support enable/disable
of the 32KHz clock output from 88PM800 family of devices.
Signed-off-by: Vaibhav
Hello,
On Sun, Aug 23, 2015 at 11:10:32PM +1000, Aleksa Sarai wrote:
Fix incorrect usage of css_get and css_put to put a different css in
pids_{cancel_,}attach() than the one grabbed in pids_can_attach(). This
could lead to quite serious memory leakage (and unsafe operations on the
putted
IMX7D contains a new version of GPC IP block (GPCv2). It has two
major functions: power management and wakeup source management.
This patch adds a new irqchip driver to manage the interrupt wakeup
sources on IMX7D.
When the system is in WFI (wait for interrupt) mode, this GPC block
will be the
Hi Peter,
Did you the explanations in the following reply make sense to you?
If you needed more clarifications, please advice. Thanks!
Forwarded Message
From: Hon Ching(Vicky) Lo hon...@linux.vnet.ibm.com
To: Peter Hüwe peterhu...@gmx.de
Cc:
On Mon 24-08-15 13:11:44, Tejun Heo wrote:
Hello,
On Mon, Aug 24, 2015 at 10:51:50AM -0400, Tejun Heo wrote:
Bah, I see the problem and indeed it was introduced by commit
e79729123f639
writeback: don't issue wb_writeback_work if clean. The problem is that
we bail out of
Hi Bjorn,
On 8/25/15 00:32, Bjorn Helgaas wrote:
Here it is again.
On Thu, Aug 13, 2015 at 6:50 PM, Bjorn Helgaas bhelg...@google.com wrote:
Hi Suravee,
On Thu, Aug 13, 2015 at 04:58:45PM +0700, Suravee Suthikulpanit wrote:
This patch refactors of_pci_dma_configure() into a more generic
On Sun, Aug 23, 2015 at 07:00:23PM +0530, Aparna Karuthodi wrote:
Oh! Sorry! I made the changes to correct the faults you figured out.
Is it okay now?
Resubmit it properly with PATCH v2 in the title and a good commit message.
Signed-off-by: Aparna Karuthodi kdasapa...@gmail.com
---
From: Luis R. Rodriguez mcg...@suse.com
Ingo,
This is my pending series of patches for both write-combining and moving
Linux' use of MTRR into the grave. It combines three set of straggler patch
series which have been pending integration for a while now. The rename patches
do not depend in any
From: Luis R. Rodriguez mcg...@suse.com
This lets drivers take advantage of PAT when available. It should help
with the transition of converting video drivers over to ioremap_wc()
to help with the goal of eventually using _PAGE_CACHE_UC over
_PAGE_CACHE_UC_MINUS on x86 on ioremap_nocache(), see:
From: Luis R. Rodriguez mcg...@suse.com
The driver doesn't use mtrr_add() or arch_phys_wc_add() but since we
know the framebuffer is isolated already on an ioremap() we can take
advantage of write combining for performance where possible.
In this case there are a few motivations for this:
a)
From: Luis R. Rodriguez mcg...@suse.com
Rename dma_*_writecombine() to dma_*_wc(), so that the naming
is coherent across the various write-combining APIs.
The following Coccinelle SmPL patch was used for this simple
transformation:
@ rename_dma_alloc_writecombine @
expression dev, size,
From: Luis R. Rodriguez mcg...@suse.com
Convert the driver from using the x86-specific MTRR code to the
architecture-agnostic arch_phys_wc_add(). It will avoid MTRR if
write-combining is available, in order to take advantage of that also
ensure the ioremapped area is requested as write-combining.
From: Luis R. Rodriguez mcg...@suse.com
dma_alloc_writecombine()'s call and return value check is tangled in all
in one call. Untangle both calls according to kernel coding style.
Signed-off-by: Luis R. Rodriguez mcg...@suse.com
Acked-by: Vinod Koul vinod.k...@intel.com
Cc: Vinod Koul
From: Luis R. Rodriguez mcg...@suse.com
This driver uses the same area for MTRR as for the ioremap().
Convert the driver from using the x86-specific MTRR code to the
architecture-agnostic arch_phys_wc_add(). It will avoid MTRRs if
write-combining is available. In order to take advantage of that
On Mon, 24 Aug 2015, Shenwei Wang wrote:
Signed-off-by: Shenwei Wang shenwei.w...@freescale.com
Signed-off-by: Anson Huang b20...@freescale.com
Ok, last question. How is Anson related to this? He did not convey
your patch and in the first posted versions his SOB was never there.
Thanks,
From: Luis R. Rodriguez mcg...@suse.com
The crusade to replace mtrr_add() with architecture agnostic
arch_phys_wc_add() is complete, this will ensure write-combining
implementations (PAT on x86) is taken advantage instead of using
MTRR. With the crusade done now, hide direct MTRR access for
From: Luis R. Rodriguez mcg...@suse.com
This driver uses the same area for MTRR as for the ioremap().
Convert the driver from using the x86-specific MTRR code to the
architecture-agnostic arch_phys_wc_add(). It will avoid MTRRs if
write-combining is available. In order to take advantage of that
Hi
On Thu, 20 Aug 2015 14:15:13 +0800
Changsheng Liu liuchangsh...@inspur.com wrote:
Hi Andrew Morton:
First, thanks very much for your review, I will update codes according
to your suggestio
在 2015/8/20 7:50, Andrew Morton 写道:
On Wed, 19 Aug 2015 04:18:26 -0400 Changsheng Liu
From: Luis R. Rodriguez mcg...@suse.com
Convert the driver from using the x86-specific MTRR code to the
architecture-agnostic arch_phys_wc_add(). It will avoid MTRRs if
write-combining is available. In order to take advantage of that also
ensure the ioremapped area is requested as
From: Luis R. Rodriguez mcg...@suse.com
Convert the driver from using the x86-specific MTRR code to the
architecture-agnostic arch_phys_wc_add(). It will avoid MTRR if
write-combining is available, in order to take advantage of that
also ensure the ioremapped area is requested as write-combining.
On Mon, 2015-08-24 at 13:04 -0400, Tejun Heo wrote:
Hello, Austin.
On Mon, Aug 24, 2015 at 11:47:02AM -0400, Austin S Hemmelgarn wrote:
Just to learn more, what sort of hypervisor support threads are we
talking about? They would have to consume considerable amount of cpu
cycles for
From: Luis R. Rodriguez mcg...@suse.com
PCI BARs tell us whether prefetching is safe, but they don't say
anything about write combining (WC). WC changes ordering rules and
allows writes to be collapsed, so it's not safe in general to use it on
a prefetchable region.
Add pci_iomap_wc() and
Hi Alexander,
Today's linux-next merge of the kvm-ppc tree got a conflict in:
arch/powerpc/kvm/book3s_hv.c
between commit:
c56dadf39761 (sched/preempt, powerpc, kvm: Use need_resched() instead of
should_resched())
from the tip tree and commit:
ec2571650826 (KVM: PPC: Book3S HV: Make
Driver will now supports enable/disable across msg xfer, which user
can control it by new DT property -
i2c-disable-after-xfer : If set, driver will disable I2C module after msg
xfer and enable it back before xfer.
Signed-off-by: Vaibhav Hiremath vaibhav.hirem...@linaro.org
---
Sorry for not following up on this aggressively, was quit busy with some
other stuff. Resending this patch with Robert's Tested-By.
This patch-series is subset of the original patch-series, submitted
on 14 Jul 2015.
Link to Original Patch-series - https://lkml.org/lkml/2015/7/14/80
The first
TWSI_ILCR TWSI_IWCR registers are used to adjust clock rate
of standard fast mode in pxa910/988; so this patch adds these two new
entries to struct pxa_reg_layout and struct pxa_i2c.
As discussed in the previous patch-series, the idea here is to add standard
DT properties for ilcr and iwcr
From: Yi Zhang yizh...@marvell.com
Enable i2c module/unit before transmission and disable when it
finishes.
why?
It's because the i2c bus may be disturbed if the slave device,
typically a touch, powers on.
As we do not want to break slave mode support, this patch introduces
DT property to
With addition of PXA910 family of devices, the TWSI module supports
new feature which allows us to adjust SCLK. i2c-pxa driver takes input
configuration in nsec and converts it to respective bit-fields,
- i2c-sclk-low-time-ns : SCLK low time (tlow)
This property is used along with mode
With addition of PXA910 family of devices, the TWSI module supports
SCL clock adjustment using ILCR register.
This patch enables the control and configuration of ICLR through DT
properties,
i2c-sclk-high-time-ns:
SCLK high time (tHigh), for standard/fast/high speed mode
i2c-sclk-low-time-ns:
Hi David joerg,
In iommu_context_addr() function, we always use lower extended-context-table
even though upper-half of the extended root-entry is present.
Signed-off-by: Nan Xiao nan.x...@hp.com
---
drivers/iommu/intel-iommu.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff
* Paul E. McKenney paul...@linux.vnet.ibm.com wrote:
here it's fully set - triggering the bug I'm worried about. So what am I
missing, what prevents CONFIG_NO_HZ_FULL_ALL from crashing?
The boot CPU is excluded from tick_nohz_full_mask in tick_nohz_init(), which
is
called from
On 08/21/2015 06:32 PM, Moritz Fischer wrote:
This patch adds 'interrupt-parent' properties to the instantation example in
the docs for the devicetree bindings of the Xilinx AXI DMA driver.
Signed-off-by: Moritz Fischer moritz.fisc...@ettus.com
---
On Tuesday 14 July 2015 12:27 AM, Vaibhav Hiremath wrote:
On Wednesday 08 July 2015 05:56 PM, Vaibhav Hiremath wrote:
This patch-series adds support for Device tree to 88PM800 mfd driver.
It also sets default configuration of irq clear method if board file
doesn't exist.
Testing::
- Boot
* Ingo Molnar mi...@kernel.org wrote:
* Denys Vlasenko dvlas...@redhat.com wrote:
I propose the table to be commented like shown below:
/*Opcode: d8 d9da db dc dd de df */
/*c0..f*/ fadd__, fld_i_, fcmovb, fcmovnb, fadd_i, ffree_, faddp_,
Hi Vinod,
On Thu, Aug 06, 2015 at 08:30:27AM +0530, Vinod Koul wrote:
On Thu, Aug 06, 2015 at 12:22:03PM +1000, Stephen Rothwell wrote:
Hi Vinod,
After merging the slave-dma tree, today's linux-next build (arm
multi_v7_defconfig) failed like this:
drivers/dma/at_hdmac.c: In
On Monday 20 July 2015 05:22 PM, Vaibhav Hiremath wrote:
Add chip identification support for 88PM860 device
to the pm80x_chip_mapping table.
Signed-off-by: Vaibhav Hiremath vaibhav.hirem...@linaro.org
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
drivers/mfd/88pm80x.c |
On 21/08/15 18:28, Arnaldo Carvalho de Melo wrote:
Em Fri, Aug 21, 2015 at 12:21:25PM -0300, Arnaldo Carvalho de Melo escreveu:
Em Fri, Aug 21, 2015 at 12:11:33PM -0300, Arnaldo Carvalho de Melo escreveu:
[acme@zoo ~]$ perf script -s
~/libexec/perf-core/scripts/python/export-to-postgresql.py
TPS77018DBVT is used to create 1.8V from avm_3v3_sw's 3.3V connected to
aic3106's DVDD.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts
The DVDD is supplied via TPS77018DBVT fixed regulator from evm_3v3
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
Signed-off-by: Darren Etheridge detheri...@ti.com
---
arch/arm/boot/dts/dra72-evm.dts | 9 +
1 file changed, 9 insertions(+)
diff --git
The board uses tlv320aic3106 codec connected to McASP3. The master clock
for the codec and McASP3 is coming from ATL2.
McASP3 is the master on the I2S bus.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 113 +
1
On Wed, Aug 19, 2015 at 08:51:17AM -0700, Liu.Zhao wrote:
This is intended to add ZTE device PIDs on kernel.
Signed-off-by: Liu.Zhao lzsos...@163.com
---
drivers/usb/serial/option.c | 36
1 file changed, 28 insertions(+), 8 deletions(-)
diff
The ABE related clocks should be configured via DT and not have it wired
inside of the kernel.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
Hi Tero,
the ABE PLL configuration can, and will be done for dra7xx in DT with the
assigned-clocks/rate/parent feature so no need to have this
* George Spelvin li...@horizon.com wrote:
First, an actual, albeit minor, bug: initializing both vmap_info_gen
and vmap_info_cache_gen to 0 marks the cache as valid, which it's not.
Ha! :-) Fixed.
vmap_info_gen should be initialized to 1 to force an initial
cache update.
Yeah.
Second, I
On 2015. 8. 24., at AM 9:43, Krzysztof Kozlowski k.kozlow...@samsung.com
wrote:
2015-08-24 8:23 GMT+09:00 Rob Herring robherri...@gmail.com:
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang y...@rock-chips.com wrote:
Analogix dp driver is split from exynos dp driver, so we just
make an copy of
On 19/08/2015 at 15:23:22 +0530, Suneel Garapati wrote :
adds support for RTC controller found on
Xilinx Zynq Ultrascale+ MPSoC platform.
Signed-off-by: Suneel Garapati suneel.garap...@xilinx.com
---
Changes v3
- fix checkpatch errors
- check time in secs arg against max sec val
-
* Mike Galbraith umgwanakikb...@gmail.com wrote:
On Mon, 2015-08-24 at 08:44 +0200, Ingo Molnar wrote:
the 'housekeeping CPU' is essentially the boot CPU. Yet we dedicate a full
mask to
it (housekeeping_mask - a variable mask to begin with) and recover the
housekeeping CPU via:
* Ingo Molnar mi...@kernel.org wrote:
One more detail: I just realized that with the read barriers, the READ_ONCE()
accesses are not needed anymore - the barriers and the control dependencies
are
enough.
This will further simplify the code.
I.e. something like the updated patch below.
On 08/21/2015 04:39 PM, Yingjoe Chen wrote:
[ ... ]
- Does the spurious interrupt occurs *every* time ? at each boot ?
Yes. If you applied this series to enable mtk timer without this fix on
mt8173 or mt8135 you can reproduce it. It occurs for every boot.
It crash before uart driver is
On Mon, 2015-08-24 at 09:41 +0200, Ingo Molnar wrote:
* Mike Galbraith umgwanakikb...@gmail.com wrote:
On Mon, 2015-08-24 at 08:44 +0200, Ingo Molnar wrote:
the 'housekeeping CPU' is essentially the boot CPU. Yet we dedicate a
full mask to
it (housekeeping_mask - a variable mask
On Mon, Aug 24, 2015 at 10:13:25AM +0300, Artem Bityutskiy wrote:
1. we are the only FS erroring out on O_DIRECT
2. other file-systems not supporting direct IO just fake it
There are lots of file systems not supporting O_DIRECT, but ubifs might
be the most common one. Given that O_DIRECT
* Mike Galbraith umgwanakikb...@gmail.com wrote:
On Mon, 2015-08-24 at 09:41 +0200, Ingo Molnar wrote:
* Mike Galbraith umgwanakikb...@gmail.com wrote:
On Mon, 2015-08-24 at 08:44 +0200, Ingo Molnar wrote:
the 'housekeeping CPU' is essentially the boot CPU. Yet we dedicate a
Add SROM controller device node for exynos5.
CC: Rob Herring robh...@kernel.org
CC: Mark Rutland mark.rutl...@arm.com
CC: Ian Campbell ijc+devicet...@hellion.org.uk
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
---
arch/arm/boot/dts/exynos5.dtsi | 5 +
1 file changed, 5 insertions(+)
This patch adds exynos-srom binding information for SROM Controller
driver on Exynos SoCs.
CC: Rob Herring robh...@kernel.org
CC: Mark Rutland mark.rutl...@arm.com
CC: Ian Campbell ijc+devicet...@hellion.org.uk
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
---
On 24/08/2015 at 09:48:42 +0200, Michal Simek wrote :
On 08/24/2015 09:43 AM, Alexandre Belloni wrote:
On 19/08/2015 at 15:23:22 +0530, Suneel Garapati wrote :
adds support for RTC controller found on
Xilinx Zynq Ultrascale+ MPSoC platform.
Signed-off-by: Suneel Garapati
On Mon, Aug 24, 2015 at 03:17:10PM +0800, Dongsheng Yang wrote:
Richard, you mention this was suggested by Dave, could you please pint
to the discussion, if possible?
http://lists.infradead.org/pipermail/linux-mtd/2015-August/060702.html
That's in a discussion I want to introduce ubifs
On 08/24/2015 04:03 PM, Christoph Hellwig wrote:
On Mon, Aug 24, 2015 at 11:02:42AM +0300, Artem Bityutskiy wrote:
Back when we were writing UBIFS, we did not need direct IO, so we did
not implement it. But yes, probably someone who cares could just try
implementing this feature.
So I think
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