On 07/21/2016 04:29 PM, Roger Pau Monné wrote:
> On Fri, Jul 15, 2016 at 05:31:48PM +0800, Bob Liu wrote:
>> blk_mq_update_nr_hw_queues() reset all queue limits to default which it's not
>> as xen-blkfront expected, introducing blkif_set_queue_limits() to reset
>> limits
>> with initial correct v
On Thu, Jul 21, 2016 at 12:33:12PM +0300, Peter Ujfalusi wrote:
> On 07/20/16 09:26, Robert Jarzmik wrote:
> > Speaking of which, from a purely design point of view, as long as you think
> > beforehand what is your sequence, ie. what is the sequence of your link
> > chaining, completion handling, e
The new DWC PCIe Core version (4.80) implements iATU in a different way.
This new mechanism is called iATU Unroll Mode. The Core still supports
the "old" mechanism calling it Legacy Mode if configured to do so, but
the standard way will be using Unroll.
This patch adds the necessary support for the
As documented in the comment gdb looks for debug files not only relative
to the binary's directory, but also in .debug and /usr/lib/debug/.
Let perf do the same thing.
Signed-off-by: Uwe Kleine-König
---
tools/perf/util/dso.c | 49 +++--
1 file changed
This patch adds the support to the new iATU mechanism that will be used
from Core version 4.80, which is called iATU Unroll.
The new Cores can support the iATU Unroll or support the "old" iATU
method now called Legacy Mode. The driver is perfectly capable of
performing well for both.
In order to
On Fri, Jul 15, 2016 at 12:38:54PM +0200, Ondřej Jirman wrote:
> On 15.7.2016 10:53, Maxime Ripard wrote:
> > On Fri, Jul 01, 2016 at 02:50:57AM +0200, Ondřej Jirman wrote:
> /**
> + * sun8i_h3_apply_pll1_factors() - applies n, k, m, p factors to the
> + * register using an algorith
perf probe makes use of debug symbols, so add --symfs as the other
commands have.
Signed-off-by: Uwe Kleine-König
---
tools/perf/builtin-probe.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tools/perf/builtin-probe.c b/tools/perf/builtin-probe.c
index ee5b42173ba3..f82d9b453366 100644
-
On Thu, Jul 21, 2016 at 10:10:35AM +0200, Jiri Olsa wrote:
> On Mon, Jul 18, 2016 at 04:00:45PM +0100, Mark Rutland wrote:
> > On Mon, Jul 18, 2016 at 04:30:18PM +0200, Jiri Olsa wrote:
> > > On Fri, Jul 15, 2016 at 11:08:13AM +0100, Mark Rutland wrote:
> > > > For system PMUs, the perf tools have
The Core version information is available since version 4.70.
This patch adds to the driver the register and default value for new core
4.80 if needed in some future work.
Signed-off-by: Joao Pinto
---
drivers/pci/host/pcie-designware.c | 4
1 file changed, 4 insertions(+)
diff --git a/dri
On Fri, Jul 15, 2016 at 03:27:56PM +0200, Jean-Francois Moine wrote:
> On Fri, 15 Jul 2016 12:38:54 +0200
> Ondřej Jirman wrote:
>
> > > If so, then yes, trying to switch to the 24MHz oscillator before
> > > applying the factors, and then switching back when the PLL is stable
> > > would be a nic
On 21.7.2016 11:48, Maxime Ripard wrote:
> On Fri, Jul 15, 2016 at 12:38:54PM +0200, Ondřej Jirman wrote:
>> On 15.7.2016 10:53, Maxime Ripard wrote:
>>> On Fri, Jul 01, 2016 at 02:50:57AM +0200, Ondřej Jirman wrote:
>> /**
>> + * sun8i_h3_apply_pll1_factors() - applies n, k, m, p factor
Hi Philipp,
2016-07-21 17:41 GMT+09:00 Philipp Zabel :
> Hi Masahiro,
>
> Am Donnerstag, den 21.07.2016, 14:05 +0900 schrieb Masahiro Yamada:
>> The recent update in the reset subsystem requires all reset consumers
>> to be explicit about the requested reset lines; _explicit or _shared.
>> This e
This patch moves the wakeup_process() invocation so it is not done under
the perm->lock by making use of a lockless wake_q. With this change, the
waiter is woken up once the message has been assigned and it does not
need to loop on SMP if the message points to NULL. In the signal case we
still need
On 07/21/2016 04:57 PM, Roger Pau Monné wrote:
> On Fri, Jul 15, 2016 at 05:31:49PM +0800, Bob Liu wrote:
>> The current VBD layer reserves buffer space for each attached device based on
>> three statically configured settings which are read at boot time.
>> * max_indirect_segs: Maximum amount of
Hi Jisheng,
On 7/18/2016 3:38 AM, Jisheng Zhang wrote:
> Dear Joao,
>
> On Fri, 15 Jul 2016 16:10:24 +0100 Joao Pinto wrote:
>
>> Hi,
>>
>> On 7/6/2016 11:59 AM, Jisheng Zhang wrote:
>>> The link may be UP but still in link training. In this case, we can't
>>> think the link is up and operating
In smp_prepare_boot_cpu(), we invoke cpuinfo_store_boot_cpu to store
the cpuinfo in a per-cpu ptr, before initialising the per-cpu offset for
the boot CPU. This patch reorders the sequence to make sure we initialise
the per-cpu offset before accessing the per-cpu area.
Commit 4b998ff1885eec ("arm
On 27/06/16 20:39, Douglas Anderson wrote:
> This reverts commit 4ac0d5f245e1 ("mmc: sdhci-of-arasan: Always power
> the PHY off/on when clock changes"), resolving conflicts with other
> patches that have come after. It appears that on some boards / with
> some eMMC devices that the patch is causi
From: Aihua Zhang
after patch:
[root@localhost bin]# ./inotify04
inotify041 TPASS : got event: wd=1 mask=400 cookie=0 len=0 name=""
inotify042 TPASS : got event: wd=1 mask=8000 cookie=0 len=0 name=""
inotify043 TPASS : got event: wd=2 mask=4 cookie=0 len=0 name=""
inotify04
Passing "nosmp" should boot the kernel with a single processor, without
provision to enable secondary CPUs even if they are present. "nosmp" is
implemented by setting maxcpus=0. At the moment we still mark the secondary
CPUs present even with nosmp, which allows the userspace to bring them
up. This
Hi Heiko,
On 2016/7/21 17:26, Heiko Stübner wrote:
Hi Frank,
Am Donnerstag, 21. Juli 2016, 10:49:53 schrieb Frank Wang:
@@ -69,6 +69,15 @@
regulator-max-microvolt = <330>;
};
+ vbus_host: vbus-host-regulator {
+ compatible = "re
On Thu, Jul 21, 2016 at 10:41:28AM +0100, Russell King - ARM Linux wrote:
> On Thu, Jul 21, 2016 at 05:20:12PM +0800, Peter Chen wrote:
> > On Thu, Jul 21, 2016 at 10:14:38AM +0100, Russell King - ARM Linux wrote:
> > > On Wed, Jul 20, 2016 at 05:40:28PM +0800, Peter Chen wrote:
> > > > diff --git
Hi Andi,
On Thu, Jul 21, 2016 at 10:09:26AM +0900, Andi Shyti wrote:
> > > + ret = regulator_enable(idata->regulator);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + mutex_lock(&idata->mutex);
> > > + idata->xfer.len = n;
> > > + idata->xfer.tx_buf = buffer;
> > > + mutex_unlock(&ida
* Davidlohr Bueso | 2016-07-20 17:16:12 [-0700]:
>Just as with expunge_all and the E2BIG case, could you remove that explicit
>barrier (B) and just rely on wake_q_add?
Just did. So we have just a smp_rmb() on the reader side and the
comment talks about smb_wmb() and at the spot where we should ha
Quoting Scott Wood (2016-07-21 04:31:48)
> On Wed, 2016-07-20 at 13:24 +0200, Arnd Bergmann wrote:
> > On Saturday, July 16, 2016 9:50:21 PM CEST Scott Wood wrote:
> > >
> > > From: yangbo lu
> > >
> > > Move mpc85xx.h to include/linux/fsl and rename it to svr.h as a common
> > > header file. T
Hi Sylwester,
On 2016년 07월 18일 19:41, Sylwester Nawrocki wrote:
> Hi Chanwoo,
>
> On 07/15/2016 07:18 AM, Chanwoo Choi wrote:
>>> +static int tm2_probe(struct platform_device *pdev)
>>> +{
>>> + struct device *dev = &pdev->dev;
>
>>> + codec_dai_node = of_parse_phandle(dev->of_node, "audio-c
On Wed, Jul 20, 2016 at 3:12 AM, Maxim Patlasov wrote:
> fuse_flush() calls write_inode_now() that triggers writeback, but actual
> writeback will happen later, on fuse_sync_writes(). If an error happens,
> fuse_writepage_end() will set error bit in mapping->flags. So, we have to
> check mapping->
On Thu, Jul 21, 2016 at 11:12:55AM +0100, Suzuki K Poulose wrote:
> In smp_prepare_boot_cpu(), we invoke cpuinfo_store_boot_cpu to store
> the cpuinfo in a per-cpu ptr, before initialising the per-cpu offset for
> the boot CPU. This patch reorders the sequence to make sure we initialise
> the per-
On Thu, Jul 21, 2016 at 12:19 PM, wrote:
> From: Aihua Zhang
>
> after patch:
> [root@localhost bin]# ./inotify04
> inotify041 TPASS : got event: wd=1 mask=400 cookie=0 len=0 name=""
> inotify042 TPASS : got event: wd=1 mask=8000 cookie=0 len=0 name=""
> inotify043 TPASS : g
There is no need to implement subroutine for suspend since there is no
data to store before suspending.
Signed-off-by: Grzegorz Jaszczyk
---
drivers/i2c/busses/i2c-mv64xxx.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2
On Thu, Jul 21, 2016 at 11:15:27AM +0100, Suzuki K Poulose wrote:
> Passing "nosmp" should boot the kernel with a single processor, without
> provision to enable secondary CPUs even if they are present. "nosmp" is
> implemented by setting maxcpus=0. At the moment we still mark the secondary
> CPUs
There is no need to implement subroutine for suspend since there is no
data to store before suspending.
Signed-off-by: Grzegorz Jaszczyk
---
drivers/thermal/armada_thermal.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/thermal/armada_thermal.c b/drivers/thermal/arm
And use it instead of opencoding in btrfs, f2fs and in fuse (coming up).
Signed-off-by: Miklos Szeredi
Cc: Chris Mason
Cc: Jaegeuk Kim
---
fs/btrfs/ctree.h| 1 -
fs/btrfs/inode.c| 15 ---
fs/btrfs/tree-log.c | 4 ++--
fs/f2fs/node.c | 7 ++-
include/linux/fs.h
On Thu, Jul 21, 2016 at 02:27:02PM +0800, Andy Green wrote:
> On July 21, 2016 1:22:02 PM GMT+08:00, John Stultz
> wrote:
> >On Wed, Jul 20, 2016 at 9:26 PM, zhangfei
Please fix your mail client to word wrap within paragraphs at something
substantially less than 80 columns. Doing this makes yo
Both SATA and second USB3.0 interface are supported in Armada-39x SoC
family. Add necessary clk description, so both xhci and sata drivers
can be correctly initialized.
The binding documentation has also been updated accordingly.
Signed-off-by: Grzegorz Jaszczyk
---
Documentation/devicetree/bin
The RTC core always calls rtc_valid_tm() after ->read_time() in case of
success (in __rtc_read_time()), so do not call it twice.
Signed-off-by: Benoît Thébaudeau
---
drivers/rtc/rtc-rv8803.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/rtc/rtc-rv8803.c b/drivers/rt
This driver supports the Epson RX8900, but this was not indicated in
Kconfig.
Signed-off-by: Benoît Thébaudeau
---
drivers/rtc/Kconfig | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 8526f1c..e215f50 100644
--- a/drivers/r
The Weekday register is encoded as 2^tm_wday, with tm_wday in 0..6, so
using tm_wday = ffs(reg) to fill tm_wday from the register value is
wrong because this gives the expected value + 1. This could be fixed as
tm_wday = ffs(reg) - 1, but tm_wday = ilog2(reg) works as well and is
more direct.
Sign
On 20/07/16 21:38, Mathieu Poirier wrote:
Up to now function coresight_build_path() was counting on a sink to
have been selected (from sysFS) prior to being called. This patch
adds a string argument so that a sink matching the argument can be
selected.
static int _coresight_build_path(struc
The I²C NACK issue of the RV-8803 may occur after any I²C START
condition, depending on the timings. Consequently, the workaround must
be applied for all the I²C transfers.
This commit abstracts the I²C transfer code into register access
functions. This avoids duplicating the I²C workaround everyw
According to the application manual of the RX8900, the RESET bit must be
set to 1 to prevent a timer update while setting the time. This also
resets the subsecond counter. The application manual of the RV-8803 does
not mention such a requirement, and it says that the 100th Seconds
register is clear
On Thu, Jul 21, 2016 at 01:00:51AM +0200, Daniel Borkmann wrote:
> On 07/20/2016 11:58 AM, Sargun Dhillon wrote:
> [...]
> >So, with that, what about the following:
> >It includes
> >-Desupporting no MMU platforms as we've deemed them incapable of being
> > safe
> >-Checking that we're not in a kt
V1F indicates that the time accuracy may have been compromised because
of a voltage drop (possibly only temporary) below VLOW1, which stops the
temperature compensation. When the time is set, the accuracy is
restored, so V1F should be cleared in order to indicate this and to be
able to detect the n
Dear Mark,
On Mon, 18 Jul 2016 19:05:08 +0100 Mark Brown wrote:
> On Mon, Jul 18, 2016 at 02:44:22PM +0800, Jisheng Zhang wrote:
>
> > v1 and v2 and both valid voltages, but here we have an explicit limitation:
> > we must take the "regulator shared" fact into consideration. Let's assume
> > the
On Friday, July 15, 2016 5:44:50 PM CEST Wan ZongShun wrote:
> 2016-07-15 15:00 GMT+08:00 Arnd Bergmann :
> > On Friday, July 15, 2016 1:15:58 PM CEST Wan Zongshun wrote:
> >>
> >> Actually, I have two choice to implement this function:
> >>
> >> option1:
> >>
> >> void __exception_irq_entry aic_ha
On Saturday, July 9, 2016 11:25:19 AM CEST Wan Zongshun wrote:
> On 2016年06月29日 23:27, Arnd Bergmann wrote:
> > On Saturday, June 25, 2016 6:37:20 PM CEST Wan Zongshun wrote:
> >> +#define IRQ_WDT W90X900_IRQ(1)
> >> +#define IRQ_WWDTW90X900_IRQ(2)
> >> +#define IRQ_LVD
On Monday, July 11, 2016 10:13:54 AM CEST Wan Zongshun wrote:
>
> On 2016年07月11日 06:17, Arnd Bergmann wrote:
> > On Sunday, July 10, 2016 3:42:21 PM CEST Wan Zongshun wrote:
> >> +
> >> +Required properties:
> >> +- compatible : Should be "nuvoton,nuc970-tmr"
> >> +- reg : Address and length of th
Am 2016-07-20 um 23:29 schrieb Dmitry Torokhov:
> On Mon, Jul 18, 2016 at 04:29:07PM +0200, Martin Kepplinger wrote:
>> Signed-off-by: Martin Kepplinger
>> ---
>> drivers/input/tablet/pegasus_notetaker.c | 19 +++
>> 1 file changed, 11 insertions(+), 8 deletions(-)
>>
>> diff --gi
Am 2016-07-20 um 23:06 schrieb Dmitry Torokhov:
> Hi Martin,
>
> On Mon, Jul 18, 2016 at 04:29:06PM +0200, Martin Kepplinger wrote:
>> Signed-off-by: Martin Kepplinger
>> ---
>> drivers/input/tablet/pegasus_notetaker.c | 26 ++
>> 1 file changed, 18 insertions(+), 8 delet
The patch
ASoC: cs53l30: Fix a bug for TDM slot location validation
has been applied to the asoc tree at
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) a
The patch
ASoC: cs53l30: Fix bit shift issue of TDM mode
has been applied to the asoc tree at
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to
This patch restrict the usage of extcon_update_state() in the extcon
core because the extcon_update_state() use the bit masking to change
the state of external connector. When this function is used in device drivers,
it may occur the probelm with the handling mistake of bit masking.
Also, this pat
This patch removes the usage of extcon_set_state() because it uses
the bit masking to change the state of external connectors. The extcon framework
should handle the state by extcon_set_cable_state_() with extcon id.
Signed-off-by: Chanwoo Choi
---
drivers/extcon/extcon-gpio.c | 2 +-
1 file cha
This patch removes the usage of extcon_set_state() because it uses the bit
masking to change the state of external connectors. The extcon framework
should handle the state by extcon_set/get_cable_state_() with extcon id.
Signed-off-by: Chanwoo Choi
---
drivers/extcon/extcon-adc-jack.c | 26
On 21/07/2016 at 12:41:30 +0200, Benoît Thébaudeau wrote :
> The I²C NACK issue of the RV-8803 may occur after any I²C START
> condition, depending on the timings. Consequently, the workaround must
> be applied for all the I²C transfers.
>
> This commit abstracts the I²C transfer code into registe
This patchset blocks the usgae of extcon_get/get_update_state()
except for extcon core. Instead, extcon framework provide the
other APIs with unique extcon id as following:
- extcon_set_cable_state_()
- extcon_get_cable_state_()
Changes from v1:
- Add patch3 to remove the usage of extcon_set_state
This patch remvoes the usage of extcon_update_state() because
the extcon_update_state() use directly the bit masking calculation
to change the state of external connector without the unique id of
external connector. It makes the code diffcult to read it.
So, this patch uses the extcon_set_cable_sta
This patch removes the state_store() which change the state of external
connectors with bit masking on user-space. It is wrong access to modify
the change the state of external connectors.
Signed-off-by: Chanwoo Choi
---
drivers/extcon/extcon.c | 21 +
1 file changed, 1 inser
On 20/07/16 21:11, Masami Hiramatsu wrote:
> On Wed, 20 Jul 2016 11:30:33 +0300
> Adrian Hunter wrote:
>
>> Hi
>>
>> Here are patches to add support for Intel's AVX-512 instructions to the
>> instruction decoder. Also there is a patch to fix vcvtph2ps.
>>
>> AVX-512 instructions are documented i
pmbus/dps400: disable PMBus status check through platform data structure to
provide support for PSU DPS-460, DPS-800 from Delta Electronics, INC and for
SGD009 from Acbel Polytech, INC.
These devices do not support the STATUS_CML register, and reports communication
error in response to this command
On 07/21/2016 12:47 PM, Sargun Dhillon wrote:
On Thu, Jul 21, 2016 at 01:00:51AM +0200, Daniel Borkmann wrote:
[...]
I don't really like couple of things, your ifdef CONFIG_MMU might not be
needed I think, couple of these checks seem redundant, (I'm not yet sure
about the task->mm != task->acti
When bl_parse_deviceid() fails in bl_alloc_deviceid_node() on
blkdev_get_by_*() step we get an pnfs_block_dev struct that is
uninitialized except for bdev field which is set to whatever error
blkdev_get_by_*() returns. bl_free_device() then tries to call
blkdev_put() if bdev is not 0 resulting in
Hi Rob,
On 20/07/16 13:56, Rob Herring wrote:
> On Tue, Jul 19, 2016 at 01:40:41PM +0100, Juri Lelli wrote:
> > ARM systems may be configured to have cpus with different power/performance
> > characteristics within the same chip. In this case, additional information
> > has to be made available to
On Wed, 20 Jul 2016, John Stultz wrote:
> On Tue, Jul 19, 2016 at 11:12 PM, James Morris wrote:
> > On Mon, 18 Jul 2016, John Stultz wrote:
> >
> >> As requested, this patch implements a task_settimerslack and
> >> task_gettimerslack LSM hooks so that the /proc//timerslack_ns
> >> interface can h
Hello,
On Thu, 21 Jul 2016 12:48:10 +0200, Grzegorz Jaszczyk wrote:
> Both SATA and second USB3.0 interface are supported in Armada-39x SoC
> family. Add necessary clk description, so both xhci and sata drivers
> can be correctly initialized.
>
> The binding documentation has also been updated ac
This series adds patches to support 2 PCIe ports simultaneously
on dra7 based boards.
None of the supported boards exposes 2 PCIe ports. However these are
mandatory changes that would be required in order to support
2 PCIe ports.
This series has been tested to see if there are regressions with 1
P
PCI_DOMAINS is required for DRA7x SoCs since there are 2 PCIe
controllers and without PCI_DOMAINS config, only one PCIe
controller gets registered.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/mach-omap2/Kconfig |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-omap2/Kco
Since DRA7 has multiple PCIe Rootcomplex, add "linux,pci-domain"
property to assign a PCI domain number to each of the host
bridges.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/dra7.dtsi |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/a
On 24/06/16 18:07, Georgi Djakov wrote:
> Enabling support for ultra high speed mode cards requires some
> voltage switching and interaction with the PMIC via a special
> power IRQ. Add support for this.
>
> Signed-off-by: Georgi Djakov
Acked-by: Adrian Hunter
> ---
> drivers/mmc/host/sdhci
On Thu, 21 Jul 2016, Masahiro Yamada wrote:
> 2016-07-21 17:41 GMT+09:00 Philipp Zabel :
> > Am Donnerstag, den 21.07.2016, 14:05 +0900 schrieb Masahiro Yamada:
> >> The recent update in the reset subsystem requires all reset consumers
> >> to be explicit about the requested reset lines; _explicit
On Thursday, July 21, 2016 5:27:56 PM CEST Kishon Vijay Abraham I wrote:
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index 1a648e9..8e6e2c0 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -86,6 +86,7 @@ config SOC_DRA7XX
> s
We check IS_DAX(inode) before calling either xfs_file_dax_read or
xfs_file_dax_write, and this will lead the call being optimized out at
compile time when CONFIG_FS_DAX is disabled.
However, the two functions are marked STATIC, so they become global
symbols when CONFIG_XFS_DEBUG is set, leaving us
On Wed, 20 Jul 2016, Sylwester Nawrocki wrote:
> On 07/05/2016 07:13 PM, Sylwester Nawrocki wrote:
> > This patch adds common driver for the Top block of the Samsung Exynos
> > SoC Low Power Audio Subsystem. This is a minimal driver which prepares
> > resources for IP blocks like I2S, audio DMA an
On Wed, 20 Jul 2016, Jonathan Cameron wrote:
> On 19/07/16 08:31, Lee Jones wrote:
> > On Mon, 18 Jul 2016, Jonathan Cameron wrote:
> >
> >> On 15/07/16 10:59, Quentin Schulz wrote:
> >>> The Allwinner SoCs all have an ADC that can also act as a touchscreen
> >>> controller and a thermal sensor.
On Thu, Jul 21, 2016 at 10:52:03AM +0200, Michal Hocko wrote:
> Look, there are
> $ git grep mempool_alloc | wc -l
> 304
>
> many users of this API and we do not want to flip the default behavior
> which is there for more than 10 years. So far you have been arguing
> about potential deadlocks and
Thanks Arnd,
this looks fine:
Reviewed-by: Christoph Hellwig
On 20/07/2016 16:57, Jonathan Cameron wrote:
> On 19/07/16 09:33, Quentin Schulz wrote:
>> On 18/07/2016 15:18, Jonathan Cameron wrote:
>>> On 15/07/16 10:59, Quentin Schulz wrote:
[...]
+ enable_irq(info->temp_data_irq);
>>> Is this hardware spitting out extra irqs? If not, much better to j
On Tue, Jul 19, 2016 at 03:05:56AM -0700, Joe Perches wrote:
> On Tue, 2016-07-19 at 10:51 +0100, Andy Whitcroft wrote:
> > On Mon, Jul 18, 2016 at 12:27:42PM -0700, Joe Perches wrote:
> > >
> > > Using \b isn't good enough to isolate what appears to be a
> > > commit id in a commit message.
> > >
On 21 Jul 2016, at 7:32, Artem Savkov wrote:
When bl_parse_deviceid() fails in bl_alloc_deviceid_node() on
blkdev_get_by_*() step we get an pnfs_block_dev struct that is
uninitialized except for bdev field which is set to whatever error
blkdev_get_by_*() returns. bl_free_device() then tries to
On Monday, July 18, 2016 11:58:02 AM CEST Thierry Reding wrote:
> On Mon, Jul 18, 2016 at 11:46:48AM +0200, Ralf Ramsauer wrote:
> > c90bb7b enabled the high speed UARTs of the Jetson TK1. Due to a merge
> > quirk, wrong addresses were introduced. Fix it and use the correct
> > addresses.
> >
> >
On July 21, 2016 2:11:32 AM PDT, Ingo Molnar wrote:
>
>* H. Peter Anvin wrote:
>
>> We already reserve the first megabyte by default. There is something
>really
>> bizarre about this; the bug report simply doesn't seem to make any
>sense.
>
>Maybe the first megabyte reservation happens after th
On 21/07/2016 at 13:10, Alexandre Belloni wrote:
> On 21/07/2016 at 12:41:30 +0200, Benoît Thébaudeau wrote :
>> The I²C NACK issue of the RV-8803 may occur after any I²C START
>> condition, depending on the timings. Consequently, the workaround must
>> be applied for all the I²C transfers.
>>
>> T
On 07/21/2016 02:28 PM, Arnd Bergmann wrote:
> On Monday, July 18, 2016 11:58:02 AM CEST Thierry Reding wrote:
>> On Mon, Jul 18, 2016 at 11:46:48AM +0200, Ralf Ramsauer wrote:
>>> c90bb7b enabled the high speed UARTs of the Jetson TK1. Due to a merge
>>> quirk, wrong addresses were introduced. F
Em Thu, Jul 21, 2016 at 02:18:34PM +0300, Adrian Hunter escreveu:
> On 20/07/16 21:11, Masami Hiramatsu wrote:
> > On Wed, 20 Jul 2016 11:30:33 +0300
> > Adrian Hunter wrote:
> >> Here are patches to add support for Intel's AVX-512 instructions to the
> >> instruction decoder. Also there is a pat
Signed-off-by: Grzegorz Jaszczyk
---
arch/arm/boot/dts/armada-385-db-ap.dts | 26 +++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts
b/arch/arm/boot/dts/armada-385-db-ap.dts
index a18f516..6648a3f 100644
--- a/arch/arm
Signed-off-by: Grzegorz Jaszczyk
---
arch/arm/boot/dts/armada-385-db-ap.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts
b/arch/arm/boot/dts/armada-385-db-ap.dts
index 2d3fd6e..a18f516 100644
--- a/arch/arm/boot/dts/armada-385-db-ap.dts
+++ b/arc
Signed-off-by: Grzegorz Jaszczyk
Reviewed-by: Lior Amsalem
---
arch/arm/boot/dts/armada-39x.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/armada-39x.dtsi
b/arch/arm/boot/dts/armada-39x.dtsi
index 03dc0ec..5e01438 100644
--- a/arch/arm/boot/dts/armad
First 3 patches enables some commonly used features in mvebu_v7_defconfig.
Patches 4 and 5 updates armada-385-db-ap.dts. Then patch 6 is currently a fix
for broken Armada 390 dtsi.
Patches 7 to 13 updates the armada-39x.dtsi about features which all can be
supported with existing drivers.
Patch
The whole Armada 39x SoC family of processors has GPIO's which all can be
supported with existing driver.
Signed-off-by: Grzegorz Jaszczyk
---
arch/arm/boot/dts/armada-39x.dtsi | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/armada-39x.dtsi
The whole Armada 39x SoC family of processors has one USB2.0 and one
USB3.0 which all can be supported with existing drivers.
Signed-off-by: Grzegorz Jaszczyk
---
arch/arm/boot/dts/armada-39x.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/armada-39x.
Beside interfaces described in the armada-39x.dtsi, the Armada 395 SoC
family supports: 2 x SATA3 (2 ports in one unit) and the USB3.0
Signed-off-by: Grzegorz Jaszczyk
---
.../devicetree/bindings/arm/marvell/armada-39x.txt | 2 +-
arch/arm/boot/dts/armada-395.dtsi | 76
Despite that FS states that rtc is present only in A395 and A398 and not in
A390, the rtc is working with A390.
Signed-off-by: Grzegorz Jaszczyk
---
arch/arm/boot/dts/armada-39x.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/armada-39x.dtsi
b/arch/arm/boot/dts
Hi Vladimir,
Sorry for getting to this only now.
On Mon, Jun 27, 2016 at 07:39:54PM +0300, Vladimir Davydov wrote:
> When selecting an oom victim, we use the same heuristic for both memory
> cgroup and global oom. The only difference is the scope of tasks to
> select the victim from. So we could
Signed-off-by: Grzegorz Jaszczyk
---
arch/arm/boot/dts/armada-398-db.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/armada-398-db.dts
b/arch/arm/boot/dts/armada-398-db.dts
index 788c3ba..969b49f 100644
--- a/arch/arm/boot/dts/armada-398-db.dts
+++ b/arch/arm/bo
This commit adds description for following features for this board:
- Serial port
- I2C buses
- 16MB SPI-NOR
- USB2.0
- USB3.0
- PCIe interfaces
Signed-off-by: Grzegorz Jaszczyk
---
arch/arm/boot/dts/armada-390-db.dts | 164
1 file changed, 164 insertions(+)
This commit adds description for the following features for this board:
- Serial port
- PCIe interfaces
- USB2.0
- USB3.0
- SDIO
- 1024 MiB NAND-FLASH
- SATA
- I2C buses
Signed-off-by: Grzegorz Jaszczyk
---
arch/arm/boot/dts/armada-395-gp.dts | 147
1 file c
Signed-off-by: Grzegorz Jaszczyk
---
arch/arm/boot/dts/armada-39x.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/armada-39x.dtsi
b/arch/arm/boot/dts/armada-39x.dtsi
index 8a22c02..03dc0ec 100644
--- a/arch/arm/boot/dts/armada-39x.dtsi
+++ b/arch/arm/boot/dts/arm
Hi, Joseph
On 2016/7/20 23:47, Joseph Myers wrote:
On Wed, 6 Jul 2016, Zhangjian (Bamvor) wrote:
correct or not. After learn and compare some fuzz tools, I feel that there is
no such fuzz tools could help me. So, I wrote a new fuzz tools base on the
trinity and it found several wrapper issues
Beside interfaces described in the armada-39x.dtsi and armada-395.dtsi, the
Armada 398 SoC family supports 2 additional SATA port (2 ports in one unit)
Signed-off-by: Grzegorz Jaszczyk
---
arch/arm/boot/dts/armada-398.dtsi | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --g
On Wed, Jul 20, 2016 at 02:18:02AM +0800, fu@linaro.org wrote:
> From: Fu Wei
>
> This driver adds support for parsing memory-mapped timer in GTDT:
> provide a kernel APIs to parse GT Block Structure in GTDT,
> export all the info by filling the struct which provided
> by parameter(pointer of
Commit 1140011ee9d9 ("mmc: sdhci-pxav3: Modify clock settings
for the SDR50 and DDR50 modes") has extended the Device Tree
binding used to describe PXAv3 SDHCI controllers in order to be
able to use the SDR50 and DDR50 modes.
This commit updates the Device Tree description of the Armada
39x SDHCI
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