From: "Steven Rostedt (VMware)"
When running the likely/unlikely profiler, one of the results did not look
accurate. It noted that the unlikely() in link_path_walk() was 100%
incorrect. When I added a trace_printk() to see what was happening there, it
became 80% correct!
Hi Javier,
On 2017-01-18 01:30, Javier Martinez Canillas wrote:
Commit a006c04e6218 ("[media] exynos-gsc: Fixup clock management at
->remove()") changed the driver's .remove function logic to fist do
a pm_runtime_get_sync() to make sure the device is powered before
attempting to gate the gsc
Vivek,
On 19/01/17 13:56, Vivek Gautam wrote:
> Hi,
>
>
> On Wed, Jun 22, 2016 at 2:00 PM, Roger Quadros wrote:
>
> Luckily hit this thread while checking about DRD role functionality for DWC3.
>
>> On 22/06/16 11:14, Felipe Balbi wrote:
>>>
>>> Hi,
>>>
>>> Roger Quadros
Hello Marek,
On 01/19/2017 11:12 AM, Marek Szyprowski wrote:
> Hi Javier,
>
> On 2017-01-18 01:30, Javier Martinez Canillas wrote:
>> Commit a006c04e6218 ("[media] exynos-gsc: Fixup clock management at
>> ->remove()") changed the driver's .remove function logic to fist do
>> a
Hi Neil,
On 18-01-2017 11:20, Neil Armstrong wrote:
>
> It's the idea we discussed with Laurent.
> Keeping the Synopsys PHY code inside the dw-hdmi driver would be simpler.
>
> But don't you think adding a proper "ops" structure apart from the plat_data
> should be necessary ?
>
> Neil
>
An
On 19/01/17 21:50, Greg Kurz wrote:
The kernel API does not use anything from this header file.
Signed-off-by: Greg Kurz
Reviewed-by: Andrew Donnellan
--
Andrew Donnellan OzLabs, ADL Canberra
andrew.donnel...@au1.ibm.com IBM
+Shawn
On 13 January 2017 at 06:29, Matt Ranostay wrote:
> Allow power sequencing for the Marvell SD8787 Wifi/BT chip.
> This can be abstracted to other chipsets if needed in the future.
>
> Cc: Tony Lindgren
> Cc: Ulf Hansson
On Fri, Jan 13, 2017 at 09:07:57PM +0100, Manuel Schölling wrote:
> Add a scrollback buffers for each VGA console. The benefit is that
> the scrollback history is not flushed when switching between consoles
> but is persistent.
> The buffers are allocated on demand when a new console is opened.
>
Hi,
On Wed, Jan 18, 2017 at 10:13:15PM +, Russell King - ARM Linux wrote:
> On Thu, Jan 19, 2017 at 02:08:37AM +0530, afzal mohammed wrote:
> > + MLK_ROUNDUP(vectors_base, vectors_base + PAGE_SIZE),
>
> I think MLK() will do here - no need to use the rounding-up version
>
This patch adds support for the STM32F4 I2C controller.
Signed-off-by: M'boumba Cedric Madianga
---
drivers/i2c/busses/Kconfig | 10 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-stm32f4.c | 897 +++
3
On Thu, 19 Jan 2017 08:55:07 +
Chris Wilson wrote:
> On Wed, Jan 18, 2017 at 03:58:24PM -0500, Steven Rostedt wrote:
> > Chris,
> >
> > My branch tracer flagged the unlikely in __mutex_lock_common() as
> > always hit. That's the:
> >
> > if (use_ww_ctx) {
> >
All platforms using this driver now register the SATA refclk. Remove
the hardcoded default value from the driver and instead read the rate
of the external clock and calculate the required MPY value from it.
Signed-off-by: Bartosz Golaszewski
---
Add the SATA node to the da850 device tree.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/boot/dts/da850.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 104155d..e9bf30e 100644
---
STM32 ADC can use dma. Add dt documentation for optional dma support.
Signed-off-by: Fabrice Gasnier
---
Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git
Configure STM32F4 ADC to use dma by default.
Signed-off-by: Fabrice Gasnier
---
arch/arm/boot/dts/stm32f429.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 11d2715..e85db07 100644
This patchset adds support for the I2C controller embedded in STM32F4xx SoC.
It enables I2C transfer in interrupt mode with Standard-mode and Fast-mode bus
speed.
Changes since v9:
- Fix minor typo in some comments
- Add some comments to explain how the driver check TRISE and CCR value have
no
Add optional DMA support to STM32 ADC.
Use dma cyclic mode with at least two periods.
Signed-off-by: Fabrice Gasnier
---
drivers/iio/adc/Kconfig | 2 +
drivers/iio/adc/stm32-adc-core.c | 1 +
drivers/iio/adc/stm32-adc-core.h | 2 +
The following patches add support for triggered buffer mode.
These are based on top of "Add PWM and IIO timer drivers for STM32"
series. Reference:
https://lkml.org/lkml/2017/1/18/588
STM32 ADC, can use either interrupts or DMA to collect data.
Either timer trigger output (TRGO) or PWM can be
STM32 ADC conversions can be launched using hardware triggers.
It can be used to start conversion sequences (group of channels).
Selected channels are select via sequence registers.
Trigger source is selected via 'extsel' (external trigger mux).
Trigger polarity is set to rising edge by default.
Define and enable pwm1 and pwm3, timers1 & 3 trigger outputs on
stm32f469-eval board.
Signed-off-by: Fabrice Gasnier
---
arch/arm/boot/dts/stm32429i-eval.dts | 28
1 file changed, 28 insertions(+)
diff --git
STM32 ADC has external timer trigger sources. Use stm32 timer triggers
API (e.g. is_stm32_timer_trigger()) with local ADC lookup table to
validate a trigger can be used.
This also provides correct trigger selection value (e.g. extsel).
Signed-off-by: Fabrice Gasnier
---
> -Original Message-
> From: Greg KH [mailto:gre...@linuxfoundation.org]
> Sent: Thursday, January 19, 2017 1:34 AM
> To: KY Srinivasan
> Cc: linux-kernel@vger.kernel.org; de...@linuxdriverproject.org;
> o...@aepfle.de; a...@canonical.com; vkuzn...@redhat.com;
>
On Thu, Jan 19, 2017 at 02:21:47PM +0100, Ingo Molnar wrote:
>
> * Greg Kroah-Hartman wrote:
>
> > On Thu, Jan 19, 2017 at 05:32:46AM -0500, Prarit Bhargava wrote:
> > >
> > >
> > > On 01/18/2017 05:25 PM, Ingo Molnar wrote:
> > > >
> > > > * Prarit Bhargava
This patch adds STM32 RTC bindings for STM32F746.
Signed-off-by: Amelie Delaunay
---
arch/arm/boot/dts/stm32f746.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index
The unikely() used in __mutex_lock_common() when use_ww_ctx is set is
currently dependent on the hardware if it is likely or unlikely. The
intel drm code calls into this function and triggers this branch 100%
of the time. As this hardware is very commonly used, this is not a rare
case at all (the
On 01/19/2017 02:35 AM, Greg KH wrote:
> On Fri, Jan 13, 2017 at 04:38:32PM -0700, Shuah Khan wrote:
>> Update USB/IP driver location in README.
>>
>> Signed-off-by: Shuah Khan
>> Reviewed-by: Krzysztof Opasiak
>> ---
>> tools/usb/usbip/README | 2
do_settimeofday() is deprecated, use do_settimeofday64() instead.
Signed-off-by: Vitaly Kuznetsov
Acked-by: John Stultz
Acked-by: Thomas Gleixner
---
drivers/hv/hv_util.c | 6 +++---
1 file changed, 3 insertions(+), 3
Hi Javier,
On 2017-01-18 01:30, Javier Martinez Canillas wrote:
Commit 15f90ab57acc ("[media] exynos-gsc: Make driver functional when
CONFIG_PM is unset") removed the implicit dependency that the driver
had with CONFIG_PM, since it relied on the config option to be enabled.
In order to work
On 19/01/17 11:40, Greg KH wrote:
Fixes: commit 237483aa5cf43 ("coresight: stm: adding driver for CoreSight STM
component")
Cc: Pratik Patel
Cc: Greg Kroah-Hartman
Cc: sta...@vger.kernel.org # 4.7+
Acked-by: Mathieu Poirier
With TimeSync version 4 protocol support we started updating system time
continuously through the whole lifetime of Hyper-V guests. Every 5 seconds
there is a time sample from the host which triggers do_settimeofday[64]().
While the time from the host is very accurate such adjustments may cause
With TimeSync version 4 protocol support we started updating system time
continuously through the whole lifetime of Hyper-V guests. Every 5 seconds
there is a time sample from the host which triggers do_settimeofday[64]().
While the time from the host is very accurate such adjustments may cause
On Thu, Jan 19, 2017 at 02:07:39AM +0530, afzal mohammed wrote:
> diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
> index 76cbd9c674df..9cc9f1dbc88e 100644
> --- a/arch/arm/include/asm/memory.h
> +++ b/arch/arm/include/asm/memory.h
> @@ -83,6 +83,8 @@
> #define
Sorry for the delay, I'm just trying to clear out some of our defects from
bugzilla and have gotten really behind on the list, so I just haven't
gotten to this yet.
On Wed, Jan 18, 2017 at 01:47:11PM -0500, Keith Busch wrote:
> Hi Bjorn,
>
> This fix looks good to me as well now. Any other
On Thu, Jan 19, 2017 at 12:31 AM, Kuninori Morimoto
wrote:
>
>
>
> Hi Rob
>
> Now many driver is getting remote-endpoint by manually,
> but we should use same method to get same result IMO.
> Thus this patch adds of_graph_get_remote_endpoint() for this purpose.
>
parse_cpu_capacity() has to return 0 on failure, but it currently returns
1 instead if raw_capacity kcalloc failed.
Fix it by removing the negation of the return value.
Cc: Russell King
Reported-by: Morten Rasmussen
Fixes: 06073ee26775 ('ARM:
Reference to cpu capacity binding has a wrong number. Fix it.
Reported-by: Lorenzo Pieralisi
Signed-off-by: Juri Lelli
---
Documentation/devicetree/bindings/arm/cpus.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
/sys/devices/system/cpu/cpu#/cpu_capacity describe information about
CPUs heterogeneity (ref. to Documentation/devicetree/bindings/arm/
cpu-capacity.txt).
Add such description.
Signed-off-by: Juri Lelli
---
Documentation/ABI/testing/sysfs-devices-system-cpu | 7 +++
1
arm and arm64 share lot of code relative to parsing CPU capacity
information from DT, using that information for appropriate scaling and
exposing a sysfs interface for chaging such values at runtime.
Factorize such code in a common place (driver/base/arch_topology.c) in
preparation for further
Reduce the scope of cap_parsing_failed (making it static in
drivers/base/arch_topology.c) by slightly changing {arm,arm64} DT
parsing code.
Suggested-by: Morten Rasmussen
Signed-off-by: Juri Lelli
---
arch/arm/kernel/topology.c | 3 +--
The sysfs cpu_capacity entry for each CPU has nothing to do with
PROC_FS, nor it's in /proc/sys path.
Remove such ifdef.
Cc: Will Deacon
Cc: Catalin Marinas
Reported-and-suggested-by: Sudeep Holla
Fixes: be8f185d8af4 ('arm64:
On Wed, Jan 11, 2017 at 04:31:57PM -0600, Andy Gross wrote:
> diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h
> index b5abfda..3e28d08 100644
> --- a/include/linux/arm-smccc.h
> +++ b/include/linux/arm-smccc.h
> @@ -72,19 +72,33 @@ struct arm_smccc_res {
> };
>
> /**
> - *
PCI fixes:
- recognize that a PCI-to-PCIe bridge originates a PCIe hierarchy, so we
enumerate that hierarchy correctly
- X-Gene: fix a change merged for v4.10 that broke MSI
- Keystone: avoid reading undefined registers, which can cause
asynchronous external aborts
- Supermicro
On Wed, Jan 18, 2017 at 04:09:32AM +0800, Chen-Yu Tsai wrote:
> Hi,
>
> On Wed, Jan 18, 2017 at 4:06 AM, Maxime Ripard
> wrote:
> > On Wed, Jan 18, 2017 at 12:57:08AM +0800, Icenowy Zheng wrote:
> >>
> >>
> >> 17.01.2017, 16:06, "Maxime Ripard"
Hello Marek,
Thanks a lot for your feedback.
On 01/19/2017 11:17 AM, Marek Szyprowski wrote:
> Hi Javier,
>
> On 2017-01-18 01:30, Javier Martinez Canillas wrote:
>> Commit 15f90ab57acc ("[media] exynos-gsc: Make driver functional when
>> CONFIG_PM is unset") removed the implicit dependency
> > > struct dsa_platform_data {
> > > /*
> > > * Reference to a Linux network interface that connects
> > > * to the root switch chip of the tree.
> > > */
> > > struct device *netdev;
>
> This I think is the oddest thing, why do you need to have the
On Thu, Jan 19, 2017 at 7:37 AM, Greg Kroah-Hartman
wrote:
> On Mon, Jan 16, 2017 at 04:54:29PM -0600, Rob Herring wrote:
>> From: Alan Cox
>>
>> Let us create tty objects entirely in kernel space. Untested proposal to
>> show why all the ideas
The ACCES 104-DIO-48E series provides registers where 8 lines of GPIO
may be set at a time. This patch add support for the set_multiple
callback function, thus allowing multiple GPIO output lines to be set
more efficiently in groups.
Signed-off-by: William Breathitt Gray
On Thursday, January 19, 2017 12:00:58 PM CET Thierry Reding wrote:
> On Thu, Jan 12, 2017 at 12:13:51PM +0100, Arnd Bergmann wrote:
> > The tegra DRM driver is almost ok without an MMU, but there
> > is one small warning that I get:
> >
> > drivers/gpu/drm/tegra/gem.c: In function
Since sem->count had been changed to a atomic_long_t type, it is no
longer necessary to use the atomic_long_t cast anymore. So they are
removed.
Signed-off-by: Waiman Long
---
include/asm-generic/rwsem.h | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
It is the time we have the real 16-bit Stream ID user, which is the
ThunderX. Its IO topology uses 1:1 map for Requester ID to Stream ID
translation for each root complex which allows to get full 16-bit
Stream ID. Firmware assigns bus IDs that are greater than 128 (0x80)
to some buses under PEM
The sysfs cpu_capacity entry for each CPU has nothing to do with
PROC_FS, nor it's in /proc/sys path.
Remove such ifdef.
Cc: Russell King
Reported-and-suggested-by: Sudeep Holla
Fixes: 7e5930aaef5d ('ARM: 8622/3: add sysfs cpu_capacity attribute')
Hi,
arm and arm64 topology.c share a lot of code related to parsing of capacity
information. This set of patches proposes a solution (based on Will's,
Catalin's and Mark's off-line suggestions) to move such common code in a single
place: drivers/base/arch_topology.c (by creating such file and
On Wed, Jan 18, 2017 at 10:53:30AM +, Marc Zyngier wrote:
> The joys of copy/paste: the example of a virtualization capable GIC
> in the DT binding was wrong, and propagated to dozens of platforms.
Could you please mention what's wrong (i.e. GICC is impossibly small in
the example).
>
> Oh
On Mon, Jan 16, 2017 at 12:01:02PM -0800, Florian Fainelli wrote:
> On 01/15/2017 11:16 AM, Andrew Lunn wrote:
> >>> What exactly is the relationship between these devices (a ascii-art tree
> >>> or sysfs tree output might be nice) so I can try to understand what is
> >>> going on here.
> >
> >
Hi,
altek/rtlwifi/rtl8192ce/hw.c
b/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c
> index a47be73..143766c4 100644
> --- a/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c
> +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c
> @@ -1306,9 +1306,9 @@ void
Without CONFIG_NET, we get a build failure for the new driver:
ERROR: "skb_queue_tail" [drivers/rpmsg/rpmsg_char.ko] undefined!
ERROR: "skb_put" [drivers/rpmsg/rpmsg_char.ko] undefined!
ERROR: "__alloc_skb" [drivers/rpmsg/rpmsg_char.ko] undefined!
ERROR: "kfree_skb" [drivers/rpmsg/rpmsg_char.ko]
* Greg Kroah-Hartman [170119 05:25]:
> On Fri, Jan 13, 2017 at 10:20:21AM -0800, Tony Lindgren wrote:
> > * Vignesh R [170113 00:03]:
> > > This patch series re enables DMA support for UART 8250_omap driver.
> > >
> > > Tested on AM335x, AM437x that
On 2017-01-19 19:43, Andy Gross wrote:
On Thu, Jan 19, 2017 at 10:31:50AM +0530, Vinod Koul wrote:
> > >
> > >I really think that we need some additional API that allows for the flag
> > >munging
> > >for the descriptors instead of overriding the prep_slave_sg. We already
> > >needed
> >
On Thu, Jan 19, 2017 at 02:34:39PM +0200, Andy Shevchenko wrote:
> On Wed, 2017-01-18 at 15:25 +0100, Clemens Gruber wrote:
> > Yes, that's what this patch tries to solve by verifying that the
> > external setting (the prescale register) is set to its hardware
> > default
> > value of 0x1E
On Wed, Jan 18, 2017 at 05:28:17PM +0100, Arnd Bergmann wrote:
> On Wednesday, January 18, 2017 1:58:14 PM CET Jens Wiklander wrote:
> > Adds a OP-TEE driver which also can be compiled as a loadable module.
> >
> > * Targets ARM and ARM64
> > * Supports using reserved memory from OP-TEE as shared
From: Yisheng Xie
This patch is to extends soft offlining framework to support
non-lru page, which already support migration after
commit bda807d44454 ("mm: migrate: support non-lru movable page
migration")
When memory corrected errors occur on a non-lru movable page,
we
This patch enables RTC on stm32746g-eval with default LSE clock source.
Signed-off-by: Amelie Delaunay
---
arch/arm/boot/dts/stm32746g-eval.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/stm32746g-eval.dts
On Thu, Jan 19, 2017 at 02:37:56PM +, Juri Lelli wrote:
> +extern unsigned long
> +arch_scale_cpu_capacity(struct sched_domain *sd, int cpu);
> +extern void set_capacity_scale(unsigned int cpu, unsigned long capacity);
These should be in a header file (please run your code through sparse).
>
On Tue, Dec 20, 2016 at 01:10:56PM +0100, Ulf Hansson wrote:
> Hi Jan,
>
> On 19 December 2016 at 13:15, Jan Glauber wrote:
> > While this patch series seems to be somehow overdue, in the meantime the
> > same MMC unit was re-used on Cavium's ThunderX SOC so our interest in
On 11.10.2016 15:39, Rob Herring wrote:
On Tue, Oct 11, 2016 at 3:17 AM, Schrempf Frieder
wrote:
On 10.10.2016 17:20, Rob Herring wrote:
On Fri, Oct 07, 2016 at 09:08:17AM +, Schrempf Frieder wrote:
This patch adds the documentation for the devicetree bindings
Most of the ISA_BUS_API drivers control GPIO via 8-bit ioport registers.
Since updating any given GPIO line involves writing out all 8 bits for
the respective register, it makes sense to add support for the GPIO
set_multiple callback function so that multiple GPIO lines may be set
more
On Thu 19 Jan 06:54 PST 2017, Arnd Bergmann wrote:
> Without CONFIG_NET, we get a build failure for the new driver:
>
> ERROR: "skb_queue_tail" [drivers/rpmsg/rpmsg_char.ko] undefined!
> ERROR: "skb_put" [drivers/rpmsg/rpmsg_char.ko] undefined!
> ERROR: "__alloc_skb"
The Diamond Systems GPIO-MM series provides registers where 8 lines of
GPIO may be set at a time. This patch add support for the set_multiple
callback function, thus allowing multiple GPIO output lines to be set
more efficiently in groups.
Signed-off-by: William Breathitt Gray
The WinSystems WS16C48 provides registers where 8 lines of GPIO may be
set at a time. This patch add support for the set_multiple callback
function, thus allowing multiple GPIO output lines to be set more
efficiently in groups.
Signed-off-by: William Breathitt Gray
---
The ACCES 104-IDIO-16 series provides registers where 8 lines of GPIO
may be set at a time. This patch add support for the set_multiple
callback function, thus allowing multiple GPIO output lines to be set
more efficiently in groups.
Signed-off-by: William Breathitt Gray
Hi Gilad,
On 19 January 2017 at 15:17, Gilad Ben-Yossef wrote:
> I tried adding sg_init_table() where I thought it was appropriate and
> it didn't resolve the issue.
>
> For what it's worth, my guess is that the difference between our
> setups is not related to Arm but to
The Apex Embedded Systems STX104 series provides a digital output
register where 4 lines may be set at a time. This patch add support for
the set_multiple callback function, thus allowing multiple digital
output lines to be set more efficiently in groups.
Cc: Jonathan Cameron
Hi Roger,
On 2017-01-19 17:45, Roger Quadros wrote:
Vivek,
On 19/01/17 13:56, Vivek Gautam wrote:
Hi,
On Wed, Jun 22, 2016 at 2:00 PM, Roger Quadros wrote:
Luckily hit this thread while checking about DRD role functionality
for DWC3.
On 22/06/16 11:14, Felipe Balbi
This patch adds arch-independent testcases for RODATA.
Both x86 and x86_64 already have testcases for RODATA,
But they are arch-specific because using inline assembly directly.
and cacheflush.h is not suitable location for rodata-test related things.
Since they were in cacheflush.h,
If someone
When running my likely/unlikely profiler, I noticed that the
SCHED_DEADLINE's pick_next_task_dl() unlikely case of
(!dl_rq->dl_nr_running) was always being hit. There's two cases where
this can happen.
First, there's an optimization in pick_next_task() for the likely case
that the only tasks
This patch adds the devicetree bindings to set the volume levels
and the default volume level.
Signed-off-by: Frieder Schrempf
---
Changes in v3:
- none
drivers/input/misc/pwm-beeper.c | 49 ++---
1 file changed, 46
This patch adds the documentation for the devicetree bindings to set
the volume levels.
Signed-off-by: Frieder Schrempf
---
Changes in v3:
- change description of volume-levels to be used for linear levels
.../devicetree/bindings/input/pwm-beeper.txt | 20
Le 18/01/2017 à 17:46, Alexandre Belloni a écrit :
> Enable DMA on usart3 to get a more reliable console. This is especially
> useful for automation and kernelci were a kernel with PROVE_LOCKING enabled
> is quite susceptible to character loss, resulting in tests failure.
>
> Cc: stable
Hi Bjorn,
Please could you review this driver?
Thanks,
Matt
On 11/01/17 15:34, Matt Redfearn wrote:
This driver allows a MIPS processor offlined from Linux to be used as a
remote processor. Firmware may be loaded via the sysfs interface and
changed at runtime, allowing the processor to
Make the driver accept switching volume levels via sysfs.
This can be helpful if the beep/bell sound intensity needs
to be adapted to the environment of the device.
The volume adjustment is done by changing the duty cycle of
the pwm signal.
This patch adds the sysfs interface with 5 default
There's an issue with the da850 SATA controller: if port multiplier
support is compiled in, but we're connecting the drive directly to
the SATA port on the board, the drive can't be detected.
To make SATA work on the da850-lcdk board: first try to softreset
with pmp - if the operation fails with
Make the driver accept switching volume levels via sysfs.
This can be helpful if the beep/bell sound intensity needs
to be adapted to the environment of the device.
The number of volume levels available and their values can
be specified via device tree (similar to pwm-backlight).
The volume
Hi Laurent,
On 18-01-2017 20:49, Laurent Pinchart wrote:
>
> Ideally the bridge mode set operation should be extended to take format and
> colorspace information (or another bridge operation should be created for
> that
> purpose, I'm still undecided). As that's quite a big change, I'm fine
Hi Michael,
[auto build test ERROR on pci/next]
[also build test ERROR on v4.10-rc4]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Michael-S-Tsirkin/pci-drop-link_reset/20170119-34
base
This patchset enables STM32 RTC on STM32F746 MCU.
Amelie Delaunay (3):
ARM: dts: stm32: set HSE_RTC clock frequency to 1 MHz on stm32f746
ARM: dts: stm32: Add RTC support for STM32F746 MCU
ARM: dts: stm32: enable RTC on stm32746g-eval
arch/arm/boot/dts/stm32746g-eval.dts | 4
On Thu, Jan 19, 2017 at 9:05 AM, Rob Herring wrote:
> On Thu, Jan 19, 2017 at 7:37 AM, Greg Kroah-Hartman
> wrote:
>> On Mon, Jan 16, 2017 at 04:54:29PM -0600, Rob Herring wrote:
>>> From: Alan Cox
>>>
>>> Let us create tty
On Wed, Jan 18, 2017 at 05:41:45PM -0800, Andi Kleen wrote:
> A native disassembler in perf is very useful, in particular with perf script
> to trace
> instruction streams, but also for other analysis. Previously I attempted
> to do this using the udis86 library, but that was rejected because:
>
On 01/18/2017 06:19 PM, Andy Lutomirski wrote:
> On Wed, Jan 18, 2017 at 2:16 PM, David Smith wrote:
>> On 01/16/2017 03:14 PM, Thomas Gleixner wrote:
>>> On Mon, 16 Jan 2017, David Smith wrote:
... stuff deleted ...
If you put that new access_ok() call in a module that
On Thu, Jan 19, 2017 at 06:54:23AM -0800, Tony Lindgren wrote:
> * Greg Kroah-Hartman [170119 05:25]:
> > On Fri, Jan 13, 2017 at 10:20:21AM -0800, Tony Lindgren wrote:
> > > * Vignesh R [170113 00:03]:
> > > > This patch series re enables DMA support
This patch adds arch-independent testcases for RODATA.
Both x86 and x86_64 already have testcases for RODATA,
But they are arch-specific because using inline assembly directly.
and cacheflush.h is not suitable location for rodata-test related things.
Since they were in cacheflush.h,
If someone
Hi,
In the block layer, we abuse sysfs to export some per-device debugging
information. I was looking into moving this to debugfs, but I realized
that debugfs doesn't have a mechanism to ensure that a file associated
with a device is safe to use when the device is removed.
At a quick glance,
Change livepatch to use a basic per-task consistency model. This is the
foundation which will eventually enable us to patch those ~10% of
security patches which change function or data semantics. This is the
biggest remaining piece needed to make livepatch more generally useful.
This code stems
Small glitch/degraded performance in Crusader is improved with SAS
drives by removing unnecessary spinlocks while clearing scsi command
in drivers internal lookup table.
Signed-off-by: Chaitra P B
Suganath Prabu
On Thu, 2017-01-19 at 15:49 +0100, Clemens Gruber wrote:
> On Thu, Jan 19, 2017 at 02:34:39PM +0200, Andy Shevchenko wrote:
> > On Wed, 2017-01-18 at 15:25 +0100, Clemens Gruber wrote:
> > > Yes, that's what this patch tries to solve by verifying that the
> > > external setting (the prescale
On Wed, Jan 18, 2017 at 01:08:14AM +0800, Icenowy Zheng wrote:
>
>
> 17.01.2017, 17:05, "Maxime Ripard" :
> > Hi,
> >
> > On Tue, Jan 17, 2017 at 02:01:14AM +0800, Icenowy Zheng wrote:
> >> V3s has a similar but cut-down CCU to H3.
> >>
> >> Add support for
On Thu, Jan 19, 2017 at 02:40:08PM +, Russell King - ARM Linux wrote:
> On Wed, Jan 11, 2017 at 04:31:57PM -0600, Andy Gross wrote:
> > diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h
> > index b5abfda..3e28d08 100644
> > --- a/include/linux/arm-smccc.h
> > +++
On Thu, Jan 19, 2017 at 03:53:15PM +0100, Andrew Lunn wrote:
> > > > struct dsa_platform_data {
> > > > /*
> > > > * Reference to a Linux network interface that connects
> > > > * to the root switch chip of the tree.
> > > > */
> > > > struct device
Hello, everyone:
This is a small patchset intended to add PCI-subsystem bits necessary
for enabling PCI support on i.MX7. This patchset is not
self-sufficient and depends on three other patchsets:
- Changes to anatop regulator driver
- Chagnes to i.MX device tree code pertaining to anatop
Some designs implement reset GPIO via a GPIO expander connected to a
peripheral bus. One such example would be i.MX7 Sabre board where said
GPIO is provided by SPI shift register connected to a bitbanged SPI
bus. In order to support such designs allow reset GPIO request to defer
probing of the
Cc: yurov...@gmail.com
Cc: Richard Zhu
Cc: Lucas Stach
Cc: Bjorn Helgaas
Cc: Fabio Estevam
Cc: Shawn Guo
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
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