Re: [PATCH 3/9] platform/x86: hp-wmi: Standardize enum usage for constants

On Wed, Apr 19, 2017 at 07:25:15PM -0700, Darren Hart wrote: > From: "Darren Hart (VMware)" > > Use enums consistently throughout the hp-wmi driver for groups of > related constants. Use hex and align the assignment within groups. Move > the *QUERY constants into an enum,

Re: [PATCH 3/9] platform/x86: hp-wmi: Standardize enum usage for constants

On Wed, Apr 19, 2017 at 07:25:15PM -0700, Darren Hart wrote: > From: "Darren Hart (VMware)" > > Use enums consistently throughout the hp-wmi driver for groups of > related constants. Use hex and align the assignment within groups. Move > the *QUERY constants into an enum, create a new enum

Re: [PATCH 0/5] IB/hfi1: Fine-tuning for three function implementations

On Fri, 2017-02-10 at 22:00 +0100, SF Markus Elfring wrote: > From: Markus Elfring > Date: Fri, 10 Feb 2017 21:53:21 +0100 > > A few update suggestions were taken into account > from static source code analysis. > > Markus Elfring (5): >   Use kcalloc() in

Re: [PATCH 0/5] IB/hfi1: Fine-tuning for three function implementations

On Fri, 2017-02-10 at 22:00 +0100, SF Markus Elfring wrote: > From: Markus Elfring > Date: Fri, 10 Feb 2017 21:53:21 +0100 > > A few update suggestions were taken into account > from static source code analysis. > > Markus Elfring (5): >   Use kcalloc() in hfi1_user_exp_rcv_init() >   Use

[PATCH 2/2] firewire: ohci: Adjust 15 checks for null pointers

From: Markus Elfring Date: Thu, 20 Apr 2017 22:10:29 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The script “checkpatch.pl” pointed information out like the following. Comparison to NULL could be written … Thus

[PATCH 2/2] firewire: ohci: Adjust 15 checks for null pointers

From: Markus Elfring Date: Thu, 20 Apr 2017 22:10:29 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The script “checkpatch.pl” pointed information out like the following. Comparison to NULL could be written … Thus fix the affected source code

[PATCH 1/2] firewire: ohci: Use kcalloc() in pci_probe()

From: Markus Elfring Date: Thu, 20 Apr 2017 21:50:19 +0200 * Multiplications for the size determination of memory allocations indicated that array data structures should be processed. Thus use the corresponding function "kcalloc". This issue was detected by

[PATCH 1/2] firewire: ohci: Use kcalloc() in pci_probe()

From: Markus Elfring Date: Thu, 20 Apr 2017 21:50:19 +0200 * Multiplications for the size determination of memory allocations indicated that array data structures should be processed. Thus use the corresponding function "kcalloc". This issue was detected by using the Coccinelle software.

Re: [PATCH v2 1/2] dt-binding: regulator: anatop: make regulator name property required

On Wed, Apr 19, 2017 at 03:33:03PM +, A.S. Dong wrote: > > We actually can't allow the missing of the regualor name, thus update the > > binding doc to make regulator-name property to be required. > Sorry, Mark, missed you about this one. Please resend, I don't have a copy. signature.asc

Re: [PATCH v2 1/2] dt-binding: regulator: anatop: make regulator name property required

On Wed, Apr 19, 2017 at 03:33:03PM +, A.S. Dong wrote: > > We actually can't allow the missing of the regualor name, thus update the > > binding doc to make regulator-name property to be required. > Sorry, Mark, missed you about this one. Please resend, I don't have a copy. signature.asc

Re: [alsa-devel] [PATCH] ASoC: dwc: disallow building designware_pcm as a module

On Thu, Apr 20, 2017 at 10:24:14PM +0200, Takashi Iwai wrote: > Mark Brown wrote: > > I think forcing this to be built in to the kernel (which is what the > > commit message says the change is going to do) is an obviously bad > > idea. Anything we add to the base kernel image needs to have a

Re: [alsa-devel] [PATCH] ASoC: dwc: disallow building designware_pcm as a module

On Thu, Apr 20, 2017 at 10:24:14PM +0200, Takashi Iwai wrote: > Mark Brown wrote: > > I think forcing this to be built in to the kernel (which is what the > > commit message says the change is going to do) is an obviously bad > > idea. Anything we add to the base kernel image needs to have a

[PATCH 0/2] FireWire-OHCI: Fine-tuning for some function implementations

From: Markus Elfring Date: Thu, 20 Apr 2017 22:22:10 +0200 A few update suggestions were taken into account from static source code analysis. Markus Elfring (2): Use kcalloc() in pci_probe() Adjust 15 checks for null pointers drivers/firewire/ohci.c | 41

[PATCH 0/2] FireWire-OHCI: Fine-tuning for some function implementations

From: Markus Elfring Date: Thu, 20 Apr 2017 22:22:10 +0200 A few update suggestions were taken into account from static source code analysis. Markus Elfring (2): Use kcalloc() in pci_probe() Adjust 15 checks for null pointers drivers/firewire/ohci.c | 41

Re: [alsa-devel] [PATCH] ASoC: dwc: disallow building designware_pcm as a module

On Thu, 20 Apr 2017 21:46:46 +0200, Mark Brown wrote: > > On Wed, Apr 19, 2017 at 05:48:15PM +0100, Jose Abreu wrote: > > > What do you think Mark? If you want to keep the PCM as a module > > then we will need to abstract this more, by reducing the > > dependencies. > > I think forcing this to

Re: [alsa-devel] [PATCH] ASoC: dwc: disallow building designware_pcm as a module

On Thu, 20 Apr 2017 21:46:46 +0200, Mark Brown wrote: > > On Wed, Apr 19, 2017 at 05:48:15PM +0100, Jose Abreu wrote: > > > What do you think Mark? If you want to keep the PCM as a module > > then we will need to abstract this more, by reducing the > > dependencies. > > I think forcing this to

Re: [PATCH v1 0/9] platform/x86: hp-wmi: Driver refactoring and cleanups

On Thu, Apr 20, 2017 at 10:38:56AM +0300, Andy Shevchenko wrote: > On Thu, Apr 20, 2017 at 5:25 AM, Darren Hart wrote: > > From: "Darren Hart (VMware)" > > > > This series factors out some redundant code, cleans up a number of style > > issues, > >

Re: [PATCH v1 0/9] platform/x86: hp-wmi: Driver refactoring and cleanups

On Thu, Apr 20, 2017 at 10:38:56AM +0300, Andy Shevchenko wrote: > On Thu, Apr 20, 2017 at 5:25 AM, Darren Hart wrote: > > From: "Darren Hart (VMware)" > > > > This series factors out some redundant code, cleans up a number of style > > issues, > > modernizes the sysfs usage, and cleans up the

Re: [PATCH 3/4] nfs: remove the objlayout driver

On Wed, 2017-04-12 at 18:01 +0200, Christoph Hellwig wrote: > The objlayout code has been in the tree, but it's been unmaintained > and > no server product for it actually ever shipped. > > Signed-off-by: Christoph Hellwig > --- >  Documentation/admin-guide/kernel-parameters.txt |   

Re: [PATCH 3/4] nfs: remove the objlayout driver

On Wed, 2017-04-12 at 18:01 +0200, Christoph Hellwig wrote: > The objlayout code has been in the tree, but it's been unmaintained > and > no server product for it actually ever shipped. > > Signed-off-by: Christoph Hellwig > --- >  Documentation/admin-guide/kernel-parameters.txt |   6 - >  

Re: [PATCH v2 0/3] uapi glibc compat: fix musl libc compatibility

On Thu, 2017-04-20 at 16:07 -0400, David Miller wrote: > > I think I have to put the brakes on this patch series, after much > consideration. > > It does not scale if we continually add a hodge-podge of different > ifdef tests to the UAPI headers in order to prevent mutliple > definitions. > >

Re: [PATCH v2 0/3] uapi glibc compat: fix musl libc compatibility

On Thu, 2017-04-20 at 16:07 -0400, David Miller wrote: > > I think I have to put the brakes on this patch series, after much > consideration. > > It does not scale if we continually add a hodge-podge of different > ifdef tests to the UAPI headers in order to prevent mutliple > definitions. > >

Re: [PATCH 0/4] infiniband: chelsio

On Thu, 2017-02-09 at 14:23 -0800, Joe Perches wrote: > Neaten logging > > Joe Perches (4): >   cxgb3: Use more common logging style >   cxgb3: Convert PDBG to pr_debug >   cxgb4: Use more common logging style >   cxgb4: Convert PDBG to pr_debug > >  drivers/infiniband/hw/cxgb3/cxio_dbg.c  | 

Re: [PATCH 0/4] infiniband: chelsio

On Thu, 2017-02-09 at 14:23 -0800, Joe Perches wrote: > Neaten logging > > Joe Perches (4): >   cxgb3: Use more common logging style >   cxgb3: Convert PDBG to pr_debug >   cxgb4: Use more common logging style >   cxgb4: Convert PDBG to pr_debug > >  drivers/infiniband/hw/cxgb3/cxio_dbg.c  | 

Re: [PATCH V5 4/7] ARM: pxa: Use - instead of @ for DT OPP entries

Viresh Kumar writes: > Compiling the DT file with W=1, DTC warns like follows: > > Warning (unit_address_vs_reg): Node /opp_table0/opp@10 has a > unit name, but no reg property > > Fix this by replacing '@' with '-' as the OPP nodes will never have a > "reg"

Re: [PATCH V5 4/7] ARM: pxa: Use - instead of @ for DT OPP entries

Viresh Kumar writes: > Compiling the DT file with W=1, DTC warns like follows: > > Warning (unit_address_vs_reg): Node /opp_table0/opp@10 has a > unit name, but no reg property > > Fix this by replacing '@' with '-' as the OPP nodes will never have a > "reg" property. > > Reported-by:

Re: [PATCH] ARM: dts: Add devicetree for the Raspberry Pi 3, for arm32 (v4)

Florian Fainelli writes: > On 03/29/2017 05:26 PM, Eric Anholt wrote: >> Raspbian and Fedora have decided to support the Pi3 in 32-bit mode for >> now, so it's useful to be able to test that mode on an upstream >> kernel. It's also been useful for me to use the same board

Re: [PATCH] ARM: dts: Add devicetree for the Raspberry Pi 3, for arm32 (v4)

Florian Fainelli writes: > On 03/29/2017 05:26 PM, Eric Anholt wrote: >> Raspbian and Fedora have decided to support the Pi3 in 32-bit mode for >> now, so it's useful to be able to test that mode on an upstream >> kernel. It's also been useful for me to use the same board for 32-bit >> and

Re: [PATCH net-next v3] bindings: net: stmmac: add missing note about LPI interrupt

On Tue, Apr 18, 2017 at 02:39:53PM +0200, Niklas Cassel wrote: > From: Niklas Cassel > > The hardware has a LPI interrupt. > There is already code in the stmmac driver to parse and handle the > interrupt. However, this information was missing from the DT binding. > > At

Re: [PATCH net-next v3] bindings: net: stmmac: add missing note about LPI interrupt

On Tue, Apr 18, 2017 at 02:39:53PM +0200, Niklas Cassel wrote: > From: Niklas Cassel > > The hardware has a LPI interrupt. > There is already code in the stmmac driver to parse and handle the > interrupt. However, this information was missing from the DT binding. > > At the same time, improve

Re: [PATCH] arm: Documentation: update a path name

On Thu, 20 Apr 2017 12:58:40 +0800 Perr Zhang wrote: > the path in the example cmd is out of date, and the path for now > is also mentioned in the same file Gee, that's only been wrong since 2008...:) Applied, thanks. jon

Re: [PATCH] arm: Documentation: update a path name

On Thu, 20 Apr 2017 12:58:40 +0800 Perr Zhang wrote: > the path in the example cmd is out of date, and the path for now > is also mentioned in the same file Gee, that's only been wrong since 2008...:) Applied, thanks. jon

Re: [PATCH v2 0/3] uapi glibc compat: fix musl libc compatibility

From: Hauke Mehrtens Date: Tue, 18 Apr 2017 23:00:33 +0200 > The code from libc-compat.h depends on some glibc specific defines and > causes compile problems with the musl libc. These patches remove some > of the glibc dependencies. With these patches the LEDE (OpenWrt) base

Re: [PATCH v2 0/3] uapi glibc compat: fix musl libc compatibility

From: Hauke Mehrtens Date: Tue, 18 Apr 2017 23:00:33 +0200 > The code from libc-compat.h depends on some glibc specific defines and > causes compile problems with the musl libc. These patches remove some > of the glibc dependencies. With these patches the LEDE (OpenWrt) base > user space

Re: [linux-sunxi] Re: [PATCH v2 1/6] clk: sunxi-ng: Add sun4i/sun7i CCU driver

On Fri, Apr 07, 2017 at 03:38:05PM +0200, Maxime Ripard wrote: > Hi Priit, > > On Tue, Apr 04, 2017 at 08:09:19PM +, Priit Laes wrote: > > > > +/* Not documented on A10 */ > > > > +static SUNXI_CCU_GATE(pll_periph_sata_clk, "pll-periph-sata", > > > > "pll-periph", > > > > +

Re: [linux-sunxi] Re: [PATCH v2 1/6] clk: sunxi-ng: Add sun4i/sun7i CCU driver

On Fri, Apr 07, 2017 at 03:38:05PM +0200, Maxime Ripard wrote: > Hi Priit, > > On Tue, Apr 04, 2017 at 08:09:19PM +, Priit Laes wrote: > > > > +/* Not documented on A10 */ > > > > +static SUNXI_CCU_GATE(pll_periph_sata_clk, "pll-periph-sata", > > > > "pll-periph", > > > > +

Re: [PATCH] fs: compat: Remove warning from COMPATIBLE_IOCTL

e most of the remaining contents > as they come from the old llvmlinux project. Yeah, I picked a subset of the llvmlinux patches from different sources. > For reference, I've uploaded my set to > > git://git.kernel.org/pub/scm/linux/kernel/git/arnd/playground.git > next-20170420

Re: [PATCH] fs: compat: Remove warning from COMPATIBLE_IOCTL

om the old llvmlinux project. Yeah, I picked a subset of the llvmlinux patches from different sources. > For reference, I've uploaded my set to > > git://git.kernel.org/pub/scm/linux/kernel/git/arnd/playground.git > next-20170420+llvmlinux > > This is rebased from the middle of a larger series, so there might be > problems I introduce. Just have a look to see what you can use. Thanks! Matthias

Re: [PATCH] net/packet: initialize val in packet_getsockopt()

From: Alexander Potapenko Date: Tue, 18 Apr 2017 19:47:08 +0200 > In the case getsockopt() is called with PACKET_HDRLEN and zero length, > |val| remains uninitialized and the syscall may behave differently > depending on its value. This doesn't have security consequences (as

Re: [PATCH] net/packet: initialize val in packet_getsockopt()

From: Alexander Potapenko Date: Tue, 18 Apr 2017 19:47:08 +0200 > In the case getsockopt() is called with PACKET_HDRLEN and zero length, > |val| remains uninitialized and the syscall may behave differently > depending on its value. This doesn't have security consequences (as the > uninit bytes

Re: [PATCH 3.18 000/124] 3.18.50-stable review

On Thu, Apr 20, 2017 at 04:28:03PM +0200, Greg Kroah-Hartman wrote: > On Thu, Apr 20, 2017 at 06:46:11AM -0700, Guenter Roeck wrote: > > On 04/19/2017 11:34 PM, Greg Kroah-Hartman wrote: > > > This is the start of the stable review cycle for the 3.18.50 release. > > > There are 124 patches in this

[PATCH 3/4] sched/topology: move comment about asymmetric node setups

Signed-off-by: Lauro Ramos Venancio --- kernel/sched/topology.c | 19 ++- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c index 55bbaf7..e77c93a 100644 --- a/kernel/sched/topology.c +++

[PATCH 4/4] sched/topology: the group balance cpu must be a cpu where the group is installed

An overlap sched group may not be installed in all cpus that compose the group. Currently, the group balance cpu may be a cpu where the group is not installed, causing two problems: 1) Two groups may have the same group balance cpu and, as consequence, share the sched_group_capacity. 2)

Re: [PATCH 3.18 000/124] 3.18.50-stable review

On Thu, Apr 20, 2017 at 04:28:03PM +0200, Greg Kroah-Hartman wrote: > On Thu, Apr 20, 2017 at 06:46:11AM -0700, Guenter Roeck wrote: > > On 04/19/2017 11:34 PM, Greg Kroah-Hartman wrote: > > > This is the start of the stable review cycle for the 3.18.50 release. > > > There are 124 patches in this

[PATCH 3/4] sched/topology: move comment about asymmetric node setups

Signed-off-by: Lauro Ramos Venancio --- kernel/sched/topology.c | 19 ++- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c index 55bbaf7..e77c93a 100644 --- a/kernel/sched/topology.c +++ b/kernel/sched/topology.c @@

[PATCH 4/4] sched/topology: the group balance cpu must be a cpu where the group is installed

An overlap sched group may not be installed in all cpus that compose the group. Currently, the group balance cpu may be a cpu where the group is not installed, causing two problems: 1) Two groups may have the same group balance cpu and, as consequence, share the sched_group_capacity. 2)

Re: [RFC] minimum gcc version for kernel: raise to gcc-4.3 or 4.6?

On Thu, Apr 20, 2017 at 3:15 AM, Arnd Bergmann wrote: > On Sun, Apr 16, 2017 at 9:52 PM, Kees Cook wrote: The original gcc-4.3 release was in early 2008. If we decide to still support that, we probably want the first 10 quirks in this series,

Re: [RFC] minimum gcc version for kernel: raise to gcc-4.3 or 4.6?

On Thu, Apr 20, 2017 at 3:15 AM, Arnd Bergmann wrote: > On Sun, Apr 16, 2017 at 9:52 PM, Kees Cook wrote: The original gcc-4.3 release was in early 2008. If we decide to still support that, we probably want the first 10 quirks in this series, while gcc-4.6 (released in 2011)

[PATCH 1/4] sched/topology: optimize build_group_mask()

The group mask is always used in intersection with the group cpus. So, when building the group mask, we don't have to care about cpus that are not part of the group. Signed-off-by: Lauro Ramos Venancio --- kernel/sched/topology.c | 4 ++-- 1 file changed, 2 insertions(+), 2

[PATCH 2/4] sched/topology: all instances of a sched group must use the same sched_group_capacity

Use the group balance cpu to select the same sched_group_capacity instance for all instances of a sched group. As the group mask is stored in the struct sched_group_capacity and the function group_balance_cpu() cannot be used when the group mask is not available, this patch creates a function to

[PATCH 1/4] sched/topology: optimize build_group_mask()

The group mask is always used in intersection with the group cpus. So, when building the group mask, we don't have to care about cpus that are not part of the group. Signed-off-by: Lauro Ramos Venancio --- kernel/sched/topology.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff

[PATCH 2/4] sched/topology: all instances of a sched group must use the same sched_group_capacity

Use the group balance cpu to select the same sched_group_capacity instance for all instances of a sched group. As the group mask is stored in the struct sched_group_capacity and the function group_balance_cpu() cannot be used when the group mask is not available, this patch creates a function to

[PATCH 0/4] sched/topology: fix overlap group capacity and balance cpu

This patchset is on top of Peter Zijlstra's sched/core tree[1]. It is equivalent to the patch 3 from my previous patchset[2]. This patchset ensures: 1) different instances of the same sched group share the same sched_group_capacity instance. 2) instances of different groups don't share the

[PATCH 0/4] sched/topology: fix overlap group capacity and balance cpu

This patchset is on top of Peter Zijlstra's sched/core tree[1]. It is equivalent to the patch 3 from my previous patchset[2]. This patchset ensures: 1) different instances of the same sched group share the same sched_group_capacity instance. 2) instances of different groups don't share the

Re: [PATCH v5] drm/pl111: Initial drm/kms driver for pl111

Russell King - ARM Linux writes: > On Tue, Apr 11, 2017 at 02:00:21PM -0700, Eric Anholt wrote: >> Russell King - ARM Linux writes: >> >> > On Tue, Apr 11, 2017 at 09:06:31AM -0700, Eric Anholt wrote: >> >> Russell King - ARM Linux

Re: [PATCH v5] drm/pl111: Initial drm/kms driver for pl111

Russell King - ARM Linux writes: > On Tue, Apr 11, 2017 at 02:00:21PM -0700, Eric Anholt wrote: >> Russell King - ARM Linux writes: >> >> > On Tue, Apr 11, 2017 at 09:06:31AM -0700, Eric Anholt wrote: >> >> Russell King - ARM Linux writes: >> >> >> >> > On Mon, Apr 10, 2017 at 06:18:01PM

Re: [PATCH] ASoC: codec: wm9860: avoid maybe-uninitialized warning

On Thu, Apr 20, 2017 at 09:44:28AM +0200, Arnd Bergmann wrote: > On Thu, Apr 20, 2017 at 8:48 AM, Daniel Baluta > wrote: > > On Wed, Apr 19, 2017 at 8:04 PM, Arnd Bergmann wrote: > > gcc version 6.2.1 20161016 (Linaro GCC 6.2-2016.11) > I'm using

Re: [PATCH] ASoC: codec: wm9860: avoid maybe-uninitialized warning

On Thu, Apr 20, 2017 at 09:44:28AM +0200, Arnd Bergmann wrote: > On Thu, Apr 20, 2017 at 8:48 AM, Daniel Baluta > wrote: > > On Wed, Apr 19, 2017 at 8:04 PM, Arnd Bergmann wrote: > > gcc version 6.2.1 20161016 (Linaro GCC 6.2-2016.11) > I'm using gcc-7.0.1 here, which overall has better

Re: [PATCH v2] timer/sysclt: Restrict timer migration sysctl values to 0 and 1

On Thu, 20 Apr 2017, Myungho Jung wrote: I told you to check your mail so you avoid sending a V2. That mail from tip-bot is a notification that: This > Commit-ID: b94bf594cf8ed67cdd0439e70fa939783471597a which can be looked at via: > Gitweb:

Re: [PATCH v2] timer/sysclt: Restrict timer migration sysctl values to 0 and 1

On Thu, 20 Apr 2017, Myungho Jung wrote: I told you to check your mail so you avoid sending a V2. That mail from tip-bot is a notification that: This > Commit-ID: b94bf594cf8ed67cdd0439e70fa939783471597a which can be looked at via: > Gitweb:

Re: [PATCH] ASoC: dwc: disallow building designware_pcm as a module

On Wed, Apr 19, 2017 at 05:48:15PM +0100, Jose Abreu wrote: > What do you think Mark? If you want to keep the PCM as a module > then we will need to abstract this more, by reducing the > dependencies. I think forcing this to be built in to the kernel (which is what the commit message says the

Re: [PATCH v17 2/3] usb: USB Type-C connector class

Thanks for the responses :) So seems like we have a plan. In Type-C connector class the checks for TYPEC_PWR_MODE_PD and pd_revision for both the port and the partner will be removed in power_role_store and the data_role_store and will be delegated to the low level drivers. TCPM code will issue

Re: [PATCH] ASoC: dwc: disallow building designware_pcm as a module

On Wed, Apr 19, 2017 at 05:48:15PM +0100, Jose Abreu wrote: > What do you think Mark? If you want to keep the PCM as a module > then we will need to abstract this more, by reducing the > dependencies. I think forcing this to be built in to the kernel (which is what the commit message says the

Re: [PATCH v17 2/3] usb: USB Type-C connector class

Thanks for the responses :) So seems like we have a plan. In Type-C connector class the checks for TYPEC_PWR_MODE_PD and pd_revision for both the port and the partner will be removed in power_role_store and the data_role_store and will be delegated to the low level drivers. TCPM code will issue

[PATCH RESEND] Makefile, LLVM: add -no-integrated-as to KBUILD_[AC]FLAGS

From: Michael Davidson Add -no-integrated-as to KBUILD_AFLAGS and KBUILD_CFLAGS for clang. Signed-off-by: Michael Davidson Signed-off-by: Matthias Kaehlcke --- Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Makefile

[PATCH RESEND] Makefile, LLVM: add -no-integrated-as to KBUILD_[AC]FLAGS

From: Michael Davidson Add -no-integrated-as to KBUILD_AFLAGS and KBUILD_CFLAGS for clang. Signed-off-by: Michael Davidson Signed-off-by: Matthias Kaehlcke --- Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Makefile b/Makefile index 5039b9148d15..3832c8243334 100644 ---

Re: [PATCH 2/2] tick: Make sure tick timer is active when bypassing reprogramming

On Thu, 20 Apr 2017, Frederic Weisbecker wrote: > On Thu, Apr 20, 2017 at 07:56:22PM +0200, Thomas Gleixner wrote: > > > /* Skip reprogram of event if its not changed */ > > > - if (ts->tick_stopped && (expires == ts->next_tick)) > > > + if (ts->tick_stopped && (expires == ts->next_tick)) { > >

Re: [PATCH 2/2] tick: Make sure tick timer is active when bypassing reprogramming

On Thu, 20 Apr 2017, Frederic Weisbecker wrote: > On Thu, Apr 20, 2017 at 07:56:22PM +0200, Thomas Gleixner wrote: > > > /* Skip reprogram of event if its not changed */ > > > - if (ts->tick_stopped && (expires == ts->next_tick)) > > > + if (ts->tick_stopped && (expires == ts->next_tick)) { > >

[PATCH 2/3] bus: fsl-mc: dpio: enable qbman CENA portal memory access

Once we enable the cacheable portal memory, we need to do cache flush for enqueue, vdq, buffer release, and management commands, as well as invalidate and prefetch for the valid bit of management command response and next index of dqrr. Signed-off-by: Haiying Wang ---

[PATCH 2/3] bus: fsl-mc: dpio: enable qbman CENA portal memory access

Once we enable the cacheable portal memory, we need to do cache flush for enqueue, vdq, buffer release, and management commands, as well as invalidate and prefetch for the valid bit of management command response and next index of dqrr. Signed-off-by: Haiying Wang ---

Re: [PATCH] of: introduce event tracepoints for dynamic device_node lifecyle

On 04/20/17 09:51, Tyrel Datwyler wrote: > On 04/19/2017 09:43 PM, Frank Rowand wrote: > < snip > >> The call stack could easily be post-processed, for example using addr2line. >> Here is the call stack for when the refcount incremented to 23 from 22 (or >> more accurately, to 22 from 21): >>

Re: [PATCH] of: introduce event tracepoints for dynamic device_node lifecyle

On 04/20/17 09:51, Tyrel Datwyler wrote: > On 04/19/2017 09:43 PM, Frank Rowand wrote: > < snip > >> The call stack could easily be post-processed, for example using addr2line. >> Here is the call stack for when the refcount incremented to 23 from 22 (or >> more accurately, to 22 from 21): >>

[PATCH 1/3] arm64: extend ioremap for cacheable non-shareable memory

NXP arm64 based SoC needs to allocate cacheable and non-shareable memory for the software portals of Queue manager, so we extend the arm64 ioremap support for this memory attribute. Signed-off-by: Haiying Wang --- arch/arm64/include/asm/io.h | 1 +

[PATCH 1/3] arm64: extend ioremap for cacheable non-shareable memory

NXP arm64 based SoC needs to allocate cacheable and non-shareable memory for the software portals of Queue manager, so we extend the arm64 ioremap support for this memory attribute. Signed-off-by: Haiying Wang --- arch/arm64/include/asm/io.h | 1 +

[PATCH 3/3] bus: fsl-mc: dpio: change CENA regs to be cacheable

plus non-shareable to meet the performance requirement. QMan's CENA region contains registers and structures that are 64byte in size and are inteneded to be accessed using a single 64 byte bus transaction, therefore this portal memory should be configured as cache-enabled. Also because the write

[PATCH 3/3] bus: fsl-mc: dpio: change CENA regs to be cacheable

plus non-shareable to meet the performance requirement. QMan's CENA region contains registers and structures that are 64byte in size and are inteneded to be accessed using a single 64 byte bus transaction, therefore this portal memory should be configured as cache-enabled. Also because the write

[PATCH 0/3] bus: fsl-mc: dpio: udpate QMan CENA region

This patchset allows the NXP's DPAA2 QMan Software portal CENA region to be cacheable as designed for the performance goal. Besides, the write allocate stash feature of the QMan requires the non-shareable attribute for this cache-enabled memory. So this patchset extends the arm64 ioremap with

[PATCH 0/3] bus: fsl-mc: dpio: udpate QMan CENA region

This patchset allows the NXP's DPAA2 QMan Software portal CENA region to be cacheable as designed for the performance goal. Besides, the write allocate stash feature of the QMan requires the non-shareable attribute for this cache-enabled memory. So this patchset extends the arm64 ioremap with

[PATCH] sched/deadline: fix switching to -deadline

From: Luca Abeni When switching to -deadline, if the scheduling deadline of a task is in the past then switched_to_dl() calls setup_new_entity() to properly initialize the scheduling deadline and runtime. The problem is that the task is enqueued _before_ having its

[PATCH] sched/deadline: fix switching to -deadline

From: Luca Abeni When switching to -deadline, if the scheduling deadline of a task is in the past then switched_to_dl() calls setup_new_entity() to properly initialize the scheduling deadline and runtime. The problem is that the task is enqueued _before_ having its parameters initialized by

Re: [PATCH 1/4] scsi: pmcraid: use __iomem pointers for ioctl argument

On Thu, Apr 20, 2017 at 07:54:45PM +0200, Arnd Bergmann wrote: > kernelci.org reports a new compile warning for old code in the pmcraid > driver: > > arch/mips/include/asm/uaccess.h:138:21: warning: passing argument 1 of > '__access_ok' makes pointer from integer without a cast

Re: [PATCH 1/4] scsi: pmcraid: use __iomem pointers for ioctl argument

On Thu, Apr 20, 2017 at 07:54:45PM +0200, Arnd Bergmann wrote: > kernelci.org reports a new compile warning for old code in the pmcraid > driver: > > arch/mips/include/asm/uaccess.h:138:21: warning: passing argument 1 of > '__access_ok' makes pointer from integer without a cast

Re: [PATCH v2 -tip 0/6] locking: Introduce range reader/writer lock

On Thu, Apr 20, 2017 at 11:36:46AM -0700, Davidlohr Bueso wrote: > On Thu, 20 Apr 2017, Peter Zijlstra wrote: > >Those are about avoiding actually going to sleep and having to be woken > >up (and waiting to become running) again, which is a long time. > > Yes, which is why I was thinking of ways

Re: [PATCH v2 -tip 0/6] locking: Introduce range reader/writer lock

On Thu, Apr 20, 2017 at 11:36:46AM -0700, Davidlohr Bueso wrote: > On Thu, 20 Apr 2017, Peter Zijlstra wrote: > >Those are about avoiding actually going to sleep and having to be woken > >up (and waiting to become running) again, which is a long time. > > Yes, which is why I was thinking of ways

Re: [PATCH 3/3] arm64/locking: qspinlocks and qrwlocks support

On Thu, Apr 20, 2017 at 09:23:18PM +0300, Yury Norov wrote: > Is there some test to reproduce the locking failure for the case. Possibly sysvsem stress before commit: 27d7be1801a4 ("ipc/sem.c: avoid using spin_unlock_wait()") Although a similar scheme is also used in nf_conntrack, see commit:

Re: [PATCH 3/3] arm64/locking: qspinlocks and qrwlocks support

On Thu, Apr 20, 2017 at 09:23:18PM +0300, Yury Norov wrote: > Is there some test to reproduce the locking failure for the case. Possibly sysvsem stress before commit: 27d7be1801a4 ("ipc/sem.c: avoid using spin_unlock_wait()") Although a similar scheme is also used in nf_conntrack, see commit:

Re: [PATCH 1/4] fs: fix data invalidation in the cleancache during direct IO

On Thu, Apr 20, 2017 at 04:44:31PM +0200, Jan Kara wrote: > On Thu 20-04-17 16:35:10, Jan Kara wrote: > > On Wed 19-04-17 13:28:36, Ross Zwisler wrote: > > > On Wed, Apr 19, 2017 at 06:11:31PM +0300, Andrey Ryabinin wrote: > > > > On 04/18/2017 10:38 PM, Ross Zwisler wrote: > > > > > On Fri, Apr

Re: [PATCH 1/4] fs: fix data invalidation in the cleancache during direct IO

On Thu, Apr 20, 2017 at 04:44:31PM +0200, Jan Kara wrote: > On Thu 20-04-17 16:35:10, Jan Kara wrote: > > On Wed 19-04-17 13:28:36, Ross Zwisler wrote: > > > On Wed, Apr 19, 2017 at 06:11:31PM +0300, Andrey Ryabinin wrote: > > > > On 04/18/2017 10:38 PM, Ross Zwisler wrote: > > > > > On Fri, Apr

Re: [PATCH] pci-hyperv: Use only 16 bit integer for PCI domain

On Thu, Apr 20, 2017 at 06:37:35PM +, Haiyang Zhang wrote: > It's Nvidia driver. Which of the many nvidia drivers in the tree? Just fix it instead of coming up with stupid workarounds like this.

Re: [PATCH] pci-hyperv: Use only 16 bit integer for PCI domain

On Thu, Apr 20, 2017 at 06:37:35PM +, Haiyang Zhang wrote: > It's Nvidia driver. Which of the many nvidia drivers in the tree? Just fix it instead of coming up with stupid workarounds like this.

[PATCH 2/2] arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3

The ARMv8 PMUv3 cache map did not include the L2 cache events, add them. Signed-off-by: Florian Fainelli --- arch/arm64/kernel/perf_event.c | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index

[PATCH 2/2] arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3

The ARMv8 PMUv3 cache map did not include the L2 cache events, add them. Signed-off-by: Florian Fainelli --- arch/arm64/kernel/perf_event.c | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 4f011cdd756d..a664c575f3fd

[PATCH 1/2] arm64: pmu: Wire-up Cortex A53 L2 cache events and DTLB refills

Add missing L2 cache events: read/write accesses and misses, as well as the DTLB refills. Signed-off-by: Florian Fainelli --- arch/arm64/kernel/perf_event.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/kernel/perf_event.c

[PATCH 1/2] arm64: pmu: Wire-up Cortex A53 L2 cache events and DTLB refills

Add missing L2 cache events: read/write accesses and misses, as well as the DTLB refills. Signed-off-by: Florian Fainelli --- arch/arm64/kernel/perf_event.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index

[PATCH 1/2] arm64: perf: Wire-up Cortex A53 L2 cache events and DTLB refills

Add missing L2 cache events: read/write accesses and misses, as well as the DTLB refills. Signed-off-by: Florian Fainelli --- arch/arm64/kernel/perf_event.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/kernel/perf_event.c

[PATCH 1/2] arm64: perf: Wire-up Cortex A53 L2 cache events and DTLB refills

Add missing L2 cache events: read/write accesses and misses, as well as the DTLB refills. Signed-off-by: Florian Fainelli --- arch/arm64/kernel/perf_event.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index

[PATCH 0/2] arm64: perf: Add L2 cache events for ARMv8 PMuv3 and A53

Hi, While investigating why there were no L2 cache events generated for a Cortex A53-like PMU, it turned out that none of the L2 cache events were mapped. This is also the case for ARMv8 PMUv3, which seems a little odd considering they are defined. Thanks! Florian Fainelli (2): arm64: perf:

[PATCH 0/2] arm64: perf: Add L2 cache events for ARMv8 PMuv3 and A53

Hi, While investigating why there were no L2 cache events generated for a Cortex A53-like PMU, it turned out that none of the L2 cache events were mapped. This is also the case for ARMv8 PMUv3, which seems a little odd considering they are defined. Thanks! Florian Fainelli (2): arm64: perf:

Re: [PATCH 3/3] arm64/locking: qspinlocks and qrwlocks support

On Thu, Apr 20, 2017 at 09:23:18PM +0300, Yury Norov wrote: > On Thu, Apr 13, 2017 at 08:12:12PM +0200, Peter Zijlstra wrote: > > On Tue, Apr 11, 2017 at 01:35:04AM +0400, Yury Norov wrote: > > > > > +++ b/arch/arm64/include/asm/qspinlock.h > > > @@ -0,0 +1,20 @@ > > > +#ifndef

Re: [PATCH 3/3] arm64/locking: qspinlocks and qrwlocks support

On Thu, Apr 20, 2017 at 09:23:18PM +0300, Yury Norov wrote: > On Thu, Apr 13, 2017 at 08:12:12PM +0200, Peter Zijlstra wrote: > > On Tue, Apr 11, 2017 at 01:35:04AM +0400, Yury Norov wrote: > > > > > +++ b/arch/arm64/include/asm/qspinlock.h > > > @@ -0,0 +1,20 @@ > > > +#ifndef

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