On Fri, Oct 27, 2017 at 05:19:55PM +0200, Gregory CLEMENT wrote:
> Hi Arnd,
>
> On ven., oct. 20 2017, Arnd Bergmann wrote:
>
> > The asm-generic/unaligned.h header provides two different implementations
> > for accessing unaligned variables: the access_ok.h version used when
> > CONFIG_HAVE_E
From: Colin Ian King
There are several instances where variables are being assigned
a value and that value is never read. Hence these assignments
are redundant and can be safely removed. Cleans up clang build
warnings:
dlmast.c:234:2: warning: Value stored to 'lksb' is never read
file.c:2173:3:
Hi,
On 27-10-17 12:41, Wolfram Sang wrote:
On Fri, Oct 27, 2017 at 12:31:01PM +0200, Hans de Goede wrote:
Hi,
On 27-10-17 12:13, Hans de Goede wrote:
Hi,
On 26-10-17 22:33, Wolfram Sang wrote:
On Wed, Oct 11, 2017 at 11:41:21AM +0200, Hans de Goede wrote:
The fusb302 driver as merged in st
Slave mode driver is based on the concept of i2c-designware driver.
Signed-off-by: Juergen Fitschen
---
drivers/i2c/busses/Makefile | 3 +
drivers/i2c/busses/i2c-at91-core.c | 13 +++-
drivers/i2c/busses/i2c-at91-slave.c | 147
drivers/i2c/busses/
Some AT91 hardware has no slave mode included or only limited features
(i.e. no fifos).
Signed-off-by: Juergen Fitschen
---
drivers/i2c/busses/i2c-at91-core.c | 14 --
drivers/i2c/busses/i2c-at91.h | 5 +
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/drive
On Tue, Oct 17, 2017 at 7:17 PM, Guillaume Douézan-Grard
wrote:
> Hi Darren,
>
> On Topstar U931 Notebooks, an issue prevents the WLAN toggle key from
> being properly managed by the Embedded Controller and successfully
> disconnect the adapter. A specific ACPI method allows to toggle the WLAN
> L
On 10/26/2017 03:32 AM, Alex Williamson wrote:
On Tue, 17 Oct 2017 16:22:01 -0500
Gary R Hook wrote:
From: amd
The extent of pages specified when applying a reserved region should
include up to the last page of the range, but not the page following
the range.
Signed-off-by: Gary R Hook
---
Hi Arnd,
On ven., oct. 20 2017, Arnd Bergmann wrote:
> The asm-generic/unaligned.h header provides two different implementations
> for accessing unaligned variables: the access_ok.h version used when
> CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is set pretends that all pointers
> are in fact align
The single file i2c-at91.c has been split into core code (i2c-at91-core.c)
and master mode specific code (i2c-at91-master.c). This should enhance
maintainability and reduce ifdeffery for slave mode related code.
The code itself hasn't been touched. Shared functions only had to be made
non-static.
Based on the discussion we had on the i2c-linux list [1], I wrote a patch for
AT91 hardware and tried to fulfill the Linux I2C slave interface description
[2] as good as possible. This enables aforementioned hardware to act as an I2C
slave that can be accessed by a remote I2C master.
I have tested
Hi Philipp,
On 10/27/2017 10:06 AM, Philipp Zabel wrote:
> Hi Philippe,
>
> On Thu, 2017-10-26 at 18:09 +0200, Philippe Cornu wrote:
>> The pixel clock is optional. When available, it offers a better
>> preciseness for timing computations.
>>
>> Signed-off-by: Philippe Cornu
>> ---
>> drivers/
In order to implement slave mode support for the at91 hardware we have to
segregate all master mode specific function parts from the general parts.
The upcoming slave mode patch will call its sepcific probe resp. init
function instead of the master mode functions after the shared general
code has b
On Fri, Oct 27, 2017 at 10:33:29PM +0800, icen...@aosc.io wrote:
> 在 2017-10-16 20:09，Maxime Ripard 写道：
> > On Mon, Oct 16, 2017 at 05:41:10PM +0800, icen...@aosc.io wrote:
> > > 在 2017-10-16 17:11，Maxime Ripard 写道：
> > > > On Sat, Oct 14, 2017 at 08:29:24PM +0800, Icenowy Zheng wrote:
> > > > > A6
Hi,
The prefix should be ARM, uppercase.
On Tue, Oct 24, 2017 at 07:57:08PM +0200, Corentin Labbe wrote:
> Since dwmac-sun8i could use either an integrated PHY or an external PHY
> (which could be at same MDIO address), we need to represent this selection
> by a MDIO switch.
>
> Signed-off-by: C
On Fri, Oct 27, 2017 at 01:30:30AM -0700, syzbot wrote:
> ==
> WARNING: possible circular locking dependency detected
> 4.13.0-next-20170911+ #19 Not tainted
> --
> syz-executor2/12380 is trying
On Tue, Oct 24, 2017 at 07:57:10PM +0200, Corentin Labbe wrote:
> The original dwmac-sun8i DT bindings have some issue on how to handle
> integrated PHY and was reverted in last RC of 4.13.
> But now we have a solution so we need to get back that was reverted.
>
> This patch restore arm64 DT about
The A64 SoC features two display pipelines, one has a LCD output, the
other has a HDMI output.
Add support for simplefb for these pipelines on A64 SoC.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 31 +++
1 file changed, 31 insertions(
The A64 SoC features a DE2 CCU like the one in H5, but needs to claim a
section of SRAM (SRAM C) to be accessed.
Adds the device tree nodes for the SRAM controller and the DE2 CCU.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 34 +++
1
A64's Display Engine 2.0 needs a section of SRAM (SRAM C) to be claimed,
otherwise the whole DE2 memory zone cannot be accessed (kept to all 0).
Add binding for this, in order to make the DE2 CCU able to claim the
SRAM and enable access to the DE2 clock and reset registers.
Signed-off-by: Icenowy
The H3/H5 SoCs have a HDMI output and a TV Composite output.
Add simplefb nodes for these outputs.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 29 +
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch/ar
The DE2 CCU on Allwinner H5 SoC has a slightly different behavior than
the one on H3, so the compatible string is not set in the common DTSI
file.
Add the compatible string of H5 DE2 CCU in H5 DTSI file.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 4
1 f
As we're going to add simplefb support for Allwinner SoCs with DE2, add
suitable pipeline strings in the device tree binding.
Acked-by: Rob Herring
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Adds Rob's ACK.
.../devicetree/bindings/display/simple-framebuffer-sunxi.txt | 4
The DE2 in H3/H5 has a clock control unit in it, and the behavior is
slightly different between H3 and H5.
Add the common parts in H3/H5 DTSI, and add the compatible string in H3
DTSI.
The compatible string of H5 DE2 CCU will be added in a separated patch.
Signed-off-by: Icenowy Zheng
---
Chang
The clocks of A64/H5 SoCs in the DE2 CCU is the same as the clocks in H3
DE2 CCU rather than the A83T DE2 CCU (the parent of them is the DE
module clock).
Fix this by change the clock descriptions to use the clocks of H3.
Fixes: 763c5bd045b1 ("clk: sunxi-ng: add support for DE2 CCU")
Signed-off-b
Allwinner H3 features a DE2 CCU like the one on A83T, however the
parent of the clocks is the DE module clock, not the PLL_DE clock.
Add support for it.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 47
1 file changed, 47 insertions
The DE2 CCU is different on A83T and H3 -- the parent of the clocks on
A83T is PLL_DE but on H3 it's the DE module clock. This is not noticed
when I develop the DE2 CCU driver.
Fix the binding by using different compatibles for A83T and H3, adding
notes for the PLL_DE usage on A83T, and change the
This patchset adds support for the SimpleFB on Allwinner SoCs with
"Display Engine 2.0".
PATCH 1 to PATCH 3 are DE2 CCU fixes for H3/H5 SoCs.
PATCH 4 adds the pipeline strings for DE2 SimpleFB.
PATCH 5 to 7 adds necessary device tree nodes (DE2 CCU and SimpleFB)
for H3/H5 SoCs.
PATCH 8 to 10 ar
On Fri, Oct 27, 2017 at 09:38:44AM -0500, Rob Herring wrote:
> On Fri, Oct 27, 2017 at 02:15:02PM +0800, Kaihua Zhong wrote:
> > From: Leo Yan
> >
> > Introduce a binding for the Hi3660 mailbox controller, the mailbox is
> > used within application processor (AP), communication processor (CP),
>
Hi Andrzej,
On 10/27/2017 08:41 AM, Andrzej Hajda wrote:
> On 26.10.2017 18:09, Philippe Cornu wrote:
>> The pixel clock is optional. When available, it offers a better
>> preciseness for timing computations.
>>
>> Signed-off-by: Philippe Cornu
>> ---
>> drivers/gpu/drm/bridge/synopsys/dw-mipi-
From: Vivien Didelot
Date: Thu, 26 Oct 2017 11:22:50 -0400
> The DSA code currently has 3 bitmaps in the dsa_switch structure:
> cpu_port_mask, dsa_port_mask and enabled_port_mask.
>
> They are used to store the type of each switch port. This dates back
> from when DSA didn't have a dsa_port str
On 2017-10-19 06:27:27 [+0200], Mike Galbraith wrote:
>
> zram cleanup forgot to adjust passed argument when changing
> zram_meta_init_table_locks() to expect page count instead
> of disk size. Doing so fixes ltp inspired explosions.
Thank you. Since only v4.13-RT is affected, I merged this into
From: "Gustavo A. R. Silva"
Date: Thu, 26 Oct 2017 07:27:45 -0500
> Notice that in this particular case unlikely() is already being called
> inside BUG_ON macro.
>
> This issue was detected with the help of Coccinelle.
>
> Signed-off-by: Gustavo A. R. Silva
Applied.
On Fri, 20 Oct 2017 15:16:21 +0300
Roger Quadros wrote:
> Since v4.12, NAND subpage writes were causing a NULL pointer
> dereference on OMAP platforms (omap2-nand) using OMAP_ECC_BCH4_CODE_HW,
> OMAP_ECC_BCH8_CODE_HW and OMAP_ECC_BCH16_CODE_HW.
>
> This is because for those ECC modes, omap_calcu
From: "Gustavo A. R. Silva"
Date: Thu, 26 Oct 2017 07:16:01 -0500
> Use BUG_ON instead of if condition followed by BUG.
>
> Something to notice in this particular case is that unlikely()
> is already being called inside BUG_ON macro.
>
> This issue was detected with the help of Coccinelle.
>
>
On Thu, Oct 26 2017 at 6:07:01 pm BST, Dongjiu Geng
wrote:
> For this matching, current code using the {I,D}FSC
> range to match kvm_vcpu_trap_get_fault_type() return
> value, but kvm_vcpu_trap_get_fault_type() only return
> the part {I,D}FSC instead of whole, so fix this issue
>
> Value T
Hi Rob,
On 10/27/2017 04:38 PM, Rob Herring wrote:
> On Thu, Oct 26, 2017 at 06:12:36PM +0200, Philippe Cornu wrote:
>> Add the DPI/RGB input pixel clock in mandatory properties
>> because it really offers a better preciseness for timing
>> computations.
>> Note: Fix also the DSI panel example whe
On 10/27/2017 04:02 PM, Gavin Guo wrote:
> Hi Hannes,
>
> Thank you for looking into the issue. If there is anything I can help
> to test the patch? I appreciate your help. Thank you.
>
If you had checked linux-scsi you would have found this patch:
'[PATCH] mptsas: Fixup device hotplug for VMWare
In particular, fixes some over-indented if statement bodies as well as a
couple lines indented with spaces. checkpatch.pl now reports no warnings
on this file other than 80 character warnings.
Signed-off-by: Stephen Brennan
---
V2 also fixes an overlooked indentation error that checkpatch didn't
> -Original Message-
> From: Dan Carpenter [mailto:dan.carpen...@oracle.com]
> Sent: Friday, October 27, 2017 5:30 PM
> To: Bogdan Purcareata
> Cc: Ruxandra Ioana Radulescu ;
> gre...@linuxfoundation.org; linux-kernel@vger.kernel.org;
> de...@driverdev.osuosl.org
> Subject: Re: [PATCH 4/5]
On 10/22/2017 11:40 PM, Anna-Maria Gleixner wrote:
From: Thomas Gleixner
Switch the timer to HRTIMER_MODE_SOFT, which executed the timer
callback in softirq context and remove the hrtimer_tasklet.
Signed-off-by: Thomas Gleixner
Signed-off-by: Anna-Maria Gleixner
Cc: Oliver Hartkopp
Acked-
> -Original Message-
> From: Dan Carpenter [mailto:dan.carpen...@oracle.com]
> Sent: Friday, October 27, 2017 5:34 PM
> To: Bogdan Purcareata
> Cc: Ruxandra Ioana Radulescu ;
> gre...@linuxfoundation.org; linux-kernel@vger.kernel.org;
> de...@driverdev.osuosl.org
> Subject: Re: [PATCH 3/5]
From: Eric Auger
This patch selects IRQ_BYPASS_MANAGER and HAVE_KVM_IRQ_BYPASS
configs for ARM/ARM64.
kvm_arch_has_irq_bypass() now is implemented and returns true.
As a consequence the irq bypass consumer will be registered for
ARM/ARM64 with the forwarding callbacks:
- stop/start: halt/resume
From: Eric Auger
We want to reuse the core of the map/unmap functions for IRQ
forwarding. Let's move the computation of the hwirq in
kvm_vgic_map_phys_irq and pass the linux IRQ as parameter.
the host_irq is added to struct vgic_irq.
We introduce kvm_vgic_map/unmap_irq which take a struct vgic_i
On Fri, Oct 27, 2017 at 07:23:58AM -0700, Joe Perches wrote:
> On Fri, 2017-10-27 at 11:32 +0300, Dan Carpenter wrote:
> > But then ssi_buffer_mgr_copy_scatterlist_portion() is still not indented
> > correctly.
Yeah, I don't know how I missed it. I'll send a new version of the patch
out momentaril
On Tue, Oct 24, 2017 at 07:57:06PM +0200, Corentin Labbe wrote:
> This patch add documentation about the MDIO switch used on sun8i-h3-emac
> for integrated PHY.
>
> Signed-off-by: Corentin Labbe
> ---
> .../devicetree/bindings/net/dwmac-sun8i.txt| 145
> +++--
> 1 file c
On Tue, Oct 24, 2017 at 02:15:43PM -0400, Jim Quinlan wrote:
> The DT bindings description of the Brcmstb PCIe device is described. This
> node can be used by almost all Broadcom settop box chips, using
> ARM, ARM64, or MIPS CPU architectures.
"dt-bindings: pci: ..." for the subject please.
>
>
On Wed, Oct 25, 2017 at 10:07:58AM +0900, Kunihiko Hayashi wrote:
> DT bindings for the AVE ethernet controller found on Socionext's
> UniPhier platforms.
>
> Signed-off-by: Kunihiko Hayashi
> Signed-off-by: Jassi Brar
> ---
> .../bindings/net/socionext,uniphier-ave4.txt | 48
> +
On Fri, 2017-10-27 at 15:58 +0200, Peter Zijlstra wrote:
> On Fri, Oct 27, 2017 at 05:06:25AM -0700, tip-bot for Frederic Weisbecker
> wrote:
> > + isolcpus= [KNL,SMP] Isolate a given set of CPUs from disturbance.
> > + Format: [flag-list,]
> > +
> > + S
On Wed, Oct 25, 2017 at 12:04:21PM -0700, Andrey Smirnov wrote:
> Add Device Tree bindings for RAVE SP watchdog drvier - an MFD cell of
> parent RAVE SP driver (documented in
> Documentation/devicetree/bindings/mfd/zii,rave-sp.txt).
>
> Cc: linux-kernel@vger.kernel.org
> Cc: devicet...@vger.kernel
On Thu, Oct 26, 2017 at 06:12:36PM +0200, Philippe Cornu wrote:
> Add the DPI/RGB input pixel clock in mandatory properties
> because it really offers a better preciseness for timing
> computations.
> Note: Fix also the DSI panel example where "ref" & "pclk"
> clocks were swapped.
>
> Signed-off-b
On Thu, Oct 26, 2017 at 01:48:08PM +0200, Philippe Cornu wrote:
> ltdc can have up to 2 endpoints:
> - dpi external gpios: for rgb panels or external bridge ICs.
> - dpi internal ios: connected internally to dsi.
>
> Note: Refer to the reference manual to know if the dsi is
> present on your dev
On Fri, Oct 27, 2017 at 02:15:02PM +0800, Kaihua Zhong wrote:
> From: Leo Yan
>
> Introduce a binding for the Hi3660 mailbox controller, the mailbox is
> used within application processor (AP), communication processor (CP),
> HIFI and MCU, etc.
>
> Cc: John Stultz
> Cc: Guodong Xu
> Cc: Haojia
On Thu, Oct 26, 2017 at 09:28:37PM +0800, Jeffy Chen wrote:
> Currently we are considering the first irq as the PCI interrupt pin,
> but a pci device may have multiple interrupts(e.g. PCIe WAKE# pin).
>
> Only parse the PCI interrupt pin when the irq is unnamed or named as
> "pci".
>
> Signed-off
On Thu, Oct 26, 2017 at 03:28:54PM -0700, Chris Lew wrote:
> Virtual GLINK channels may know what throughput to expect from a
> remoteproc. An intent advertises to the remoteproc this channel is
> ready to receive data. Allow a channel to define the size and amount of
> intents to be prequeued.
>
On Thu, Oct 26, 2017 at 02:49:46PM +0200, Lothar Waßmann wrote:
> When switching the backlight on, the LCD may need some time to adjust
> to the configured PWM duty cycle. Add a configurable delay between
> configuring the PWM and enabling the backlight regulator to account
> for this.
>
> Signed-
On Wed, Oct 25, 2017 at 11:27:43AM +0200, Fabrice Gasnier wrote:
> STM32H7 ADC channels may be configured either as single-ended or
> differential.
> Add 'st,adc-diff-channels' property to support differential channels.
> Differential channels are defined as a pair of positive and negative
> inputs
On Wed, Oct 25, 2017 at 07:10:59PM +0200, Ludovic Barre wrote:
> From: Ludovic Barre
>
> This patch updates stm32-exti documentation with stm32h7-exti
> compatible string.
>
> Signed-off-by: Ludovic Barre
> ---
> .../devicetree/bindings/interrupt-controller/st,stm32-exti.txt| 4
> +++-
The whole MSI injection process is fairly monolithic. An MSI write
gets turned into an injected LPI in one swift go. But this is actually
a more fine-grained process:
- First, a virtual ITS gets selected using the doorbell address
- Then the DevID/EventID pair gets translated into an LPI
- Finally
On Wed, Oct 25, 2017 at 01:12:13PM +0800, rick wrote:
Commit msg?
> Signed-off-by: rick
> Signed-off-by: rick
Need a full name.
> Signed-off-by: Greentime Hu
S-o-b should be in chronological order of who touched the code. And the
sender should be last.
> ---
> .../bindings/timer/andeste
2017-10-27 15:58 UTC+02:00, Peter Zijlstra :
> On Fri, Oct 27, 2017 at 05:06:25AM -0700, tip-bot for Frederic Weisbecker
> wrote:
>> +isolcpus= [KNL,SMP] Isolate a given set of CPUs from disturbance.
>> +Format: [flag-list,]
>> +
>> +Specify one or
The GICv4 support introduces a hard dependency between the KVM
core and the ITS infrastructure. arm64 already selects it at
the architecture level, but 32bit doesn't. In order to avoid
littering the kernel with #ifdefs, let's just select the whole
of the GICv3 suport code.
You know you want it.
A
In order to control the GICv4 view of virtual CPUs, we rely
on an irqdomain allocated for that purpose. Let's add a couple
of helpers to that effect.
At the same time, the vgic data structures gain new fields to
track all this... erm... wonderful stuff.
The way we hook into the vgic init is sligh
Add a new has_gicv4 field in the global VGIC state that indicates
whether the HW is GICv4 capable, as a per-VM predicate indicating
if there is a possibility for a VM to support direct injection
(the above being true and the VM having an ITS).
Reviewed-by: Christoffer Dall
Signed-off-by: Marc Zyn
Let's use the irq bypass mechanism introduced for platform device
interrupts to intercept the virtual PCIe endpoint configuration
and establish our LPI->VLPI mapping.
Reviewed-by: Christoffer Dall
Signed-off-by: Marc Zyngier
---
include/kvm/arm_vgic.h | 8
virt/kvm/arm/arm.c
Miklos Szeredi wrote:
> Also, how about moving calls to vfs_parse_fs_option() into filesystem
> code? Even those options are not generic, some filesystem wants
> this, some that. It's just a historical accident that those are set
> with MS_FOO and not "foo". Filesystems that don't have any op
When the guest issues an affinity change, we need to tell the physical
ITS that we're now targetting a new vcpu. This is done by extracting
the current mapping, updating the target, and reapplying the mapping.
Reviewed-by: Christoffer Dall
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vgic/vgic
Handling CLEAR is pretty easy. Just ask the ITS driver to clear
the corresponding pending bit (which will turn into a CLEAR
command on the physical side).
Acked-by: Christoffer Dall
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vgic/vgic-its.c | 4
1 file changed, 4 insertions(+)
diff --gi
On Fri, Oct 27, 2017 at 02:31:22PM +, Bogdan Purcareata wrote:
> > -Original Message-
> > From: Dan Carpenter [mailto:dan.carpen...@oracle.com]
> > Sent: Friday, October 27, 2017 5:27 PM
> > To: Bogdan Purcareata
> > Cc: Ruxandra Ioana Radulescu ;
> > gre...@linuxfoundation.org; linux-
From: Jose Abreu
Date: Thu, 26 Oct 2017 10:07:12 +0100
> According to DWMAC databook the first queue operating mode
> must always be in DCB.
>
> As MTL_QUEUE_DCB = 1, we need to always set the first queue
> operating mode to DCB otherwise driver will think that queue
> is in AVB mode (because MT
Upon updating a property, we propagate it all the way to the physical
ITS, and ask for an INV command to be executed there.
Acked-by: Christoffer Dall
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vgic/vgic-its.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/virt/kvm/arm/vgic/vgic-its.c
在 2017-10-16 20:09，Maxime Ripard 写道：
On Mon, Oct 16, 2017 at 05:41:10PM +0800, icen...@aosc.io wrote:
在 2017-10-16 17:11，Maxime Ripard 写道：
> On Sat, Oct 14, 2017 at 08:29:24PM +0800, Icenowy Zheng wrote:
> > A64's Display Engine 2.0 needs a section of SRAM (SRAM C) to be
> > claimed.
>
> Why?
A
When a vPE exits, the pending_last flag is set when there are
pending VLPIs stored in the pending table. Similarily, we set
this flag when a doorbell interrupt fires, as it indicates the
same condition.
Let's update kvm_vgic_vcpu_pending_irq() to account for that
flag as well, making a vcpu runnab
When a vPE is not running, a VLPI being made pending results in a
doorbell interrupt being delivered. Let's handle this interrupt
and update the pending_last flag that indicates that VLPIs are
pending. The corresponding vcpu is also kicked into action.
Special care is taken to prevent the doorbell
The GICv4 architecture doesn't make it easy for save/restore to
work, as it doesn't give any guarantee that the pending state
is written into the pending table.
So let's not take any chance, and let's return an error if
we encounter any LPI that has the HW bit set. In order for
userspace to distin
The redistributor needs to be told which vPE is about to be run,
and tells us whether there is any pending VLPI on exit.
Let's add the scheduling calls to the vgic flush/sync functions,
allowing the VLPIs to be delivered to the guest.
Reviewed-by: Christoffer Dall
Signed-off-by: Marc Zyngier
--
> -Original Message-
> From: Dan Carpenter [mailto:dan.carpen...@oracle.com]
> Sent: Friday, October 27, 2017 5:27 PM
> To: Bogdan Purcareata
> Cc: Ruxandra Ioana Radulescu ;
> gre...@linuxfoundation.org; linux-kernel@vger.kernel.org;
> de...@driverdev.osuosl.org
> Subject: Re: [PATCH 3/5]
All it takes is the has_v4 flag to be set in gic_kvm_info
as well as "kvm-arm.vgic_v4_enable=1" being passed on the
command line for GICv4 to be enabled in KVM.
Acked-by: Christoffer Dall
Signed-off-by: Marc Zyngier
---
Documentation/admin-guide/kernel-parameters.txt | 4
virt/kvm/arm/vgi
On Fri, Oct 27, 2017 at 02:11:35PM +, Bogdan Purcareata wrote:
> @@ -93,10 +100,10 @@
> * buffers large enough to allow building an skb around them and also account
> * for alignment restrictions
> */
> -#define DPAA2_ETH_BUF_RAW_SIZE \
> +#define DPAA2_ETH_BUF_RAW_SIZE(priv) \
> (D
From: Egil Hjelmeland
Date: Thu, 26 Oct 2017 11:00:47 +0200
> When CPU transmit directly to port using tag, the LAN9303 does not
> learn MAC addresses received on the CPU port into the ALR table.
> ALR learning is performed only when transmitting using ALR lookup.
>
> Solution:
> If the two exte
We so far allocate the doorbell interrupts without taking any
special measure regarding the affinity of these interrupts. We
simply move them around as required when the vcpu gets scheduled
on a different CPU.
But that's counting without userspace (and the evil irqbalance) that
can try and move th
On 10/24/2017 09:41 AM, C.Wehrmeyer wrote:
> On 2017-10-23 20:02, Michal Hocko wrote:
>> On Mon 23-10-17 19:52:27, C.Wehrmeyer wrote:
>> [...]
or you can mmap a larger block and
munmap the initial unaligned part.
>>>
>>> And how is that supposed to be transparent? When I hear "transparent
Yet another braindump so I can free some cells...
Acked-by: Christoffer Dall
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vgic/vgic-v4.c | 67 +
1 file changed, 67 insertions(+)
diff --git a/virt/kvm/arm/vgic/vgic-v4.c b/virt/kvm/arm/vgic/vgic-v4.c
i
In order for VLPIs to be delivered to the guest, we must make
sure that the cpuif is always enabled, irrespective of the
presence of virtual interrupt in the LRs.
Acked-by: Christoffer Dall
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/hyp/vgic-v3-sr.c | 9 ++---
1 file changed, 6 insertions
The doorbell interrupt is only useful if the vcpu is blocked on WFI.
In all other cases, recieving a doorbell interrupt is just a waste
of cycles.
So let's only enable the doorbell if a vcpu is getting blocked,
and disable it when it is unblocked. This is very similar to
what we're doing for the b
The current implementation of MOVALL doesn't allow us to call
into the core ITS code as we hold a number of spinlocks.
Let's try a method used in other parts of the code, were we copy
the intids of the candicate interrupts, and then do whatever
we need to do with them outside of the critical secti
Since when updating the properties one LPI at a time, there is no
need to perform an INV each time we read one. Instead, we rely
on the final VINVALL that gets sent to the ITS to do the work.
Acked-by: Christoffer Dall
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vgic/vgic-its.c | 15 +-
When freeing an LPI (on a DISCARD command, for example), we need
to unmap the VLPI down to the physical ITS level.
Acked-by: Christoffer Dall
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vgic/vgic-its.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/virt/kvm/arm/vgic/v
If the guest issues an INT command targetting a VLPI, let's
call into the irq_set_irqchip_state() helper to make it pending
on the physical side.
This works just as well if userspace decides to inject an interrupt
using the normal userspace API...
Acked-by: Christoffer Dall
Signed-off-by: Marc Z
In order help integrating the vITS code with GICv4, let's add
a new helper that deals with updating the affinity of an LPI,
which will later be augmented with super duper extra GICv4
goodness.
Reviewed-by: Christoffer Dall
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vgic/vgic-its.c | 20 ++
The way we call kvm_vgic_destroy is a bit bizarre. We call it
*after* having freed the vcpus, which sort of defeats the point
of cleaning up things before that point.
Let's move kvm_vgic_destroy towards the beginning of kvm_arch_destroy_vm,
which seems more sensible.
Acked-by: Christoffer Dall
S
So far, we require the hypervisor to update the VLPI properties
once the the VLPI mapping has been established. While this
makes it easy for the ITS driver, it creates a window where
an incoming interrupt can be delivered with an unknown set
of properties. Not very nice.
Instead, let's add a "prop
This series implements full support for GICv4 in KVM, bringing direct
injection of MSIs to arm and arm64, assuming you have the right
hardware (which is quite unlikely).
To get an idea of the design, I'd recommend you start with commit
7954907bedaf as well as patch #26, which try to shed some ligh
On Fri, Oct 27, 2017 at 02:11:34PM +, Bogdan Purcareata wrote:
> When configuring the Tx buffer layout, the software annotation size is
> mentioned, and MC accounts for it when configuring the frame
> tx_data_offset. No need to handle it in the driver as well.
>
The impact is that we allocat
From: Jose Abreu
Date: Thu, 26 Oct 2017 09:51:33 +0100
> According to DT bindings documentation we are expecting a
> property called "snps,read-requests" but we are parsing
> instead a property called "read,read-requests".
>
> This is clearly a typo. Fix it.
>
> Signed-off-by: Jose Abreu
Appl
On Fri, 2017-10-27 at 11:32 +0300, Dan Carpenter wrote:
> On Thu, Oct 26, 2017 at 06:53:42PM -0700, Stephen Brennan wrote:
> > In particular, fixes some over-indented if statement bodies as well as a
> > couple lines indented with spaces. checkpatch.pl now reports no warnings
> > on this file other
Hi Bjorn,
Thanks for reviewing!
On 10/26/2017 07:28 AM, Bjorn Andersson wrote:
> On Thu 21 Sep 09:49 PDT 2017, Georgi Djakov wrote:
>
>> Move the structure shared by the APCS IPC device and its subdevices
>> into a separate header file.
>>
>
> As you're creating the apcs regmap with devm_regmap
On Fri, Oct 27, 2017 at 09:43:11AM +0200, Jiri Olsa wrote:
> Reset header size for namespace events, otherwise
> it only gets bigger in ctx iterations.
>
> Cc: Hari Bathini
> Link: http://lkml.kernel.org/n/tip-nlo4gonz9d4guyb8153uk...@git.kernel.org
> Signed-off-by: Jiri Olsa
Fixes: e422267322c
On Fri, Oct 27, 2017 at 02:33:48PM +0200, Borislav Petkov wrote:
> On Fri, Oct 27, 2017 at 07:42:45PM +0800, zhouchengming wrote:
> > This is a real bug happened on one of our machines, below is the calltrace.
> > We can see the trigger is at alternatives_text_reserved+0x20/0x80, and
> > encounter
The WRIOP hardware block v1.0.0 (found on LS2080A board)
requires data in RX buffers to be aligned to 256B, but
newer revisions (e.g. on LS2088A, LS1088A) only require
64B alignment.
Check WRIOP version and decide at runtime which alignment
requirement to configure for ingress buffers.
Signed-off
The needed headroom that we ask the stack to reserve for us in TX
skbs is larger than the headroom available in RX frames, which
leads to skb reallocations in forwarding scenarios involving two
DPNI interfaces.
Configure the hardware to reserve some extra space in the RX
frame headroom to avoid th
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