On Thu, Feb 01, 2018 at 01:27:30PM +0300, Kirill A. Shutemov wrote:
> > It's non-trivial to do this because at minimum a page fault has to check
> > if there is a potential promotion candidate by checking the PTEs around
> > the faulting address searching for a correctly-aligned base page that is
On 1/31/2018 4:00 AM, Bryan O'Donoghue wrote:
> From: Rui Miguel Silva
>
> Add CAAM device node to the i.MX7s device tree.
>
> Signed-off-by: Rui Miguel Silva
> Cc: Shawn Guo
> Cc: Sascha Hauer
> Cc:
Hi Arnd,
On Thu, Feb 1, 2018 at 12:46 PM, Arnd Bergmann wrote:
> On Thu, Feb 1, 2018 at 11:21 AM, Geert Uytterhoeven
> wrote:
>> Gcc versions before 4.4 do not recognize the __optimize__ compiler
>> attribute:
>>
>> warning: ‘__optimize__’ attribute
Ingo pointed out that:
"The "memory model" name is overly generic, ambiguous and somewhat
misleading, as we usually mean the virtual memory layout/model
when we say "memory model". GCC too uses it in that sense [...]"
Make it clearer that, in the context of tools/memory-model/, the term
On Wed, Jan 17, 2018 at 12:31:57PM +0100, Mathieu Malaterre wrote:
> Replace pointer comparison to 0 with NULL in prepare_ftrace_return
> to improve code readability. Identified with coccinelle script
> 'badzero.cocci'.
>
> Signed-off-by: Mathieu Malaterre
I've applied to my
On 01/02/18 12:32, Robin Murphy wrote:
> On 01/02/18 11:46, Marc Zyngier wrote:
>> Since PSCI 1.0 allows the SMCCC version to be (indirectly) probed,
>> let's do that at boot time, and expose the version of the calling
>> convention as part of the psci_ops structure.
>>
>> Acked-by: Lorenzo
[CC Kees and Linus - for your background, we are talking about failures
http://lkml.kernel.org/r/20180107090229.gb24...@dhcp22.suse.cz
introduced by http://lkml.kernel.org/r/20171213092550.2774-3-mho...@kernel.org
Debugging has shown that load_elf_binary tries to map elf segment over
an
On 29/01/18 16:49, Stephen Boyd wrote:
> On some platforms there's an ITS available but it's not enabled
> because reading or writing the registers is denied by the
> firmware. In fact, reading or writing them will cause the system
> to reset.
Wow. Funky.
> We could remove the node from DT in
On Thu, 01 Feb 2018 13:59:45 +,
Ard Biesheuvel wrote:
>
> On 1 February 2018 at 11:46, Marc Zyngier wrote:
> > ARM has recently published a SMC Calling Convention (SMCCC)
> > specification update[1] that provides an optimised calling convention
> > and optional,
On 2018/2/1 6:15, Jaegeuk Kim wrote:
> On 01/31, Chao Yu wrote:
>> On 2018/1/31 10:02, Jaegeuk Kim wrote:
>>> What if we want to add more entries in addition to node_checksum? Do we have
>>> to add a new feature flag at every time? How about adding a layout value
>>> instead
>>
>> Hmm.. for
On 02/01/18 at 05:49am, Dave Hansen wrote:
> On 02/01/2018 02:16 AM, Kirill A. Shutemov wrote:
> > On Thu, Feb 01, 2018 at 03:19:56PM +0800, Baoquan He wrote:
> >> In sparse_init(), we allocate usemap_map and map_map which are pointer
> >> array with the size of NR_MEM_SECTIONS. The memory
On 01/02/2018 08:22, Stephen Rothwell wrote:
> Hi Christoffer,
>
> On Thu, 1 Feb 2018 11:47:07 +0100 Christoffer Dall
> wrote:
>>
>> While the suggested fix is functional it does result in some code
>> duplication, and the better resolution is the following:
>
>
On Wed, Jan 31, 2018 at 2:05 PM, wrote:
> From: Frank Rowand
>
> Create a cache of the nodes that contain a phandle property. Use this
> cache to find the node for a given phandle value instead of scanning
> the devicetree to find the node. If
On Wed, Jan 31, 2018 at 8:27 AM, Eric Biggers wrote:
>
> Also Dmitry, syzbot seems to be grouping together unrelated bugs under the
> refcount_t WARNINGs; maybe those should be on a blacklist?
Not a blacklist, we need a proper way of extracting the offending
caller like it's
On Thu, Feb 1, 2018 at 3:48 PM, Mark Brown wrote:
> On Thu, Feb 01, 2018 at 03:20:38PM +0200, Andy Shevchenko wrote:
>> On Thu, Feb 1, 2018 at 11:05 AM, Daniel Baluta wrote:
>
>> >> > Signed-off-by: Junichi Wakasugi
>>
On Thu, Feb 01, 2018 at 10:48:52AM +0100, Julia Lawall wrote:
> Some files use both a non-devm allocation and a devm_allocation. Don't
> complain about a free when the same function contains a non-devm
> allocation.
>
> Signed-off-by: Julia Lawall
>
That's surprising...
The documentation was mentioning the "future SCHED EDF" as the
solution for fine-grained control of deadline/period. This patch
updates this citing the (now) existing SCHED_DEADLINE.
Signed-off-by: Daniel Bristot de Oliveira
Cc: Jonathan Corbet
Cc: Juri Lelli
Commit fd8aa9095a95 ("xen: optimize xenbus driver for multiple concurrent
xenstore accesses") optimized xenbus concurrent accesses but in doing so
may have broke UABI of /dev/xen/xenbus. Through /dev/xen/xenbus
applications are in charge of exchange xenbus message exchange with the
correct header
On Tue, Jan 16, 2018 at 03:22:18PM +, Don Brace wrote:
> > -Original Message-
> > From: Laurence Oberman [mailto:lober...@redhat.com]
> > Sent: Tuesday, January 16, 2018 7:29 AM
> > To: Thomas Gleixner ; Ming Lei
> > Cc: Christoph Hellwig
Hi Niklas,
On Thursday 01 February 2018 04:46 PM, Niklas Cassel wrote:
> On Thu, Feb 01, 2018 at 11:10:54AM +, Lorenzo Pieralisi wrote:
>> On Thu, Feb 01, 2018 at 09:56:09AM +0100, Niklas Cassel wrote:
>>> On Thu, Feb 01, 2018 at 10:51:14AM +1100, Stephen Rothwell wrote:
Hi Bjorn,
A couple of things that have been lurking in the "shall we do this?" area
of my git tree for a while, and I think we probably should...
David Woodhouse (1):
x86/retpoline: No retpolines for built-in __init functions
KarimAllah Ahmed (1):
x86: Simplify spectre_v2 command line parsing
There's no point in building init code with retpolines, since it runs before
any potentially hostile userspace does. And before the retpoline is actually
ALTERNATIVEd into place, for much of it.
Signed-off-by: David Woodhouse
---
include/linux/init.h | 9 -
1 file
Peter Zijlstra wrote:
> On Mon, Jan 29, 2018 at 08:47:20PM +0900, Tetsuo Handa wrote:
> > Peter Zijlstra wrote:
> > > On Sun, Jan 28, 2018 at 02:55:28PM +0900, Tetsuo Handa wrote:
> > > > This warning seems to be caused by commit d92a8cfcb37ecd13
> > > > ("locking/lockdep: Rework FS_RECLAIM
On Saturday 20 January 2018 10:43 PM, David Lechner wrote:
> This adds platform-specific declarations for the PSC clocks on TI
> DM365 based systems.
>
> Signed-off-by: David Lechner
Apart from comment given on 13/41 that applies here:
Reviewed-by: Sekhar Nori
RTM_NEWLINK supports the IFLA_IF_NETNSID property since
5bb8ed075428b71492734af66230aa0c07fcc515 so we should not error out
when it is passed.
Signed-off-by: Christian Brauner
---
net/core/rtnetlink.c | 3 ---
1 file changed, 3 deletions(-)
diff --git
On Tue, 30 Jan 2018, Enric Balletbo Serra wrote:
> Hi,
>
> 2017-12-01 13:06 GMT+01:00 Enric Balletbo i Serra
> :
> > Before this patch the enable signal was set before the PWM signal and
> > vice-versa on power off. This sequence is wrong, at least, it is on
> >
Hi Markus,
On 1 February 2018 at 20:17, Marcus Folkesson
wrote:
> Hi Baolin,
>
> On Tue, Jan 30, 2018 at 08:07:43PM +0800, Baolin Wang wrote:
>> The Spreadtrum SC9860 platform GPIO controller contains 16 groups and
>> each group contains 16 GPIOs. Each GPIO can set
On 1 February 2018 at 20:22, Marcus Folkesson
wrote:
> On Thu, Feb 01, 2018 at 11:08:46AM +0800, Baolin Wang wrote:
>> On 31 January 2018 at 22:23, Andy Shevchenko
>> wrote:
>> > On Wed, Jan 31, 2018 at 4:01 AM, Baolin Wang
Add documentation for core and hardware specific infiniband interfaces.
The descriptions have been collected from git commit logs, reading
through code and data sheets. Some drivers have incomplete doc and are
annotated with the comment '[to be documented]'.
Signed-off-by: Aishwarya Pant
On Thu, Feb 01, 2018 at 02:29:09PM +0100, Peter Zijlstra wrote:
> On Thu, Feb 01, 2018 at 09:27:50PM +0900, Stafford Horne wrote:
> > I tried to clarify some of this in the spec v1.2 [0] which help formalize
> > some of
> > the techniques we used for the SMP implementation. Its probably not
> >
LPTimer pwm cells should be updated to 3, to allow initialization of
channel, period and polarity.
Signed-off-by: Fabrice Gasnier
---
arch/arm/boot/dts/stm32h743.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/stm32h743.dtsi
Add missing generic #pwm-cells on STM32 LPTimer to allow initialization
of channel, period and polarity.
Fabrice Gasnier (1):
ARM: dts: stm32: update pwm-cells for LPTimer on stm32h743
Gerald Baeza (2):
dt-bindings: pwm-stm32-lp: add #pwm-cells
pwm: stm32: LPTimer: use 3 cells xlate
From: Gerald Baeza
STM32 Low-Power Timer supports generic 3 cells pwm to encode
PWM number, period and polarity.
Signed-off-by: Gerald Baeza
Signed-off-by: Fabrice Gasnier
---
From: Gerald Baeza
STM32 Low-Power Timer supports generic 3 cells pwm to encode
PWM number, period and polarity.
Signed-off-by: Gerald Baeza
Signed-off-by: Fabrice Gasnier
---
drivers/pwm/pwm-stm32-lp.c | 2 ++
1 file changed,
On 02/01/2018 06:19 AM, Baoquan He wrote:
>
> I suppose these functions changed here are only called during system
> bootup, namely in paging_init(). Hot-add memory goes in a different
> path, __add_section() -> sparse_add_one_section(), different called
> functions.
But does this keep those
On Thu, 2018-02-01 at 13:37 +0100, Sergio Lopez wrote:
> "restrict_smt" is an optional security feature that, when enabled,
> automatically adjusts the cpus_allowed mask of user tasks with CFS
> policies, forcing them to run on the first SMT thread of each core.
>
> This security feature prevents
On 02/01/18 at 06:15am, Dave Hansen wrote:
> On 01/31/2018 11:19 PM, Baoquan He wrote:
> > for_each_present_section_nr(0, pnum) {
> > + struct mem_section *ms;
> > + ms = __nr_to_section(pnum);
> > usemap = usemap_map[pnum];
> > - if (!usemap)
> > +
From: Colin King
Date: Wed, 31 Jan 2018 16:14:25 +
> From: Colin Ian King
>
> Variable head is initialized to a value that is never read and is
> being updated to a new value a few lines later, hence this
> initialization is redundant and
On 01/02/18 11:00, Himanshu Jha wrote:
In scpsys_probe function, return value of of_match_device function which
returns null is dereferenced without checking. Therefore, add a check for
potential null dereference.
Detected by CoverityScan, CID#1424087 "Dereference null return value"
Fixes:
Most callers of put_cmsg() use a "sizeof(foo)" for the length argument.
Within put_cmsg(), a copy_to_user() call is made with a dynamic size, as a
result of the cmsg header calculations. This means that hardened usercopy
will examine the copy, even though it was technically a fixed size and
should
Hi Daniel,
On 01/02/18 11:31, Daniel Bristot de Oliveira wrote:
> The documentation was mentioning the "future SCHED EDF" as the
> solution for fine-grained control of deadline/period. This patch
> updates this citing the (now) existing SCHED_DEADLINE.
>
> Signed-off-by: Daniel Bristot de
>> * Do we agree that a proper size determination is essential for every
>> condition in the discussed SmPL rules together with forwarding
>> this information?
>
> No. I don't mind a few false positives.
I have got other source code analysis expectations there.
This SmPL script contains
In order to call into the firmware to apply workarounds, it is
useful to find out whether we're using HVC or SMC. Let's expose
this through the psci_ops.
Acked-by: Lorenzo Pieralisi
Signed-off-by: Marc Zyngier
---
drivers/firmware/psci.c | 28
Function identifiers are a 32bit, unsigned quantity. But we never
tell so to the compiler, resulting in the following:
4ac: b26187e0mov x0, #0x8001
We thus rely on the firmware narrowing it for us, which is not
always a reasonable expectation.
Cc:
PSCI 1.0 can be trivially implemented by having PSCI 0.2 and
the FEATURES call. Of, and returning 1.0 as the PSCI version.
We happily ignore everything else, as it is optional.
Signed-off-by: Marc Zyngier
---
include/kvm/arm_psci.h | 1 +
virt/kvm/arm/psci.c| 43
On Thu, Feb 1, 2018 at 11:26 AM, Geert Uytterhoeven
wrote:
> With gcc-4.1.2:
>
> net/ipv4/inet_hashtables.c: In function ‘inet_unhash’:
> net/ipv4/inet_hashtables.c:628: warning: ‘ilb’ may be used uninitialized
> in this function
>
> While this is a false positive,
Now that we've standardised on SMCCC v1.1 to perform the branch
prediction invalidation, let's drop the previous band-aid.
If vendors haven't updated their firmware to do SMCCC 1.1, they
haven't updated PSCI either, so we don't loose anything.
Signed-off-by: Marc Zyngier
Add the detection and runtime code for ARM_SMCCC_ARCH_WORKAROUND_1.
It is lovely. Really.
Signed-off-by: Marc Zyngier
---
arch/arm64/kernel/bpi.S| 20 +
arch/arm64/kernel/cpu_errata.c | 68 +-
2 files changed, 87
On 01/02/2018 at 16:30:22 +0530, Himanshu Jha wrote:
> In scpsys_probe function, return value of of_match_device function which
> returns null is dereferenced without checking. Therefore, add a check for
> potential null dereference.
>
> Detected by CoverityScan, CID#1424087 "Dereference null
Hi Baolin,
On Tue, Jan 30, 2018 at 08:07:43PM +0800, Baolin Wang wrote:
> The Spreadtrum SC9860 platform GPIO controller contains 16 groups and
> each group contains 16 GPIOs. Each GPIO can set input/output and has
> the interrupt capability.
>
> Signed-off-by: Baolin Wang
On Saturday 20 January 2018 10:43 PM, David Lechner wrote:
> This adds platform-specific declarations for the PSC clocks on TI
> DM646x based systems.
>
> Signed-off-by: David Lechner
Reviewed-by: Sekhar Nori
Thanks,
Sekhar
On Wed, Jan 31, 2018 at 02:26:10PM +0100, Peter Zijlstra wrote:
> On Wed, Jan 31, 2018 at 01:17:37PM +, Will Deacon wrote:
> > On Wed, Jan 31, 2018 at 02:00:34PM +0100, Peter Zijlstra wrote:
> > >
> > > While looking through the qspinlock users, I stumbled upon openrisc and
> > > being
Hi Will, Thanks for your quick reply.
On 02/01/2018 04:33 AM, Will Deacon wrote:
> Hi Shanker,
>
> On Wed, Jan 31, 2018 at 06:03:42PM -0600, Shanker Donthineni wrote:
>> A DMB instruction can be used to ensure the relative order of only
>> memory accesses before and after the barrier. Since
On Thu, Feb 01, 2018 at 01:33:35PM +0100, Peter Zijlstra wrote:
> I think you want to go allocate sched_domain_shared for the MC level and
> use that, much like sd_llc_shared.
Also, you'd want to try and get performance numbers for something like
Power8, which has SMT8 and fairly expensive atomic
On Thu, Feb 01, 2018 at 03:20:38PM +0200, Andy Shevchenko wrote:
> On Thu, Feb 1, 2018 at 11:05 AM, Daniel Baluta wrote:
> >> > Signed-off-by: Junichi Wakasugi
> >> > Signed-off-by: Mihai Serban
> >> >
> -struct klp_object *klp_get_or_add_object(struct klp_patch *patch,
> +static struct klp_object *klp_get_or_add_object(struct klp_patch *patch,
> struct klp_object *old_obj)
A nit, but this change belongs to 3/6, doesn't it?
> {
> struct
On Thu, 25 Jan 2018, Petr Mladek wrote:
> Hi,
>
> the atomic replace allows to create cumulative patches. They
> are useful when you maintain many livepatches and want to remove
> one that is lower on the stack. In addition it is very useful when
> more patches touch the same function and there
On Thu 01-02-18 08:43:34, Anshuman Khandual wrote:
[...]
> $dmesg | grep elf_brk
> [9.571192] elf_brk 10030328 elf_bss 1003
>
> static int load_elf_binary(struct linux_binprm *bprm)
> -
>
> if (unlikely (elf_brk > elf_bss)) {
> unsigned
On 02/01/2018 02:16 AM, Kirill A. Shutemov wrote:
> On Thu, Feb 01, 2018 at 03:19:56PM +0800, Baoquan He wrote:
>> In sparse_init(), we allocate usemap_map and map_map which are pointer
>> array with the size of NR_MEM_SECTIONS. The memory consumption can be
>> ignorable in 4-level paging mode.
On 1 February 2018 at 11:46, Marc Zyngier wrote:
> ARM has recently published a SMC Calling Convention (SMCCC)
> specification update[1] that provides an optimised calling convention
> and optional, discoverable support for mitigating CVE-2017-5715. ARM
> Trusted Firmware
On 01/02/18 13:54, Marc Zyngier wrote:
On 01/02/18 13:34, Robin Murphy wrote:
On 01/02/18 11:46, Marc Zyngier wrote:
One of the major improvement of SMCCC v1.1 is that it only clobbers
the first 4 registers, both on 32 and 64bit. This means that it
becomes very easy to provide an inline
On 02/01/2018 03:19 PM, Konrad Rzeszutek Wilk wrote:
.snip..
+/* Is SPEC_CTRL intercepted for the currently running vCPU? */
+static bool spec_ctrl_intercepted(struct kvm_vcpu *vcpu)
+{
+ unsigned long *msr_bitmap;
+ int f = sizeof(unsigned long);
+
+ if
From: Geert Uytterhoeven
Date: Thu, 1 Feb 2018 11:25:27 +0100
> With gcc-4.1.2.:
>
> net/bridge/br_fdb.c: In function ‘br_fdb_sync_static’:
> net/bridge/br_fdb.c:996: warning: ‘err’ may be used uninitialized in this
> function
>
> Indeed, if the list is empty,
There are the retpoline validation patches; they work with the __noretpoline
thing from David.
The objtool retpoline validation found this indirect jump. Seeing how
it's on CPU bringup before we run userspace it should be safe, annotate
it.
Reviewed-by: David Woodhouse
Signed-off-by: Peter Zijlstra (Intel)
---
arch/x86/kernel/head_64.S |2 ++
Use the existing global variables instead of passing them around and
creating duplicate global variables.
Signed-off-by: Peter Zijlstra (Intel)
---
tools/objtool/builtin-check.c |2 +-
tools/objtool/builtin-orc.c |6 +-
tools/objtool/builtin.h |5
This is boot code, we run this _way_ before userspace comes along to
poison our branch predictor.
Cc: Tom Lendacky
Cc: Borislav Petkov
Signed-off-by: Peter Zijlstra (Intel)
---
arch/x86/mm/mem_encrypt_boot.S |2 ++
1 file
On Thu, 2018-02-01 at 15:34 +0100, Peter Zijlstra wrote:
>
> * These are the bare retpoline primitives for indirect jmp and call.
> * Do not use these directly; they only exist to make the ALTERNATIVE
> * invocation below less ugly.
> @@ -102,9 +114,9 @@
> .macro JMP_NOSPEC reg:req
>
Hi Shanker,
On Wed, Jan 31, 2018 at 06:03:42PM -0600, Shanker Donthineni wrote:
> A DMB instruction can be used to ensure the relative order of only
> memory accesses before and after the barrier. Since writes to system
> registers are not memory operations, barrier DMB is not sufficient
> for
In scpsys_probe function, return value of of_match_device function which
returns null is dereferenced without checking. Therefore, add a check for
potential null dereference.
Detected by CoverityScan, CID#1424087 "Dereference null return value"
Fixes: commit 53fddb1a66dd ("soc: mediatek: reduce
The following changes since commit 30a7acd573899fd8b8ac39236eff6468b195ac7d:
Linux 4.15-rc6 (2017-12-31 14:47:43 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/
tags/driver-core-4.16-rc1
for you to fetch changes up to
The following changes since commit 30a7acd573899fd8b8ac39236eff6468b195ac7d:
Linux 4.15-rc6 (2017-12-31 14:47:43 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git/
tags/char-misc-4.16-rc1
for you to fetch changes up to
Hi Robin,
On 1/31/2018 6:36 PM, Robin Murphy wrote:
> On 19/01/18 11:43, Vivek Gautam wrote:
>> From: Sricharan R
>>
>> The smmu device probe/remove and add/remove master device callbacks
>> gets called when the smmu is not linked to its master, that is without
>> the
On 23/01/2018 16:36, John Garry wrote:
On some platforms(such as Hip06/Hip07), the legacy ISA/LPC devices access
I/O with some special host-local I/O ports known on x86. As their I/O space
are not memory mapped like PCI/PCIE MMIO host bridges, this patch is meant
to support a new class of I/O
On Saturday 20 January 2018 10:43 PM, David Lechner wrote:
> This adds platform-specific declarations for the PSC clocks on TI DA850/
> OMAP-L138/AM18XX SoCs.
>
> Signed-off-by: David Lechner
Reviewed-by: Sekhar Nori
Thanks,
Sekhar
On Thu, Dec 07, 2017 at 02:31:08PM +0800, Huacai Chen wrote:
> Add Jiaxun Yang as the MIPS/Loongson-2 maintainer and add Huacai Chen
> as the MIPS/Loongson-3 maintainer.
>
> Signed-off-by: Huacai Chen
> Signed-off-by: Jiaxun Yang
> ---
> MAINTAINERS
On 01/02/18 11:46, Marc Zyngier wrote:
In order to call into the firmware to apply workarounds, it is
useful to find out whether we're using HVC or SMC. Let's expose
this through the psci_ops.
Reviewed-by: Robin Murphy
Acked-by: Lorenzo Pieralisi
On 01/02/18 13:22, Andrew Cooper wrote:
> On 01/02/18 12:16, Juergen Gross wrote:
>> When running as Xen pv guest %gs is initialized some time after
>> C code is started. Depending on stack protector usage this might be
>> too late, resulting in page faults.
>>
>> So setup %gs and MSR_GS_BASE in
On Thursday 01 February 2018 01:31 PM, Sekhar Nori wrote:
> One thing missing is DIV4.5 clock. It will be nice to add that too,
> mostly just because it will make the binding complete.
Ah, ignore this comment please. I noticed that its part of cfgchip
clocks (which makes sense).
Thanks,
Sekhar
When running as Xen pv guest %gs is initialized some time after
C code is started. Depending on stack protector usage this might be
too late, resulting in page faults.
So setup %gs and MSR_GS_BASE in assembly code already.
Cc: sta...@vger.kernel.org
Signed-off-by: Juergen Gross
On 01/02/18 11:46, Marc Zyngier wrote:
Function identifiers are a 32bit, unsigned quantity. But we never
tell so to the compiler, resulting in the following:
4ac: b26187e0mov x0, #0x8001
We thus rely on the firmware narrowing it for us, which is not
always a
On Thu, 2018-02-01 at 10:11 +0100, Peter Zijlstra wrote:
> On Thu, Feb 01, 2018 at 08:50:28AM +0100, Rafael J. Wysocki wrote:
> >
> > On Wednesday, January 31, 2018 11:17:10 AM CET Peter Zijlstra
> > wrote:
> > >
> > > On Wed, Jan 31, 2018 at 10:22:49AM +0100, Rafael J. Wysocki
> > > wrote:
> >
On Fri, Feb 02, 2018 at 12:22:27AM +1100, Stephen Rothwell wrote:
> Hi Christoffer,
>
> On Thu, 1 Feb 2018 11:47:07 +0100 Christoffer Dall
> wrote:
> >
> > While the suggested fix is functional it does result in some code
> > duplication, and the better resolution
On Thu, Feb 01, 2018 at 01:19:28PM +, Olivier MOYSAN wrote:
> On 02/01/2018 10:10 AM, Ladislav Michl wrote:
> > depends on (ARCH_STM32 && OF) || COMPILE_TEST ?
> I can find in many configs "depends on OF && (ARCH_X || COMPILE_TEST)"
> This seems reasonable to me, as the driver always
This guide is an adapted version of the more general "Protecting Code
Integrity" guide written and maintained by The Linux Foundation IT for
use with open-source projects. It provides the oft-lacking guidance on
the following topics:
- how to properly protect one's PGP keys to minimize the risks
Expose the new features introduced by Arm v8.4 extensions to
Arm v8-A profile.
These include :
1) Data indpendent timing of instructions. (DIT, exposed as HWCAP_DIT)
2) Unaligned atomic instructions and Single-copy atomicity of loads
and stores. (AT, expose as HWCAP_USCAT)
3) LDAPR and
We treat most of the feature bits in the ID registers as STRICT,
implying that all CPUs should match it the boot CPU state. However,
for most of the features, we can handle if there are any mismatches
by using the safe value. e.g, HWCAPs and other features used by the
kernel. Relax the constraint
On Thu, Feb 01, 2018 at 09:56:09AM +0100, Niklas Cassel wrote:
> On Thu, Feb 01, 2018 at 10:51:14AM +1100, Stephen Rothwell wrote:
> > Hi Bjorn,
> >
> > After merging the pci tree, today's linux-next build (arm
> > multi_v7_defconfig) failed like this:
> >
> >
From: KarimAllah Ahmed
[dwmw2: Use ARRAY_SIZE]
Signed-off-by: KarimAllah Ahmed
Signed-off-by: David Woodhouse
---
arch/x86/kernel/cpu/bugs.c | 86 ++
1 file changed, 56 insertions(+), 30
On Thu, Feb 01, 2018 at 04:52:01PM +0530, Kishon Vijay Abraham I wrote:
> Hi Niklas,
>
> On Thursday 01 February 2018 04:46 PM, Niklas Cassel wrote:
> > On Thu, Feb 01, 2018 at 11:10:54AM +, Lorenzo Pieralisi wrote:
> >> On Thu, Feb 01, 2018 at 09:56:09AM +0100, Niklas Cassel wrote:
> >>> On
On 01/02/18 12:25, Geert Uytterhoeven wrote:
> With gcc-4.1.2.:
>
> net/bridge/br_fdb.c: In function ‘br_fdb_sync_static’:
> net/bridge/br_fdb.c:996: warning: ‘err’ may be used uninitialized in this
> function
>
> Indeed, if the list is empty, err will be uninitialized, and will be
>
Since PSCI 1.0 allows the SMCCC version to be (indirectly) probed,
let's do that at boot time, and expose the version of the calling
convention as part of the psci_ops structure.
Acked-by: Lorenzo Pieralisi
Signed-off-by: Marc Zyngier
---
We want SMCCC_ARCH_WORKAROUND_1 to be fast. As fast as possible.
So let's intercept it as early as we can by testing for the
function call number as soon as we've identified a HVC call
coming from the guest.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/hyp/hyp-entry.S |
We're about to need kvm_psci_version in HYP too. So let's turn it
into a static inline, and pass the kvm structure as a second
parameter (so that HYP can do a kern_hyp_va on it).
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/hyp/switch.c | 20
One of the major improvement of SMCCC v1.1 is that it only clobbers
the first 4 registers, both on 32 and 64bit. This means that it
becomes very easy to provide an inline version of the SMC call
primitive, and avoid performing a function call to stash the
registers that would otherwise be
A new feature of SMCCC 1.1 is that it offers firmware-based CPU
workarounds. In particular, SMCCC_ARCH_WORKAROUND_1 provides
BP hardening for CVE-2017-5715.
If the host has some mitigation for this issue, report that
we deal with it using SMCCC_ARCH_WORKAROUND_1, as we apply the
host workaround
On Wed, Jan 17, 2018 at 07:56:38PM +0100, Corentin Labbe wrote:
> MIPS_GENERIC select some options with condition on BIG_ENDIAN which do
> not exists.
> Replace BIG_ENDIAN by CPU_BIG_ENDIAN which is the correct kconfig name.
> Note that BMIP_GENERIC do the same which confirm that this patch is
>
On Thu, Feb 01, 2018 at 11:08:46AM +0800, Baolin Wang wrote:
> On 31 January 2018 at 22:23, Andy Shevchenko
> wrote:
> > On Wed, Jan 31, 2018 at 4:01 AM, Baolin Wang wrote:
> >> On 31 January 2018 at 00:48, Andy Shevchenko
On 01/02/18 02:00, Christopher Lameter wrote:
> On Tue, 30 Jan 2018, Igor Stoppa wrote:
>
>> @@ -1769,6 +1774,9 @@ void *__vmalloc_node_range(unsigned long size,
>> unsigned long align,
>>
>> kmemleak_vmalloc(area, size, gfp_mask);
>>
>> +for (page_counter = 0; page_counter <
On 1 February 2018 at 12:40, Robin Murphy wrote:
> On 01/02/18 11:46, Marc Zyngier wrote:
>>
>> Function identifiers are a 32bit, unsigned quantity. But we never
>> tell so to the compiler, resulting in the following:
>>
>> 4ac: b26187e0mov x0,
1 - 100 of 1576 matches
Mail list logo