> > No no, you don't need to add yourself there. I understand the mux drivers,
> > and it's pretty quiet, so no need for that. What I was worrying about was
> > this "Odd Fixes" fallback entry needlessly covering the muxes when they
> > are covered elsewhere.
>
> If you want to exclude drivers/i2
On Tue, Apr 10, 2018 at 06:53:04AM -0700, Eric Dumazet wrote:
> On 04/10/2018 05:53 AM, Matthew Wilcox wrote:
> > From: Matthew Wilcox
> >
> > __GFP_ZERO requests that the object be initialised to all-zeroes,
> > while the purpose of a constructor is to initialise an object to a
> > particular pa
On 04/09/2018 05:05 PM, Mike Kravetz wrote:
In preparation for memfd code restucture, update comments dealing
with file sealing to indicate that tmpfs and hugetlbfs are the
supported filesystems. Also, change file pointer checks in
memfd_file_seals_ptr to use defined routines instead of directly
On 04/09/2018 05:05 PM, Mike Kravetz wrote:
With the addition of memfd hugetlbfs support, we now have the situation
where memfd depends on TMPFS -or- HUGETLBFS. Previously, memfd was only
supported on tmpfs, so it made sense that the code resided in shmem.c.
In the current code, memfd is only fu
On Tue, 10 Apr 2018 21:54:19 +0800
Jia-Ju Bai wrote:
> dma_tx_fragment() is never called in atomic context.
>
> dma_tx_fragment() is only called by b43legacy_dma_tx(), which is
> only called by b43legacy_tx_work().
> b43legacy_tx_work() is only set a parameter of INIT_WORK() in
> b43legacy_wir
Hi Andy, Shawn,
I saw mention of DMA while skimming through LAKML, so you win a drive-by
review :)
On 08/02/18 12:18, Andy Yan wrote:
From: Shawn Lin
Add Rockchip SFC(serial flash controller) driver.
Signed-off-by: Shawn Lin
Signed-off-by: Andy Yan
Acked-by: Marek Vasut
---
Changes in
On Tue, Apr 10, 2018 at 01:13:13PM +0200, Dmitry Vyukov wrote:
> On Mon, Apr 9, 2018 at 8:11 PM, Paul E. McKenney
> wrote:
> > On Mon, Apr 09, 2018 at 06:28:16PM +0200, Dmitry Vyukov wrote:
> >> On Mon, Apr 9, 2018 at 6:20 PM, Paul E. McKenney
> >> wrote:
> >> > On Mon, Apr 09, 2018 at 02:54:20PM
The code refactoring by commit 0176adb00406 ("swiotlb: refactor
coherent buffer allocation") made swiotlb_alloc_buffer() almost always
failing due to a thinko: namely, the function evaluates the
dma_coherent_ok() call incorrectly and dealing as if it's invalid.
This ends up with weird errors like i
On Tue, 10 Apr 2018, Matthew Wilcox wrote:
> Are you willing to have this kind of bug go uncaught for a while?
There will be frequent allocations and this will show up at some point.
Also you could put this into the debug only portions somehwere so we
always catch it when debugging is on,
'
On Tue, Apr 10, 2018 at 07:05:13PM +0200, Takashi Iwai wrote:
> The code refactoring by commit 0176adb00406 ("swiotlb: refactor
> coherent buffer allocation") made swiotlb_alloc_buffer() almost always
> failing due to a thinko: namely, the function evaluates the
> dma_coherent_ok() call incorrectly
On Thu, Apr 5, 2018 at 4:17 PM Stephen Boyd wrote:
> Quoting Taniya Das (2018-04-02 03:33:26)
> >
> > >
> > >> +
> > >> +#include "common.h"
> > >> +#include "clk-regmap.h"
> > >> +
> > >> +#define CLK_RPMH_ARC_EN_OFFSET 0
> > >> +#define CLK_RPMH_VRM_EN_OFFSET 4
> > >> +#define CLK_RPMH_VRM_OFF_
Hi Bartosz,
I love your patch! Yet something to improve:
[auto build test ERROR on gpio/for-next]
[also build test ERROR on v4.16 next-20180410]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits
On Tue, 10 Apr 2018 19:06:15 +0200,
Christoph Hellwig wrote:
>
> On Tue, Apr 10, 2018 at 07:05:13PM +0200, Takashi Iwai wrote:
> > The code refactoring by commit 0176adb00406 ("swiotlb: refactor
> > coherent buffer allocation") made swiotlb_alloc_buffer() almost always
> > failing due to a thinko:
...and restore reverse xmas tree while at it.
Signed-off-by: Laszlo Toth
---
drivers/acpi/reboot.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/acpi/reboot.c b/drivers/acpi/reboot.c
index 71769fd..6fa9c2a 100644
--- a/drivers/acpi/reboot.c
+++ b/drivers/acpi/re
Hi Linus,
This is first batch of Platform Drivers x86 for v4.17 cycle. Due to few
duplication the merge will have conflicts which would be resolved by
using `git merge -X no-renames ...` followed by choose of our version of
two failed one-liner hunks situated in one file.
Thanks,
With Best Regar
On 04/10/2018 03:13 PM, jacopo mondi wrote:
>>> From: Niklas Söderlund
>>>
>>> Add the LVDS device to r8a77970.dtsi in a disabled state. Also connect
>>> the it to the LVDS output of the DU.
>>>
>>> Signed-off-by: Niklas Söderlund
>>> Signed-off-by: Jacopo Mondi
>>> Reviewed-by: Laurent Pinchar
Adds in pci_epc_set_msi function a maximum number of 32 interrupts
validation.
Removes duplicate defines located on pcie-designware.h file. Uses now
the defines available on /include/uapi/linux/pci-regs.h file.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/dwc/pcie-designware-ep.c | 46 ++
This patch set depends the following series:
https://lkml.org/lkml/2018/4/10/421
This series aims to add pcitest tool support for MSI-X.
Includes new callbacks methods and handlers to trigger the MSI-X
interruptions on the EP Designware IP driver.
Provides new methods on pci_epf_test driver tha
Changes the cdns_pcie_ep_raise_irq function signature, namely the
interrupt_num variable type from u8 to u16 to accommodate the MSI-X maximum
interrupts of 2048.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/cadence/pcie-cadence-ep.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Adds MSI-X support to the pcitest tool and modified the pcitest.sh script
to accomodate this new type of interruption test.
Signed-off-by: Gustavo Pimentel
---
include/uapi/linux/pcitest.h | 1 +
tools/pci/pcitest.c | 18 +-
tools/pci/pcitest.sh | 25 +++
Adds the MSI-X support and updates driver documentation accordingly.
Changes the driver parameter in order to allow the interruption type
selection.
Signed-off-by: Gustavo Pimentel
---
Documentation/misc-devices/pci-endpoint-test.txt | 3 +
drivers/misc/pci_endpoint_test.c | 1
Hi Tejun,
On 09-Apr 15:24, Tejun Heo wrote:
> On Mon, Apr 09, 2018 at 05:56:12PM +0100, Patrick Bellasi wrote:
> > This patch extends the CPU controller by adding a couple of new attributes,
> > util_min and util_max, which can be used to enforce frequency boosting and
> > capping. Specifically:
>
Replaces lower into upper case characters in comments and debug printks.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/endpoint/functions/pci-epf-test.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/pci/endpoint/functions/pci-epf-test.
Replaces lower into upper case characters in comments and debug printks.
Signed-off-by: Gustavo Pimentel
---
drivers/misc/pci_endpoint_test.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
Hi, Kees, Paolo et al.
10.04.2018 08:53, Kees Cook wrote:
Unfortunately I only had a single hang with no dumps. I haven't been
able to reproduce it since. :(
For your convenience I've prepared a VM that contains a reproducer.
It consists of 3 disk images (sda.img is for the system, it is
Arc
Adds driver's MSI-X support.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/endpoint/functions/pci-epf-test.c | 87 +--
1 file changed, 69 insertions(+), 18 deletions(-)
diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c
b/drivers/pci/endpoint/functions/pci-epf
Implements the generic method for calling the get/set callbacks.
Adds the PCI_EPC_IRQ_MSIX type.
Adds the MSI-X callbacks signatures to the ops structure.
Adds sysfs interface for altering the number of MSI-X entries.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/endpoint/pci-ep-cfs.c | 2
Adds a legacy interrupt callback handler. Currently Designware IP doesn't
allow triggering the legacy interrupt.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/dwc/pcie-designware-ep.c | 10 ++
drivers/pci/dwc/pcie-designware-plat.c | 3 +--
drivers/pci/dwc/pcie-designware.h |
Changes the pcie_raise_irq function signature, namely the interrupt_num
variable type from u8 to u16 to accommodate the MSI-X maximum interrupts
of 2048.
Implements a PCIe config space capability iterator function to search and
save the MSI and MSI-X pointers. With this method the code becomes mor
It was observed occasionally in PowerPC systems that there was reader
who had not been woken up but that its waiter->task had been cleared.
One probable cause of this missed wakeup may be the fact that the
waiter->task and the task state have not been properly synchronized as
the lock release-acqu
On Tue, Apr 10, 2018 at 09:37:53AM +0300, Oleksandr Andrushchenko wrote:
> On 04/06/2018 09:57 PM, Dongwon Kim wrote:
> >On Fri, Apr 06, 2018 at 03:36:03PM +0300, Oleksandr Andrushchenko wrote:
> >>On 04/06/2018 02:57 PM, Gerd Hoffmann wrote:
> >>> Hi,
> >>>
> >I fail to see any common ground
On Fri, Apr 06, 2018 at 04:36:06PM +0100, Dietmar Eggemann wrote:
> + for_each_freq_domain(fd) {
> + unsigned long spare_cap, max_spare_cap = 0;
> + int max_spare_cap_cpu = -1;
> + unsigned long util;
> +
> + /* Find the CPU with the max spare cap
Hans de Goede - 19.03.18, 10:50:
> > Martin (or someone else): Could you gibe a status update? I have this
> > issue on my list or regressions, but it's hard to follow as two
> > different issues seem to be discussed. Or is it just one issue? Did the
> > patch/discussion that Bart pointed to help?
On 10/04/18 16:23, Marc Zyngier wrote:
> I have a vague idea how to support this. Given that level-triggered MSIs
> have to be platform MSIs (because it is just madness otherwise), we can
> probably store an extra message in the struct platform_msi_desc for the
> "lower the line" write. On activat
On Tue, 10 Apr 2018, Matthew Wilcox wrote:
> If we want to get rid of the concept of constructors, it's doable,
> but somebody needs to do the work to show what the effects will be.
How do you envision dealing with the SLAB_TYPESAFE_BY_RCU slab caches?
Those must have a defined state of the objec
On Tue, Apr 10, 2018 at 12:30:23PM -0500, Christopher Lameter wrote:
> On Tue, 10 Apr 2018, Matthew Wilcox wrote:
>
> > If we want to get rid of the concept of constructors, it's doable,
> > but somebody needs to do the work to show what the effects will be.
>
> How do you envision dealing with t
On Sun 08 Apr 03:32 PDT 2018, Taniya Das wrote:
> From: Amit Nischal
>
> Add the RPMh clock driver to control the RPMh managed clock resources on
> some of the Qualcomm Technologies, Inc. SoCs.
>
> Signed-off-by: David Collins
> Signed-off-by: Amit Nischal
> Signed-off-by: Taniya Das
> ---
>
On Tue, Apr 10, 2018 at 10:34:55AM +0200, Petr Mladek wrote:
> > > > > > We were just recently discussing the possibility of not allowing the
> > > > > > disabling of patches at all. If we're not going that far, let's at
> > > > > > least further restrict it, for the sanity of our code, so we don'
On Tue, 10 Apr 2018, Matthew Wilcox wrote:
> > How do you envision dealing with the SLAB_TYPESAFE_BY_RCU slab caches?
> > Those must have a defined state of the objects at all times and a
> > constructor is
> > required for that. And their use of RCU is required for numerous lockless
> > lookup a
> > I agree here. Practically we use only cumulative replacement patches at
> > SUSE. So with that in mind I don't care about the stacking much. But, it
> > may make sense for someone else. Evgenii mentioned they used it for
> > hotfixes. Therefore I'm reluctant to remove it completely.
>
> Well,
On Fri, Apr 06 2018 at 17:23 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2018-04-06 08:13:55)
From: Mahesh Sivasubramanian
Command DB is a simple database in the shared memory of QCOM SoCs, that
provides information regarding shared resources. Some shared resources
in the SoC have properties
On 10/04/18 18:07, Takashi Iwai wrote:
On Tue, 10 Apr 2018 19:06:15 +0200,
Christoph Hellwig wrote:
On Tue, Apr 10, 2018 at 07:05:13PM +0200, Takashi Iwai wrote:
The code refactoring by commit 0176adb00406 ("swiotlb: refactor
coherent buffer allocation") made swiotlb_alloc_buffer() almost alwa
On Tue, Apr 10, 2018 at 12:45:56PM -0500, Christopher Lameter wrote:
> On Tue, 10 Apr 2018, Matthew Wilcox wrote:
>
> > > How do you envision dealing with the SLAB_TYPESAFE_BY_RCU slab caches?
> > > Those must have a defined state of the objects at all times and a
> > > constructor is
> > > requi
On Tue, Apr 10, 2018 at 04:31:05PM +0200, Miroslav Benes wrote:
>
> > > > I love this. Nice work!
>
> Yes, it looks really good.
>
> > > > As you and Petr discussed, it would be nice to get rid of some of the
> > > > delays, and also the callback tests will be very important.
> > >
> > > I've
On Tue, Apr 10, 2018 at 12:56:25PM +0200, Petr Mladek wrote:
> > > diff --git a/include/linux/livepatch.h b/include/linux/livepatch.h
> > > index f28af280f9e0..d6e6d8176995 100644
> > > --- a/include/linux/livepatch.h
> > > +++ b/include/linux/livepatch.h
> > > @@ -378,7 +383,7 @@ int klp_disable_p
From: Mahesh Sivasubramanian
Command DB is a simple database in the shared memory of QCOM SoCs, that
provides information regarding shared resources. Some shared resources
in the SoC have properties that are probed dynamically at boot by the
remote processor. The information pertaining to the SoC
From: Mahesh Sivasubramanian
Command DB provides information on shared resources like clocks,
regulators etc., probed at boot by the remote subsytem and made
available in shared memory.
Cc: devicet...@vger.kernel.org
Signed-off-by: Mahesh Sivasubramanian
Signed-off-by: Lina Iyer
Reviewed-by: B
Changes since v7:
- Add reviewed-by tags
- Fix example
Changes since v6:
- Fix 'reg' property
- Add reviewed-by tags
Changes since v5:
- Remove indirection of command db start address
- Rebase on top of 4.16
Changes since v4:
- Address comm
On Tue, 10 Apr 2018 09:45:54 -0700
Joel Fernandes wrote:
> > diff --git a/include/linux/ring_buffer.h b/include/linux/ring_buffer.h
> > index a0233edc0718..807e2bcb21b3 100644
> > --- a/include/linux/ring_buffer.h
> > +++ b/include/linux/ring_buffer.h
> > @@ -106,7 +106,8 @@ __poll_t ring_buffer_
Nobody ever tried to self destruct by unmapping whole address space at once:
munmap((void *)0, (1ULL << 47) - 4096);
Doing this produces 2 warnings for zero-length vmalloc allocations:
a.out[1353]: segfault at 7f80bcc4b757 ip 7f80bcc4b757 sp 7fff683939b8
error 14
a.out: vmalloc:
On Tue, Apr 10, 2018 at 7:07 PM, H. Nikolaus Schaller
wrote:
> PCAL chips ("L" seems to stand for "latched") have additional
> registers starting at address 0x40 to control the latches,
> interrupt mask, pull-up and pull down etc.
>
> The constants are so far defined in a way that they fit for
>
On Tue, Apr 10, 2018 at 7:07 PM, H. Nikolaus Schaller
wrote:
> The of_device_table is missing the PCA_PCAL flag so the
> pcal6524 would be operated in tca6424 compatibility mode which
> does not handle the new interrupt mask registers.
> + { .compatible = "nxp,pcal6524", .data = OF_953X(2
On Tue, Apr 10, 2018 at 9:08 PM, Andy Shevchenko
wrote:
> On Tue, Apr 10, 2018 at 7:07 PM, H. Nikolaus Schaller
> wrote:
>> The of_device_table is missing the PCA_PCAL flag so the
>> pcal6524 would be operated in tca6424 compatibility mode which
>> does not handle the new interrupt mask register
On Tue, Apr 10, 2018 at 06:50:04PM +0100, Robin Murphy wrote:
> In the first one, the machine appears to have enough RAM that most of it is
> beyond the device's 36-bit DMA mask, thus it's fairly likely for the
> initial direct alloc to come back with something unsuitable.
But we should try a GF
On Tuesday 10 Apr 2018 at 19:29:32 (+0200), Peter Zijlstra wrote:
> On Fri, Apr 06, 2018 at 04:36:06PM +0100, Dietmar Eggemann wrote:
> > + for_each_freq_domain(fd) {
> > + unsigned long spare_cap, max_spare_cap = 0;
> > + int max_spare_cap_cpu = -1;
> > + unsigned l
Alan,
I merged SBI emulation for perf counters and config:
https://github.com/riscv/riscv-pk/pull/98
You should be able to write these CSRs.
Thanks,
Alex
On Mon, Apr 9, 2018 at 12:07 AM, Alan Kao wrote:
> On Thu, Apr 05, 2018 at 09:47:50AM -0700, Palmer Dabbelt wrote:
>> On Mon, 26 Mar 2018 00
Quoting Marc Zyngier (2018-04-10 08:23:00)
> On 10/04/18 16:01, Thomas Petazzoni wrote:
>
> > In the upcoming Armada 8KP, we have a GICv3, which has built-in support
> > for memory-triggered SPIs, thanks to the GICD_SETSPI_NSR and
> > GICD_CLRSPI_NSR, and the ICU will directly use this GICv3
> > f
On Mon, Mar 26, 2018 at 02:22:54PM -0700, Andrew Morton wrote:
> On Mon, 26 Mar 2018 10:39:51 +0800 Wei Wang wrote:
>
> > This patch adds support to walk through the free page blocks in the
> > system and report them via a callback function. Some page blocks may
> > leave the free list after zone
A struct with a bool member can have different sizes on various
architectures because neither bool size nor alignment is standardized.
So emit a message on the use of bool in structs only in .h files and
not .c files.
There is the real possibility that this test could have a false positive
when a
Quoting Viresh Kumar (2018-04-10 02:05:22)
> The OPP tables are present as separate nodes, whose phandle is used in
> the "operating-points-v2" property of devices. Currently the OF core
> creates a platform device for the OPP table unconditionally, which is
> not used by any kernel code.
>
> Skip
On some Mali-DP processors, the LAYER_FORMAT register contains fields
other than the format. These bits were unconditionally cleared when
setting the pixel format, whereas they should be preserved at their
reset values.
Reported-by: Brian Starkey
Reported-by: Liviu Dudau
Signed-off-by: Ayan Kuma
Code is expecing to observe the same number of buffers returned from
dma_map_sg() function compared to sg_alloc_table_from_pages(). This
doesn't hold true universally especially for systems with IOMMU.
IOMMU driver tries to combine buffers into a single DMA address as much
as it can. The right thi
On Tue 03 Apr 02:12 PDT 2018, Loic PALLARDY wrote:
> > -Original Message-
> > From: linux-remoteproc-ow...@vger.kernel.org [mailto:linux-remoteproc-
> > ow...@vger.kernel.org] On Behalf Of Bjorn Andersson
[..]
> > diff --git a/drivers/rpmsg/rpmsg_core.c b/drivers/rpmsg/rpmsg_core.c
> > inde
Hi Waiman,
On Mon, Apr 09, 2018 at 02:08:52PM -0400, Waiman Long wrote:
> A locker in the pending code path is doing an infinite number of spins
> when waiting for the _Q_PENDING_VAL to _Q_LOCK_VAL transition. There
> is a concern that lock starvation can happen concurrent lockers are
> able to ta
Hi Eric,
> Eric Anholt hat am 10. April 2018 um 01:00 geschrieben:
>
>
> The GPU subsystem node was a workaround to have a central device to
> bind V3D and display to. Following the lead of 246774d17fc0
> ("drm/etnaviv: remove the need for a gpu-subsystem DT node"), remove
> the subsystem node
On 4/10/18 9:21 AM, Yang Shi wrote:
On 4/10/18 5:28 AM, Cyrill Gorcunov wrote:
On Tue, Apr 10, 2018 at 01:10:01PM +0200, Michal Hocko wrote:
Because do_brk does vma manipulations, for this reason it's
running under down_write_killable(&mm->mmap_sem). Or you
mean something else?
Yes, all we
Introduction of the Platform Environment Control Interface (PECI) bus
device driver. PECI is a one-wire bus interface that provides a
communication channel between an Intel processor and chipset components to
external monitoring or control devices. PECI is designed to support the
following sideband
Quoting Doug Anderson (2018-04-10 08:05:27)
> On Mon, Apr 9, 2018 at 11:36 PM, Manu Gautam wrote:
> > On 3/30/2018 2:24 AM, Doug Anderson wrote:
> >> Oh! This is what you did in the previous version of the patch, then you
> >> said:
> >>
> >> "That is still needed as PHY might take some time to
This commit Updates ioctl-number.txt to reflect ioctl numbers being
used by the PECI subsystem.
Signed-off-by: Jae Hyun Yoo
Cc: Alan Cox
Cc: Andrew Jeffery
Cc: Andrew Lunn
Cc: Andy Shevchenko
Cc: Arnd Bergmann
Cc: Benjamin Herrenschmidt
Cc: Fengguang Wu
Cc: Greg KH
Cc: Guenter Roeck
Cc:
This commit adds a maintainer information for the PECI subsystem.
Signed-off-by: Jae Hyun Yoo
Reviewed-by: Haiyue Wang
Reviewed-by: James Feist
Reviewed-by: Vernon Mauery
Cc: Alan Cox
Cc: Andrew Jeffery
Cc: Andrew Lunn
Cc: Andy Shevchenko
Cc: Arnd Bergmann
Cc: Benjamin Herrenschmidt
Cc:
On 10.04.2018 13:21, Richard Fitzgerald wrote:
> On 04/04/18 06:33, Mika Penttilä wrote:
>> Hi!
>>
>> Reverting this made the hogs on a i.MX6 board work again. :
>>
>>
>> commit b89405b6102fcc3746f43697b826028caa94c823
>> Author: Richard Fitzgerald
>> Date: Wed Feb 28 15:53:06 2018 +
>>
>>
This commit adds PECI cputemp and dimmtemp hwmon drivers.
Signed-off-by: Jae Hyun Yoo
Reviewed-by: Haiyue Wang
Reviewed-by: James Feist
Reviewed-by: Vernon Mauery
Cc: Alan Cox
Cc: Andrew Jeffery
Cc: Andrew Lunn
Cc: Andy Shevchenko
Cc: Arnd Bergmann
Cc: Benjamin Herrenschmidt
Cc: Fengguan
This commit adds PECI adapter driver implementation for Aspeed
AST24xx/AST25xx.
Signed-off-by: Jae Hyun Yoo
Reviewed-by: Haiyue Wang
Reviewed-by: James Feist
Reviewed-by: Vernon Mauery
Cc: Alan Cox
Cc: Andrew Jeffery
Cc: Andrew Lunn
Cc: Andy Shevchenko
Cc: Arnd Bergmann
Cc: Benjamin Herre
This commit adds dt-bindings documents for PECI cputemp and dimmtemp client
drivers.
Signed-off-by: Jae Hyun Yoo
Reviewed-by: Haiyue Wang
Reviewed-by: James Feist
Reviewed-by: Vernon Mauery
Cc: Alan Cox
Cc: Andrew Jeffery
Cc: Andrew Lunn
Cc: Andy Shevchenko
Cc: Arnd Bergmann
Cc: Benjamin
This commit adds hwmon documents for PECI cputemp and dimmtemp drivers.
Signed-off-by: Jae Hyun Yoo
Reviewed-by: Haiyue Wang
Reviewed-by: James Feist
Reviewed-by: Vernon Mauery
Cc: Alan Cox
Cc: Andrew Jeffery
Cc: Andrew Lunn
Cc: Andy Shevchenko
Cc: Arnd Bergmann
Cc: Benjamin Herrenschmidt
This commit adds a dt-bindings document of PECI adapter driver for Aspeed
AST24xx/25xx SoCs.
Signed-off-by: Jae Hyun Yoo
Reviewed-by: Haiyue Wang
Reviewed-by: James Feist
Reviewed-by: Vernon Mauery
Cc: Alan Cox
Cc: Andrew Jeffery
Cc: Andrew Lunn
Cc: Andy Shevchenko
Cc: Arnd Bergmann
Cc: B
Hi Andy,
Just a very minor nit.
On 8 February 2018 at 09:18, Andy Yan wrote:
[..]
> +
> +static int get_if_type(struct rockchip_sfc *sfc, enum spi_nor_protocol proto)
> +{
I understand that this got copy-pasted from some other driver,
but please change this function name to something like
rockc
Platform device core assumes the ownership of dev.platform_data as
well as that it is dynamically allocated and it will try to kfree it
as a part of platform_device_release(). Change the code to use
platform_device_add_data() n instead of a pointer to a static memory
to avoid causing a BUG() when c
Platform device core assumes the ownership of dev.platform_data as
well as that it is dynamically allocated and it will try to kfree it
as a part of platform_device_release(). Change the code to use
platform_device_add_data() instead of a pointer to a static memory to
avoid causing a BUG() when cal
This commit adds PECI bus/adapter node of AST24xx/AST25xx into
aspeed-g4 and aspeed-g5.
Signed-off-by: Jae Hyun Yoo
Reviewed-by: Haiyue Wang
Reviewed-by: James Feist
Reviewed-by: Vernon Mauery
Cc: Alan Cox
Cc: Andrew Jeffery
Cc: Andrew Lunn
Cc: Andy Shevchenko
Cc: Arnd Bergmann
Cc: Benjam
Hi Stephen,
On 10/04/18 19:17, Stephen Boyd wrote:
> Quoting Marc Zyngier (2018-04-10 08:23:00)
>> On 10/04/18 16:01, Thomas Petazzoni wrote:
>>
>>> In the upcoming Armada 8KP, we have a GICv3, which has built-in support
>>> for memory-triggered SPIs, thanks to the GICD_SETSPI_NSR and
>>> GICD_CLR
This commit adds driver implementation for PECI bus core into linux
driver framework.
Signed-off-by: Jae Hyun Yoo
Signed-off-by: Fengguang Wu
Reviewed-by: Haiyue Wang
Reviewed-by: James Feist
Reviewed-by: Vernon Mauery
Cc: Alan Cox
Cc: Andrew Jeffery
Cc: Andrew Lunn
Cc: Andy Shevchenko
Cc
This commit adds documents of generic PECI bus, adapter and client drivers.
Signed-off-by: Jae Hyun Yoo
Reviewed-by: Haiyue Wang
Reviewed-by: James Feist
Reviewed-by: Vernon Mauery
Cc: Alan Cox
Cc: Andrew Jeffery
Cc: Andrew Lunn
Cc: Andy Shevchenko
Cc: Arnd Bergmann
Cc: Benjamin Herrensch
Hi Steve,
On Tue, Apr 10, 2018 at 11:00 AM, Steven Rostedt wrote:
> On Tue, 10 Apr 2018 09:45:54 -0700
> Joel Fernandes wrote:
>
>> > diff --git a/include/linux/ring_buffer.h b/include/linux/ring_buffer.h
>> > index a0233edc0718..807e2bcb21b3 100644
>> > --- a/include/linux/ring_buffer.h
>> > ++
On Tue 10 Apr 06:54 PDT 2018, Srinivas Kandagatla wrote:
> From: Srinivas Kandagatla
>
> This patch adds missing microSD card supplies, without this uSD
> card will not be detected.
>
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> Signed-off-by: Srinivas Kandagatla
> ---
> arch/arm64/boot/
Thanks Christian for catching that. I'm working on a patch series to
upstream Vega10 support, about 95% done. It will add this ASIC info for
Vega10:
static const struct kfd_device_info vega10_device_info = {
.asic_family = CHIP_VEGA10,
.max_pasid_bits = 16,
.max_no_of_hqd
On 04/09/2018 11:38 PM, Christian König wrote:
Am 09.04.2018 um 23:06 schrieb Laura Abbott:
There's an ongoing effort to remove VLAs[1] from the kernel to eventually
turn on -Wvla. The single VLA usage in the amdkfd driver is actually
constant across all current platforms.
Actually that isn't
Tejun Heo - 03.04.18, 00:04:
> Request abortion is performed by overriding deadline to now and
> scheduling timeout handling immediately. For the latter part, the
> code was using mod_timer(timeout, 0) which can't guarantee that the
> timer runs afterwards. Let's schedule the underlying work item
On 04/10/2018 12:57 AM, Arnd Bergmann wrote:
On Mon, Apr 9, 2018 at 11:07 PM, Laura Abbott wrote:
There's an ongoing effort to remove VLAs[1] from the kernel to eventually
turn on -Wvla. The single VLA can either take a value of 2 or 4 so switch
to the upper bound.
[1] https://lkml.org/lkml/20
Am 10.04.2018 um 20:25 schrieb Sinan Kaya:
Code is expecing to observe the same number of buffers returned from
dma_map_sg() function compared to sg_alloc_table_from_pages(). This
doesn't hold true universally especially for systems with IOMMU.
IOMMU driver tries to combine buffers into a single
On 04/10/2018 02:26 PM, Will Deacon wrote:
> Hi Waiman,
>
> On Mon, Apr 09, 2018 at 02:08:52PM -0400, Waiman Long wrote:
>> A locker in the pending code path is doing an infinite number of spins
>> when waiting for the _Q_PENDING_VAL to _Q_LOCK_VAL transition. There
>> is a concern that lock starva
>Hi,
>
>Many thanks that you have picked it up.
>Unfortunately I didn't had time to work on it for a while.
>
>I am ok with what you have done, ihmo the review is going in good direction.
>I will try not to miss your update of it.
>From my side I can say that damage rects with frame-buffer coordina
On 04/10/2018 03:45 AM, Christian Brauner wrote:
> On Tue, Apr 10, 2018 at 04:20:53PM +1000, Michael Ellerman wrote:
>> In commit ce290a19609d ("selftests: add devpts selftests"), the
>> filesystems directory was added to the top-level selftests Makefile.
>>
>> That had the effect of causing the ex
On Mon 09 Apr 14:40 PDT 2018, Niklas Cassel wrote:
> qcom_scm_call_atomic1() can crash with a NULL pointer dereference at
> qcom_scm_call_atomic1+0x30/0x48.
>
> disassembly of qcom_scm_call_atomic1():
> ...
> <0xc08d73b0 <+12>: ldr r3, [r12]
> ... (no instruction explicitly modifies r12)
> 0xc08d
On Tue, 10 Apr 2018 11:39:24 -0700
Joel Fernandes wrote:
> Yes I agree. So lets just do that and no other patches additional
> patches are needed then. Let me know if there's anything else I
> missed?
Yeah, I think there's really no other issue. I'm not going to apply
more patches.
>
> Also I
From: Greg Hartman
The cuttlefish system is a virtual SoC architecture based on QEMU. It
uses the QEMU ivshmem feature to share memory regions between guest and
host with a custom protocol.
Cc: Greg Kroah-Hartman
Cc: Arve Hjønnevåg
Cc: Todd Kjos
Cc: Martijn Coenen
Cc: de...@driverdev.osuosl.
On Tue, Apr 10, 2018 at 10:58:22AM +0300, Kirill A. Shutemov wrote:
> On Mon, Apr 09, 2018 at 01:36:35PM -0700, Eric Biggers wrote:
> > On Mon, Apr 09, 2018 at 01:12:32PM -0700, Davidlohr Bueso wrote:
> > > On Mon, 09 Apr 2018, Eric Biggers wrote:
> > >
> > > > It's necessary because if we don't h
On Tue, Apr 10, 2018 at 11:28:13AM -0700, Yang Shi wrote:
> >
> > At the first glance, it looks feasible to me. Will look into deeper
> > later.
>
> A further look told me this might be *not* feasible.
>
> It looks the new lock will not break check_data_rlimit since in my patch
> both start_brk
On 04/09/2018 11:51 PM, Michael Ellerman wrote:
Thanks for picking this one up.
I hate to be a pain ... but before we merge this and proliferate these
names, I'd like to change the names of some of these early asm
functions. They're terribly named due to historical reasons.
Indeed :) No worrie
On Fri, Mar 30, 2018 at 01:24:44PM +0530, Nipun Gupta wrote:
> It is bus specific aspect to map a given device on the bus and
> relevant firmware description of its DMA configuration.
> So, this change introduces 'dma_configure' as bus callback
> giving flexibility to busses for implementing its ow
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