On Sun, Mar 24, 2019 at 10:24 PM Wu Hao wrote:
Hi Hao,
>
> This patch introduces more sysfs interfaces for Accelerated
> Function Unit (AFU). These interfaces allow users to read
> current AFU Power State (APx), read / clear AFU Power (APx)
> events which are sticky to identify transient APx
On Mon, Mar 25, 2019 at 01:47:58PM +0100, Gregory CLEMENT wrote:
> Document the device tree binding for the cluster clock controllers found
> in the Armada 7K/8K SoCs.
>
> Signed-off-by: Gregory CLEMENT
> ---
> .../arm/marvell/ap806-system-controller.txt | 25 +++
> 1 file
On Fri, Mar 22, 2019 at 12:51:20PM +0200, Jarkko Sakkinen wrote:
> tpm_chip_start/stop() should be also called for TPM 1.x devices on
> suspend. Add that functionality back. Do not lock the chip because
> it is unnecessary as there are no multiple threads using it when
> doing the suspend.
>
>
On 3/26/2019 9:00 PM, Parav Pandit wrote:
>
>
>> -Original Message-
>> From: Kirti Wankhede
>> Sent: Tuesday, March 26, 2019 2:06 AM
>> To: Parav Pandit ; k...@vger.kernel.org; linux-
>> ker...@vger.kernel.org; alex.william...@redhat.com
>> Cc: Neo Jia
>> Subject: Re: [PATCH 8/8]
On Thu, Mar 28, 2019 at 02:23:33PM +0200, Jarkko Sakkinen wrote:
> On Wed, Mar 27, 2019 at 09:21:15AM +0100, Domenico Andreoli wrote:
> > Hi Jarkko,
> >
> > my laptop fails to suspend/hibernate since v5.1-rc1, it worked fine
> > with v4.20 and previous.
> >
> > My suspect is on tpm_tis driver,
Hi Rob,
On jeu., mars 28 2019, Rob Herring wrote:
> On Mon, Mar 25, 2019 at 01:47:58PM +0100, Gregory CLEMENT wrote:
>> Document the device tree binding for the cluster clock controllers found
>> in the Armada 7K/8K SoCs.
>>
>> Signed-off-by: Gregory CLEMENT
>> ---
>>
On 3/28/19 12:27 PM, Pierre Morel wrote:
On 28/03/2019 17:12, Tony Krowiak wrote:
On 3/22/19 10:43 AM, Pierre Morel wrote:
When the mediated device is open we setup the relation with KVM unset it
when the mediated device is released.
s/open we setup/open, we set up/
s/with KVM unset/with KVM
On 28/03/2019 11:22, Quentin Perret wrote:
> On Thursday 28 Mar 2019 at 10:13:50 (+), Quentin Perret wrote:
>> The recently introduced Energy Model (EM) framework manages power cost
>> tables for the CPUs of the system. Its only user right now is the
>> scheduler, in the context of Energy
On Thu, Mar 28, 2019 at 05:26:42PM +0100, Oleg Nesterov wrote:
> On 03/28, Jann Horn wrote:
> >
> > Since we're just talking about RCU stuff now, adding Paul McKenney to
> > the thread.
>
> Since you added Paul let me add more confusion to this thread ;)
Woo-hoo!!! More confusion! Bring it
On Thu, Mar 28, 2019 at 06:25:14PM +0100, Gregory CLEMENT wrote:
> Hi Rob,
>
> On jeu., mars 28 2019, Rob Herring wrote:
>
> > On Mon, Mar 25, 2019 at 01:47:58PM +0100, Gregory CLEMENT wrote:
> >> Document the device tree binding for the cluster clock controllers found
> >> in the Armada
On Wed, Mar 27, 2019 at 8:40 AM Jessica Yu wrote:
> >No. There are definitely not all modules. I have a builtin sha256_generic,
> >but I can't find him in the /sys/module.
>
> Yeah, you'll only find builtin modules under /sys/module/ if it has any module
> parameters, otherwise you won't find it
On Wed, Mar 20, 2019 at 06:49:38PM +, Suzuki K Poulose wrote:
> We rely on the device names to find a CoreSight device on the
> coresight bus. The device name however is obtained from the platform,
> which is bound to the real platform/amba device. As we are about
> to use different naming
Hi Daniel,
On Thursday 28 Mar 2019 at 18:27:49 (+0100), Daniel Lezcano wrote:
> On 28/03/2019 11:22, Quentin Perret wrote:
> >> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> >> index 2d9c39033c1a..3c09bdaaefd3 100644
> >> --- a/arch/arm64/configs/defconfig
> >> +++
Hi Jonathan,
> Am 24.03.2019 um 19:29 schrieb Jonathan Cameron :
>
> On Mon, 18 Mar 2019 21:39:30 +0100
> "H. Nikolaus Schaller" wrote:
>
>
>> Some user spaces (e.g. some Android) use /dev/input/event* for handling the
>> 3D
>> position of the device with respect to the center of
On Tue, Mar 26, 2019 at 05:48:10PM -0500, Bjorn Helgaas wrote:
[...]
> I'm not convinced about this last sentence.
>
> It's true that on most modern systems, including that Intel PCH, the
> Super I/O controller is attached via an LPC bridge on a PCI bus.
>
> But I don't think it's an actual
On Fri, 15 Mar 2019 01:59:26 +0100, =?UTF-8?q?Marek=20Beh=C3=BAn?= wrote:
> This adds device tree binding documentation for the driver communicating
> with the rWTM firmware on Turris Mox.
>
> Signed-off-by: Marek Behún
> Cc: Rob Herring
> Cc: devicet...@vger.kernel.org
> ---
>
From: Haiyang Zhang
After queue stopped, the wakeup mechanism may wake it up again
when ring buffer usage is lower than a threshold. This may cause
send path panic on NULL pointer when we stopped all tx queues in
netvsc_detach and start removing the netvsc device.
This patch fix it by adding a
On Sun, Mar 17, 2019 at 09:35:27PM +0100, Andreas Klinger wrote:
> Add doc for dt binding maxbotix,mb1232. This binding is for MaxBotix
> I2CXL-MaxSonar ultrasonic rangers which share a common i2c interface.
>
> Signed-off-by: Andreas Klinger
> ---
>
On Thu, 21 Mar 2019 08:40:45 -0700, "Angus Ainslie (Purism)" wrote:
> Document the vishay VCNL4000 devicetree bindings.
>
> Signed-off-by: Angus Ainslie (Purism)
> ---
> .../bindings/iio/light/vcnl4000.txt | 22 +++
> 1 file changed, 22 insertions(+)
> create mode
On Thu, 21 Mar 2019 08:40:47 -0700, "Angus Ainslie (Purism)" wrote:
> Document the vishay VCNL4040 devicetree bindings.
>
> Signed-off-by: Angus Ainslie (Purism)
> ---
> Documentation/devicetree/bindings/iio/light/vcnl4000.txt | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
On Wed, Mar 27, 2019 at 9:04 AM Alexey Gladkov wrote:
>
> On Wed, Mar 27, 2019 at 04:40:25PM +0100, Jessica Yu wrote:
> > +++ Alexey Gladkov [26/03/19 18:24 +0100]:
> > >On Fri, Mar 22, 2019 at 02:34:12PM +0900, Masahiro Yamada wrote:
> > >> Hi.
> > >>
> > >> (added some people to CC)
> >
> >
On Thu, Mar 21, 2019 at 07:14:39PM -0400, Gaël PORTAY wrote:
> From: Lin Huang
>
> These are required to support DDR DVFS on rk3399 platform. The patch also
> introduces a new file with default DRAM settings.
>
> Signed-off-by: Lin Huang
> Signed-off-by: Enric Balletbo i Serra
>
Hi Liang,
On Wed, Mar 27, 2019 at 9:52 AM Liang Yang wrote:
>
> Hi Martin,
>
> Thanks a lot.
> On 2019/3/26 2:31, Martin Blumenstingl wrote:
> > Hi Liang,
> >
> > On Mon, Mar 25, 2019 at 11:03 AM Liang Yang wrote:
> >>
> >> Hi Martin,
> >>
> >> On 2019/3/23 5:07, Martin Blumenstingl wrote:
>
On Thu, Feb 28, 2019 at 11:27:38AM -0800, Dmitry Torokhov wrote:
> Hi Eric,
>
> Currently, unless caller has CAP_SETGID in parent namespace, we can
> only map effective group id in the new user namespace. Would it be
> possible to relax this rule to also allow mapping of supplemental
> groups
On Mon, Mar 25, 2019 at 01:38:13PM +0530, Kishon Vijay Abraham I wrote:
> AM654x has two SERDES instances. Each instance has three input clocks
> (left input, externel reference clock and right input) and two output
> clocks (left output and right output) in addition to a PLL mux clock
> which the
This is part 2 of a 3-part (0/1/2) series to rearchitect the internal
operation of rwsem.
part 0: https://lkml.org/lkml/2019/3/22/1662
part 1: https://lkml.org/lkml/2019/2/28/1124
This patchset revamps the current rwsem-xadd implementation to make
it saner and easier to work with. It also
Because of writer lock stealing, it is possible that a constant
stream of incoming writers will cause a waiting writer or reader to
wait indefinitely leading to lock starvation.
The mutex code has a lock handoff mechanism to prevent lock starvation.
This patch implements a similar lock handoff
With separate count and owner, there are timing windows where the two
values are inconsistent. That can cause problem when trying to figure
out the exact state of the rwsem. For instance, a RT task will stop
optimistic spinning if the lock is acquired by a writer but the owner
field isn't set yet.
When the front of the wait queue is a reader, other readers
immediately following the first reader will also be woken up at the
same time. However, if there is a writer in between. Those readers
behind the writer will not be woken up.
Because of optimistic spinning, the lock acquisition order is
This patch enables readers to optimistically spin on a
rwsem when it is owned by a writer instead of going to sleep
directly. The rwsem_can_spin_on_owner() function is extracted
out of rwsem_optimistic_spin() and is called directly by
__rwsem_down_read_failed_common() and
With the commit 59aabfc7e959 ("locking/rwsem: Reduce spinlock contention
in wakeup after up_read()/up_write()"), the rwsem_wake() forgoes doing
a wakeup if the wait_lock cannot be directly acquired and an optimistic
spinning locker is present. This can help performance by avoiding
spinning on the
This patch modifies rwsem_spin_on_owner() to return four possible
values to better reflect the state of lock holder which enables us to
make a better decision of what to do next.
In the special case that there is no active lock and the handoff bit
is set, optimistic spinning has to be stopped.
When the rwsem is owned by reader, writers stop optimistic spinning
simply because there is no easy way to figure out if all the readers
are actively running or not. However, there are scenarios where
the readers are unlikely to sleep and optimistic spinning can help
performance.
This patch
The current way of using various reader, writer and waiting biases
in the rwsem code are confusing and hard to understand. I have to
reread the rwsem count guide in the rwsem-xadd.c file from time to
time to remind myself how this whole thing works. It also makes the
rwsem code harder to be
An RT task can do optimistic spinning only if the lock holder is
actually running. If the state of the lock holder isn't known, there
is a possibility that high priority of the RT task may block forward
progress of the lock holder if it happens to reside on the same CPU.
This will lead to
Before combining owner and count, we are adding two new helpers for
accessing the owner value in the rwsem.
1) struct task_struct *rwsem_get_owner(struct rw_semaphore *sem)
2) bool is_rwsem_reader_owned(struct rw_semaphore *sem)
Signed-off-by: Waiman Long
---
kernel/locking/rwsem-xadd.c | 15
On 64-bit architectures, each rwsem writer will have its unique lock
word for acquiring the lock. Right now, the writer code recomputes the
lock word every time it tries to acquire the lock. This is a waste of
time. The lock word is now cached and reused when it is needed.
On 32-bit
With the merging of owner into count for x86-64, there is only 16 bits
left for reader count. It is theoretically possible for an application to
cause more than 64k readers to acquire a rwsem leading to count overflow.
To prevent this dire situation, the most significant bit of the count
is now
Hi Mukesj,
On Thu, Mar 28, 2019 at 4:31 PM Mukesh Ojha wrote:
> On 3/28/2019 6:43 PM, Geert Uytterhoeven wrote:
> > The err_remove_chip block is too coarse, and may perform cleanup that
> > must not be done. E.g. if of_gpiochip_add() fails, of_gpiochip_remove()
> > is still called, causing:
> >
On 2019-03-28 4:03 a.m., Anup Patel wrote:
> I understand that this patch is inline with your virtual memory layout cleanup
> but the way we map virtual memory in swapper_pg_dir is bound to change.
>
> We should not be mapping complete virtual memory in swapper_pd_dir()
> rather we should only
Hi Serge,
On Thu, Mar 28, 2019 at 11:05 AM Serge E. Hallyn wrote:
>
> On Thu, Feb 28, 2019 at 11:27:38AM -0800, Dmitry Torokhov wrote:
> > Hi Eric,
> >
> > Currently, unless caller has CAP_SETGID in parent namespace, we can
> > only map effective group id in the new user namespace. Would it be
>
On Mon, 25 Mar 2019 20:41:34 +0800, Zhiyong Tao wrote:
> The commit adds mt8183 compatible node in binding document.
>
> Signed-off-by: Zhiyong Tao
> ---
> .../devicetree/bindings/pinctrl/pinctrl-mt8183.txt | 132
> +
> 1 file changed, 132 insertions(+)
> create mode
On Mon, 25 Mar 2019 10:57:55 -0500, thor.tha...@linux.intel.com wrote:
> From: Thor Thayer
>
> Add peripheral bindings for Stratix10 EDAC to capture
> the differences between the ARM64 and ARM32 architecture.
>
> Signed-off-by: Thor Thayer
> ---
> v2-3 No change
> ---
>
Hello,
Chong Qiao wrote:
> KGDB_call_nmi_hook is called by other cpu through smp call.
> MIPS smp call is processed in ipi irq handler and regs is saved in
> handle_int.
> So kgdb_call_nmi_hook get regs by get_irq_regs and regs will be passed
> to kgdb_cpu_enter.
>
> Signed-off-by: Chong Qiao
>
On Thu, Mar 28, 2019 at 11:30:52AM -0700, Dmitry Torokhov wrote:
> Hi Serge,
>
> On Thu, Mar 28, 2019 at 11:05 AM Serge E. Hallyn wrote:
> >
> > On Thu, Feb 28, 2019 at 11:27:38AM -0800, Dmitry Torokhov wrote:
> > > Hi Eric,
> > >
> > > Currently, unless caller has CAP_SETGID in parent
Hello,
Thomas Bogendoerfer wrote:
> smatch complaint:
>
> arch/mips/sgi-ip27/ip27-irq.c:123 shutdown_bridge_irq()
> warn: variable dereferenced before check 'hd' (see line 121)
>
> Fix it by removing local variable and use hd->pin directly.
>
> Fixes: 69a07a41d908 ("MIPS: SGI-IP27: rework HUB
On Thu, 28 Mar 2019 17:48:45 +
Haiyang Zhang wrote:
> +static inline void netvsc_tx_enable(struct netvsc_device *nvscdev,
> + struct net_device *ndev)
> +{
> + nvscdev->tx_disable = false;
> + mb(); /* ensure queue wake up mechanism is on */
> +
> +
On Thu, Mar 28, 2019 at 11:15:53AM -0700, H. Peter Anvin wrote:
> So, per our conversation today, lets create a new, readonly, data structure
> pointed to by a single field in setup_header, in order to preserve what little
> space we have left in that structure (a whopping 24 bytes...)
>
> The new
On Tue, Mar 26, 2019 at 02:56:20PM +0100, Ibtsam Ul-Haq wrote:
> This adds devicetree bindings for TI TLA202x ADCs.
>
> Signed-off-by: Ibtsam Ul-Haq
> ---
> .../devicetree/bindings/iio/adc/ti-tla2024.txt | 45
> ++
> 1 file changed, 45 insertions(+)
> create mode
On Wed, 27 Mar 2019 18:08:27 +0530, Sibi Sankar wrote:
> From: Bjorn Andersson
>
> Add RPM power domain bindings for the qcs404 family of SoC
>
> Signed-off-by: Bjorn Andersson
> [sibis: Add supported rpmpd states for qcs404]
> Signed-off-by: Sibi Sankar
> ---
>
> skip adding Rob's R-b due
On Wed, 27 Mar 2019 18:08:30 +0530, Sibi Sankar wrote:
> Add RPM power domain bindings for the msm8998 family of SoC
>
> Signed-off-by: Sibi Sankar
> ---
> .../devicetree/bindings/power/qcom,rpmpd.txt | 1 +
> include/dt-bindings/power/qcom-rpmpd.h | 12
> 2
On 03/28/2019 05:42 PM, Mathieu Poirier wrote:
On Wed, Mar 20, 2019 at 06:49:38PM +, Suzuki K Poulose wrote:
We rely on the device names to find a CoreSight device on the
coresight bus. The device name however is obtained from the platform,
which is bound to the real platform/amba device.
On Thu, 28 Mar 2019 10:19:22 +0800, Bibby Hsieh wrote:
> "thread-num" is an unused property so we remove it from example.
>
> Signed-off-by: Bibby Hsieh
> ---
> Documentation/devicetree/bindings/mailbox/mtk-gce.txt | 1 -
> 1 file changed, 1 deletion(-)
>
Reviewed-by: Rob Herring
Hi Florian,
On Tue, Mar 26, 2019 at 10:03:34AM -0700, Florian Fainelli wrote:
> The 'event' variable may be unused in case only CONFIG_CPU_BMIPS5000
> being enabled:
>
> arch/mips/kernel/perf_event_mipsxx.c: In function 'mipsxx_pmu_enable_event':
> arch/mips/kernel/perf_event_mipsxx.c:326:21:
On Thu, 28 Mar 2019 00:30:57 -0400
Kimberly Brown wrote:
> On Thu, Mar 21, 2019 at 04:04:20PM +, Michael Kelley wrote:
> > From: Kimberly Brown Sent: Wednesday, March 20,
> > 2019 8:48 PM
> > > > > > Adding more locks will solve the problem but it seems like overkill.
> > > > > > Why
On Thu, Mar 28, 2019 at 11:37 AM Serge E. Hallyn wrote:
>
> On Thu, Mar 28, 2019 at 11:30:52AM -0700, Dmitry Torokhov wrote:
> > Hi Serge,
> >
> > On Thu, Mar 28, 2019 at 11:05 AM Serge E. Hallyn wrote:
> > >
> > > On Thu, Feb 28, 2019 at 11:27:38AM -0800, Dmitry Torokhov wrote:
> > > > Hi Eric,
On Thu, Mar 28, 2019 at 10:19:24AM +0800, Bibby Hsieh wrote:
> Client hardware would send event to GCE hardware,
> so #event-cells, mediatek,gce-event-names, mediatek,gce-events.
> present the event.
>
> Signed-off-by: Bibby Hsieh
> ---
> Documentation/devicetree/bindings/mailbox/mtk-gce.txt |
On Thu, Mar 28, 2019 at 10:41:59AM -0700, Lucas De Marchi wrote:
> On Wed, Mar 27, 2019 at 8:40 AM Jessica Yu wrote:
> > >No. There are definitely not all modules. I have a builtin sha256_generic,
> > >but I can't find him in the /sys/module.
> >
> > Yeah, you'll only find builtin modules under
Hi Rob, Yash,
On 28/03/2019 13:16, Rob Herring wrote:
> On Tue, Mar 12, 2019 at 02:51:00PM +0530, Yash Shah wrote:
>> DT documentation for L2 cache controller added.
>> diff --git a/Documentation/devicetree/bindings/edac/sifive-edac-l2.txt
>>
On Mon, Mar 25, 2019 at 7:44 PM Wu Hao wrote:
>
> On Mon, Mar 25, 2019 at 12:50:40PM -0500, Alan Tull wrote:
> > On Sun, Mar 24, 2019 at 10:23 PM Wu Hao wrote:
> >
> > Hi Hao,
> >
> > Looks good, one question below.
> >
> > >
> > > Current driver checks if input bitstream file size is aligned or
On 3/27/19 11:58 PM, Michal Hocko wrote:
On Wed 27-03-19 19:09:10, Yang Shi wrote:
One question, when doing demote and promote we need define a path, for
example, DRAM <-> PMEM (assume two tier memory). When determining what nodes
are "DRAM" nodes, does it make sense to assume the nodes with
PCI fixes:
- Clear level-triggered interrupts for the bandwidth notification
supported added for v5.1 (Alexandru Gagniuc)
- Clear bandwidth notification interrupts before enabling them (Lukas
Wunner)
- Report post-enumeration bandwidth changes only once for multi-function
On Thu, 28 Mar 2019 10:35:08 +0800, Leo Yan wrote:
> Document DT binding for static (non-configurable) funnel and give an
> example for it.
>
> Cc: Mathieu Poirier
> Cc: Suzuki K Poulose
> Cc: Wanglai Shi
> Signed-off-by: Leo Yan
> ---
> .../devicetree/bindings/arm/coresight.txt | 45
On Mon, Mar 25, 2019 at 10:40:02AM -0400, Jerome Glisse wrote:
> From: Jérôme Glisse
>
> Every time i read the code to check that the HMM structure does not
> vanish before it should thanks to the many lock protecting its removal
> i get a headache. Switch to reference counting instead it is
On Sat, Mar 23, 2019 at 4:16 PM Fabien Parent wrote:
>
> Add binding documentation of pwrap for MT8516 SoCs.
>
> Signed-off-by: Fabien Parent
> ---
> Documentation/devicetree/bindings/soc/mediatek/pwrap.txt | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Rob Herring
On Sat, Mar 23, 2019 at 4:17 PM Fabien Parent wrote:
>
> Add binding documentation of topckgen for MT8516 SoC.
>
> Signed-off-by: Fabien Parent
> ---
> .../arm/mediatek/mediatek,topckgen.txt| 1 +
> include/dt-bindings/clock/mt8516-clk.h| 192 ++
> 2 files
On Sat, Mar 23, 2019 at 4:17 PM Fabien Parent wrote:
>
> Add binding documentation of infracfg for MT8516 SoC.
>
> Signed-off-by: Fabien Parent
> ---
> .../bindings/arm/mediatek/mediatek,infracfg.txt | 1 +
> include/dt-bindings/clock/mt8516-clk.h | 9 +
> 2
On Sat, Mar 23, 2019 at 4:17 PM Fabien Parent wrote:
>
> Add binding documentation of apmixedsys for MT8516 SoC.
>
> Signed-off-by: Fabien Parent
> ---
> .../bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 +
> include/dt-bindings/clock/mt8516-clk.h | 10 ++
> 2
On Thu, Mar 28, 2019 at 04:07:20AM -0700, Ira Weiny wrote:
> On Mon, Mar 25, 2019 at 10:40:02AM -0400, Jerome Glisse wrote:
> > From: Jérôme Glisse
> >
> > Every time i read the code to check that the HMM structure does not
> > vanish before it should thanks to the many lock protecting its
On Sat, Mar 23, 2019 at 4:17 PM Fabien Parent wrote:
>
> Add binding documentation of pinctrl-mt65xx for MT8516 SoC.
>
> Signed-off-by: Fabien Parent
> ---
> Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Rob Herring
On Thu 28-03-19 11:58:57, Yang Shi wrote:
>
>
> On 3/27/19 11:58 PM, Michal Hocko wrote:
> > On Wed 27-03-19 19:09:10, Yang Shi wrote:
> > > One question, when doing demote and promote we need define a path, for
> > > example, DRAM <-> PMEM (assume two tier memory). When determining what
> > >
On Sat, Mar 23, 2019 at 4:17 PM Fabien Parent wrote:
>
> Add binding documentation of mtk-timer for MT8516 SoC.
>
> Signed-off-by: Fabien Parent
> ---
> Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Rob Herring
On Sat, Mar 23, 2019 at 4:17 PM Fabien Parent wrote:
>
> Add binding documentation of spi-mt65xx for MT8516 SoC.
>
> Signed-off-by: Fabien Parent
> ---
> Documentation/devicetree/bindings/spi/spi-mt65xx.txt | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Rob Herring
On Sat, Mar 23, 2019 at 4:17 PM Fabien Parent wrote:
>
> Add binding documentation of mtk-uart for MT8516 SoC.
>
> Signed-off-by: Fabien Parent
> ---
> Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Rob Herring
On Sat, Mar 23, 2019 at 4:17 PM Fabien Parent wrote:
>
> Add binding documentation of mediatek,sysirq for MT8516 SoC.
>
> Signed-off-by: Fabien Parent
> ---
> .../bindings/interrupt-controller/mediatek,sysirq.txt | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Acked-by: Rob
On Sat, Mar 23, 2019 at 4:17 PM Fabien Parent wrote:
>
> Add binding documentation of i2c-mtk for MT8516 SoC.
>
> Signed-off-by: Fabien Parent
> ---
> Documentation/devicetree/bindings/i2c/i2c-mtk.txt | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Rob Herring
On Sat, Mar 23, 2019 at 4:17 PM Fabien Parent wrote:
>
> Add binding documentation of mtk-wdt for MT8516 SoC.
>
> Signed-off-by: Fabien Parent
> ---
> Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Rob Herring
On 3/28/2019 8:08 PM, Dan Carpenter wrote:
We forgot to set "err" on this error path.
What is "this" error path, please describe
like
"Currently, when irq_domain_add_linear() fails, error code does not get
set due to which
it return zero which is wrong.Fix it by setting appropriate
Commit d901b2760dc6 ("lib/scatterlist: Provide a DMA page iterator")
added the sg DMA iterator but a leftover remained in the sg_page_iter
documentation, remove it.
Cc: Jason Gunthorpe
Signed-off-by: Gal Pressman
---
include/linux/scatterlist.h | 10 +-
1 file changed, 5 insertions(+),
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to you on how the
On Sat, Mar 23, 2019 at 4:16 PM Fabien Parent wrote:
>
> Add binding documentation of the regulator for MT6392 SoCs.
>
> Signed-off-by: Fabien Parent
> ---
> .../bindings/regulator/mt6392-regulator.txt | 220 ++
> 1 file changed, 220 insertions(+)
> create mode 100644
>
On Wed, Mar 27, 2019 at 9:23 PM Xing, Cedric wrote:
>
> Hi Andy,
>
> > From: linux-sgx-ow...@vger.kernel.org [mailto:linux-sgx-
> > ow...@vger.kernel.org] On Behalf Of Andy Lutomirski
> >
> > I suppose the real question is: are there a significant number of
> > users who will want to run enclaves
On Sat, Mar 23, 2019 at 4:16 PM Fabien Parent wrote:
>
> Add the regulator nodes for the MT6392 PMIC.
>
> Signed-off-by: Fabien Parent
> ---
> arch/arm64/boot/dts/mediatek/mt6392.dtsi | 208 +++
> 1 file changed, 208 insertions(+)
> create mode 100644
On 03/28/2019 02:35 AM, Leo Yan wrote:
Document DT binding for static (non-configurable) funnel and give an
example for it.
Cc: Mathieu Poirier
Cc: Suzuki K Poulose
Cc: Wanglai Shi
Signed-off-by: Leo Yan
Reviewed-by: Suzuki K Poulose
On Sat, Mar 23, 2019 at 4:17 PM Fabien Parent wrote:
>
> The MT8516 SoC provides the following peripherals: GPIO, UART, USB2,
> SPI, eMMC, SDIO, NAND, Flash, ADC, I2C, PWM, Timers, IR, Ethernet, and
> Audio (I2S, SPDIF, TDM).
>
> This commit is adding the basic dtsi file with the support of the
>
On 03/28/2019 02:35 AM, Leo Yan wrote:
Since CoreSight hardware topology can use a 'hidden' funnel in the
trace data path, this kind funnel doesn't have register for accessing
and is used by default from hardware design perspective. Below is an
example for related hardware topology:
On Thu, 28 Mar 2019, Matthew Garrett wrote:
> On Wed, Mar 27, 2019 at 8:15 PM James Morris wrote:
> > OTOH, this seems like a combination of mechanism and policy. The 3 modes
> > are a help here, but I wonder if they may be too coarse grained still,
> > e.g. if someone wants to allow a specific
Hello,
syzbot tried to test the proposed patch but build/boot failed:
patch is already applied
Tested on:
commit: 0532a1b0 virt: vbox: Implement passing requestor info to t..
git tree:
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git
char-misc-linus
On 3/28/2019 10:40 PM, Colin King wrote:
From: Colin Ian King
The return from tty_write_room could potentially be negative if
a tty write_room driver returns an error number (not that any seem
to do). Rather than just check for a zero return, also check for
a -ve return. This avoids the
+arm-soc
On Mon, Mar 18, 2019 at 5:05 AM Maxime Ripard wrote:
>
> Commit fd73403a4862 ("dt-bindings: arm: Add SMP enable-method for
> Milbeaut") added support for a new cpu enable-method, but did so using
> tabulations to ident. This is however invalid in the syntax, and resulted
> in a failure
On Tue, Mar 26, 2019 at 06:52:33AM +, Anson Huang wrote:
> i.MX7ULP has TPM(Low Power Timer/Pulse Width Modulation Module)
> inside, it can support multiple PWM channels, all the channels
> share same counter and period setting, but each channel can
> configure its duty and polarity
Dumb question: this is basically a pty on steroids. Wouldn't this be
better done by enhancing the pty devices?
-0hpa
On 3/28/19 12:12 PM, Michal Hocko wrote:
On Thu 28-03-19 11:58:57, Yang Shi wrote:
On 3/27/19 11:58 PM, Michal Hocko wrote:
On Wed 27-03-19 19:09:10, Yang Shi wrote:
One question, when doing demote and promote we need define a path, for
example, DRAM <-> PMEM (assume two tier memory).
On Fri, Mar 15, 2019 at 10:22:47AM +0100, Maxime Ripard wrote:
> The node returned by of_graph_get_endpoint_by_regs has a reference taken,
> and we need to put that reference back when done with the node.
>
> However, the documentation for that node doesn't mention it, so let's make
> sure it
On Wed, Mar 20, 2019 at 06:49:39PM +, Suzuki K Poulose wrote:
> So far we have reused the name of the "platform" device for
> the CoreSight device. But this is not very intuitive when
> we move to ACPI. Also, the ACPI device names have ":" in them
> (e.g, ARMHC97C:01), which the perf tool
Hi,
On Thu, Mar 28, 2019 at 3:13 AM Pavel Machek wrote:
>
> > From: Douglas Anderson
> >
> > [ Upstream commit 31b265b3baaf55f209229888b7ffea523ddab366 ]
> >
> > As reported back in 2016-11 [1], the "ftdump" kdb command triggers a
> > BUG for "sleeping function called from invalid context".
> >
On 28/03/2019 18:42, Quentin Perret wrote:
> Hi Daniel,
>
> On Thursday 28 Mar 2019 at 18:27:49 (+0100), Daniel Lezcano wrote:
>> On 28/03/2019 11:22, Quentin Perret wrote:
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 2d9c39033c1a..3c09bdaaefd3 100644
On Thu, 28 Mar 2019 16:46:24 +0530
Naga Sureshkumar Relli wrote:
> Call spi_mem_default_supports_op() first, before calling controller
> specific ctlr->supports_op().
> With this, controller drivers can drop checking the buswidths again.
No, this was done on purpose, in case the controller does
This commit adds the TmFifo platform driver for Mellanox BlueField
Soc. TmFifo is a shared FIFO which enables external host machine
to exchange data with the SoC via USB or PCIe. The driver is based
on virtio framework and has console and network access enabled.
Reviewed-by: Vadim Pasternak
On 28/03/19 9:32 PM, Boris Brezillon wrote:
> On Thu, 28 Mar 2019 17:02:15 +1300
> Chris Packham wrote:
>
>> When the gpio-addr-flash.c driver was merged with physmap-core.c the
>> code to store the current gpio_values was lost. This meant that once a
>> gpio was asserted it was never
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