To help the compiler figure out that efi_printk() will not modify
the string it is given, make the input argument type const char*.
While at it, simplify the implementation as well.
Suggested-by: Joe Perches
Signed-off-by: Ard Biesheuvel
---
.../firmware/efi/libstub/efi-stub-helper.c| 19
From: Arvind Sankar
Use efi_err if we ignore a command-line dtb= argument, so that it shows
up even on a quiet boot.
Signed-off-by: Arvind Sankar
Link: https://lore.kernel.org/r/20200430182843.2510180-8-nived...@alum.mit.edu
Signed-off-by: Ard Biesheuvel
---
From: Joe Perches
Fix a couple typos in comments.
Signed-off-by: Joe Perches
Link:
https://lore.kernel.org/r/ec53e67b3ac928922807db3cb1585e911971dadc.1588273612.git@perches.com
Signed-off-by: Ard Biesheuvel
---
drivers/firmware/efi/libstub/pci.c | 2 +-
From: Arvind Sankar
In several places 64-bit values need to be split up into two 32-bit
fields, in order to be backward-compatible with the old 32-bit ABIs.
Instead of open-coding this, add a helper function to set a 64-bit value
as two 32-bit fields.
Signed-off-by: Arvind Sankar
Link:
From: Arvind Sankar
Factor out the initrd loading into a common function that can be called
both from the generic efi-stub.c and the x86-specific x86-stub.c.
Signed-off-by: Arvind Sankar
Link: https://lore.kernel.org/r/20200430182843.2510180-10-nived...@alum.mit.edu
Signed-off-by: Ard
From: Arvind Sankar
Commit
22090f84bc3f ("efi/libstub: unify EFI call wrappers for non-x86")
refactored the macros that are used to provide wrappers for mixed-mode
calls on x86, allowing us to boot a 64-bit kernel on 32-bit firmware.
Unfortunately, this broke mixed mode boot due to the fact
From: Arvind Sankar
Rename pr_efi to efi_info and pr_efi_err to efi_err to make it more
obvious that they are part of the EFI stub and not generic printk infra.
Suggested-by: Joe Perches
Signed-off-by: Arvind Sankar
Link:
From: Arvind Sankar
Use efi_err instead of bare efi_printk for error messages.
Signed-off-by: Arvind Sankar
Link: https://lore.kernel.org/r/20200430182843.2510180-5-nived...@alum.mit.edu
Signed-off-by: Ard Biesheuvel
---
drivers/firmware/efi/libstub/x86-stub.c | 24
When building the x86 EFI stub with Clang, the libstub Makefile rules
that manipulate the ELF object files may throw an error like:
STUBCPY drivers/firmware/efi/libstub/efi-stub-helper.stub.o
strip: drivers/firmware/efi/libstub/efi-stub-helper.stub.o: Failed to find
link section for
From: Arvind Sankar
efi_parse_options can fail if it is unable to allocate space for a copy
of the command line. Check the return value to make sure it succeeded.
Signed-off-by: Arvind Sankar
Link: https://lore.kernel.org/r/20200430182843.2510180-12-nived...@alum.mit.edu
Signed-off-by: Ard
On Fri, May 8, 2020 at 9:16 AM Christoph Hellwig wrote:
>
> Hi all,
>
> various bio based drivers use queue->queuedata despite already having
> set up disk->private_data, which can be used just as easily. This
> series cleans them up to only use a single private data pointer.
...but isn't the
On Fri, May 8, 2020 at 12:21 AM Ian Rogers wrote:
>
> On Fri, May 8, 2020 at 12:12 AM Andrii Nakryiko
> wrote:
> >
> > On Thu, May 7, 2020 at 11:40 PM Ian Rogers wrote:
> > >
> > > If bits is 0, the case when the map is empty, then the >> is the size of
> > > the register which is undefined
On 5/8/20 7:40 AM, Arnd Bergmann wrote:
> One cannot select DEVICE_PRIVATE when its dependencies are disabled:
>
> WARNING: unmet direct dependencies detected for DEVICE_PRIVATE
> Depends on [n]: ZONE_DEVICE [=n]
> Selected by [m]:
> - TEST_HMM [=m] && RUNTIME_TESTING_MENU [=y] &&
On 5/8/20 7:40 AM, Arnd Bergmann wrote:
> CONFIG_DEVICE_PRIVATE cannot be selected in configurations
> without ZONE_DEVICE:
>
> WARNING: unmet direct dependencies detected for DEVICE_PRIVATE
> Depends on [n]: ZONE_DEVICE [=n]
> Selected by [y]:
> - DRM_NOUVEAU_SVM [=y] && HAS_IOMEM [=y] &&
This is easily reproducible via CC=clang+CONFIG_STAGING=y+CONFIG_VT6656=m.
It turns out that if your config tickles __builtin_constant_p via
differences in choices to inline or not, these statements produce
invalid assembly:
$ cat foo.c
long a(long b, long c) {
asm("orb\t%1, %0" : "+q"(c):
Hi Hemant,
On Fri, May 08, 2020 at 10:34:13AM -0700, Hemant Kumar wrote:
> Hi Mani,
>
> On 5/7/20 10:45 PM, Manivannan Sadhasivam wrote:
> > On Tue, May 05, 2020 at 03:47:07PM -0700, Bhaumik Bhatt wrote:
> > > From: Hemant Kumar
> > >
> > > MHI data completion handler function reads channel id
On Fri, May 8, 2020 at 11:06 AM Nick Desaulniers
wrote:
>
> This is easily reproducible via CC=clang+CONFIG_STAGING=y+CONFIG_VT6656=m.
>
> It turns out that if your config tickles __builtin_constant_p via
> differences in choices to inline or not, these statements produce
> invalid assembly:
>
>
On Thu, May 7, 2020 at 2:34 PM Arnd Bergmann wrote:
>
> Building a kernel with clang sometimes fails with an objtool error in dlm:
>
> fs/dlm/lock.o: warning: objtool: revert_lock_pc()+0xbd: can't find jump dest
> instruction at .text+0xd7fc
>
> The problem is that BUG() never returns and the
Hi Will,
On Fri, May 8, 2020 at 4:47 AM Will Deacon wrote:
>
> Yes, please! And please include Daniel's acks on the BPF changes too. It's a
> public holiday here in the UK today, but I can pick this up next week.
Thanks!
> Nice! Two things:
>
> (1) I really think you should give a talk on this
On 5/8/2020 10:15 AM, Stanley Chu wrote:
Allow flush threshold for WriteBooster to be customizable by
vendors. To achieve this, make the value as a variable in struct
ufs_hba first.
Signed-off-by: Stanley Chu
---
drivers/scsi/ufs/ufshcd.c | 6 --
drivers/scsi/ufs/ufshcd.h | 1 +
2
> > It does have a numeric version defined for EISA types. OTOH I suspect that
> > your right. If there were a "PHY\VEN_ID_" definition, it may not
> > be ideal to parse it. Instead the normal ACPI model of exactly matching the
> > complete string in the phy driver might be more
This patch series introduces several optimizations to the arm64 BPF JIT.
The optimizations make use of arm64 immediate instructions to avoid
loading BPF immediates to temporary registers, when possible.
In the process, we discovered two bugs in the logical immediate encoding
function in
This patch fixes two issues present in the current function for encoding
arm64 logical immediates when using the 32-bit variants of instructions.
First, the code does not correctly reject an all-ones 32-bit immediate,
and returns an undefined instruction encoding.
Second, the code incorrectly
The current code for BPF_{AND,OR,XOR,JSET} BPF_K loads the immediate to
a temporary register before use.
This patch changes the code to avoid using a temporary register
when the BPF immediate is encodable using an arm64 logical immediate
instruction. If the encoding fails (due to the immediate
The current code for BPF_{ADD,SUB} BPF_K loads the BPF immediate to a
temporary register before performing the addition/subtraction. Similarly,
BPF_JMP BPF_K cases load the immediate to a temporary register before
comparison.
This patch introduces optimizations that use arm64 immediate add, sub,
On Fri, 8 May 2020, Tang Bin wrote:
> Delete unused initialized value, because 'retval' will be assigined
> by the function mv_ehci_enable(). And delete the extra blank lines.
>
> Signed-off-by: Zhang Shengju
> Signed-off-by: Tang Bin
> ---
Acked-by: Alan Stern
> Changes from v1
> - fix
This looks like a a good change to me.
Tested-by: Matthew Gerlach
On Thu, 7 May 2020, Gustavo A. R. Silva wrote:
The current codebase makes use of the zero-length array language
extension to the C90 standard, but the preferred mechanism to declare
variable-length types such as these ones
On Fri, 8 May 2020, Tang Bin wrote:
> Use the defined variable "dev" to make the code cleaner. And
> delete an extra blank line.
>
> Signed-off-by: Zhang Shengju
> Signed-off-by: Tang Bin
> ---
> Changes from v1:
> - fix the subject and the code.
> ---
Acked-by: Alan Stern
>
On Tue, May 5, 2020 at 7:24 AM Arnd Bergmann wrote:
>
> Checking the pointer value of st->chip_info->convst_channel is pointless
> since this this an array inside of a struct: even if st->chip_info is NULL,
> the pointer is non-zero. Clang warns about this:
>
> drivers/iio/adc/ad7476.c:312:40:
On Thu, Mar 05, 2020 at 04:48:12PM +0100, Vlastimil Babka wrote:
> On 3/2/20 8:36 PM, Minchan Kim wrote:
> > In upcoming patches, do_madvise will be called from external process
> > context so we shouldn't asssume "current" is always hinted process's
> > task_struct.
>
>
> > Furthermore, we
On Fri, May 8, 2020 at 2:06 PM Nick Desaulniers wrote:
>
> This is easily reproducible via CC=clang+CONFIG_STAGING=y+CONFIG_VT6656=m.
>
> It turns out that if your config tickles __builtin_constant_p via
> differences in choices to inline or not, these statements produce
> invalid assembly:
>
> $
From: David Matlack
Two new stats for exposing halt-polling cpu usage:
halt_poll_success_ns
halt_poll_fail_ns
Thus sum of these 2 stats is the total cpu time spent polling. "success"
means the VCPU polled until a virtual interrupt was delivered. "fail"
means the VCPU had to schedule out (either
On Wednesday, May 6, 2020 6:42:33 PM EDT Richard Guy Briggs wrote:
> > > > We can't be adding deleting fields based on how its triggered. If
> > > > they are unset, that is fine. The main issue is they have to behave
> > > > the same.
> > >
> > > I don't think the intent was to have fields swing
From: Peter Feiner
Optimization for avoiding lookups in mmu_page_hash. When there's a
single direct root, a shadow page has at most one parent SPTE
(non-root SPs have exactly one; the root has none). Thus, if an SPTE
is non-present, it can be linked to a newly allocated SP without
first checking
On Thu, 7 May 2020, Gustavo A. R. Silva wrote:
> The current codebase makes use of the zero-length array language
> extension to the C90 standard, but the preferred mechanism to declare
> variable-length types such as these ones is a flexible array member[1][2],
> introduced in C99:
>
> struct
Hello,
This series adds mailbox driver support for Qualcomm Inter Processor
Communications Controller (IPCC) block found in MSM chipsets. This block
is used to route interrupts between modems, DSPs and APSS (Application
Processor Subsystem).
The driver is modeled as a mailbox+irqchip driver. The
> Maybe dmc->df->lock is unnecessary to protect function
> exynos5_dmc_perf_events_check(dmc). If we have to protect,
> dmc->lock is more better and more effective.
> Also, it seems not needed to protect "if (ret) & dev_warn"
> branch.
I suggest to improve also this commit message.
* Please
Add devicetree YAML binding for Qualcomm Inter-Processor Communication
Controller (IPCC) block.
Signed-off-by: Manivannan Sadhasivam
---
.../bindings/mailbox/qcom-ipcc.yaml | 77 +++
include/dt-bindings/mailbox/qcom-ipcc.h | 33
2 files changed, 110
Add support for the Inter-Processor Communication Controller (IPCC)
block from Qualcomm that coordinates the interrupts (inbound & outbound)
for Multiprocessor (MPROC), COMPUTE-Level0 (COMPUTE-L0) & COMPUTE-Level1
(COMPUTE-L1) protocols for the Application Processor Subsystem (APSS).
This driver
Add MAINTAINERS entry for Qualcomm IPCC driver and its binding.
Signed-off-by: Manivannan Sadhasivam
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e64e5db31497..cc2fb991cc0d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14013,6
On Tue, 2020-05-05 at 12:18 -0700, a...@linux-foundation.org wrote:
> The patch titled
> Subject: checkpatch: use patch subject when reading from stdin
> has been added to the -mm tree. Its filename is
> checkpatch-use-patch-subject-when-reading-from-stdin.patch
Hey Andrew:
Please
This is easily reproducible via CC=clang+CONFIG_STAGING=y+CONFIG_VT6656=m.
It turns out that if your config tickles __builtin_constant_p via
differences in choices to inline or not, these statements produce
invalid assembly:
$ cat foo.c
long a(long b, long c) {
asm("orb\t%1, %0" : "+q"(c):
On Thu, 7 May 2020, Guilherme G. Piccoli wrote:
> Well...you can think that the problem we are trying to solve was more
> like...admin forgot if they triggered or not the compaction hehe
> So, counting on the user to keep track of it is what I'd like to
> avoid. And thinking about drop_caches
The move_lock is a per-memcg lock, but the VM accounting code that
needs to acquire it comes from the page and follows page->mem_cgroup
under RCU protection. That means that the page becomes unlocked not
when we drop the move_lock, but when we update page->mem_cgroup. And
that assignment doesn't
This patch series reworks memcg to charge swapin pages directly at
swapin time, rather than at fault time, which may be much later, or
not happen at all.
Changes in version 2:
- prevent double charges on pre-allocated hugepages in khugepaged
- leave shmem swapcache when charging fails to avoid
The memcg charging API carries a boolean @compound parameter that
tells whether the page we're dealing with is a hugepage.
mem_cgroup_commit_charge() has another boolean @lrucare that indicates
whether the page needs LRU locking or not while charging. The majority
of callsites know those
The cgroup swaprate throttling is about matching new anon allocations
to the rate of available IO when that is being throttled. It's the io
controller hooking into the VM, rather than a memory controller thing.
Rename mem_cgroup_throttle_swaprate() to cgroup_throttle_swaprate(),
and drop the
When memcg uses the generic vmstat counters, it doesn't need to do
anything at charging and uncharging time. It does, however, need to
migrate counts when pages move to a different cgroup in move_account.
Prepare the move_account function for the arrival of NR_FILE_PAGES,
NR_ANON_MAPPED,
Anonymous compound pages can be mapped by ptes, which means that if we
want to track NR_MAPPED_ANON, NR_ANON_THPS on a per-cgroup basis, we
have to be prepared to see tail pages in our accounting functions.
Make mod_lruvec_page_state() and lock_page_memcg() deal with tail
pages correctly, namely
The previous patches have simplified the access rules around
page->mem_cgroup somewhat:
1. We never change page->mem_cgroup while the page is isolated by
somebody else. This was by far the biggest exception to our rules
and it didn't stop at lock_page() or lock_page_memcg().
2. We charge
Right now, users that are otherwise memory controlled can easily
escape their containment and allocate significant amounts of memory
that they're not being charged for. That's because swap readahead
pages are not being charged until somebody actually faults them into
their page table. This can be
Swapin faults were the last event to charge pages after they had
already been put on the LRU list. Now that we charge directly on
swapin, the lrucare portion of the charge code is unused.
Signed-off-by: Johannes Weiner
Reviewed-by: Joonsoo Kim
---
include/linux/memcontrol.h | 5 ++--
There are no more users. RIP in peace.
Signed-off-by: Johannes Weiner
Reviewed-by: Joonsoo Kim
---
include/linux/memcontrol.h | 36 ---
mm/memcontrol.c| 126 +
2 files changed, 15 insertions(+), 147 deletions(-)
diff --git
A few cleanups to streamline the swap controller setup:
- Replace the do_swap_account flag with cgroup_memory_noswap. This
brings it in line with other functionality that is usually available
unless explicitly opted out of - nosocket, nokmem.
- Remove the really_do_swap_account flag that
With rmap memcg locking already in place for NR_ANON_MAPPED, it's just
a small step to remove the MEMCG_RSS_HUGE wart and switch memcg to the
native NR_ANON_THPS accounting sites.
Signed-off-by: Johannes Weiner
Reviewed-by: Joonsoo Kim
---
include/linux/memcontrol.h | 3 +--
mm/huge_memory.c
From: Alex Shi
Signed-off-by: Alex Shi
Signed-off-by: Johannes Weiner
---
.../admin-guide/cgroup-v1/memory.rst | 19 +++
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/Documentation/admin-guide/cgroup-v1/memory.rst
Memcg maintains a private MEMCG_RSS counter. This divergence from the
generic VM accounting means unnecessary code overhead, and creates a
dependency for memcg that page->mapping is set up at the time of
charging, so that page types can be told apart.
Convert the generic accounting sites to
Without swap page tracking, users that are otherwise memory controlled
can easily escape their containment and allocate significant amounts
of memory that they're not being charged for. That's because swap does
readahead, but without the cgroup records of who owned the page at
swapout, readahead
This is easily reproducible via CC=clang+CONFIG_STAGING=y+CONFIG_VT6656=m.
It turns out that if your config tickles __builtin_constant_p via
differences in choices to inline or not, these statements produce
invalid assembly:
$ cat foo.c
long a(long b, long c) {
asm("orb\t%1, %0" : "+q"(c):
With the page->mapping requirement gone from memcg, we can charge anon
and file-thp pages in one single step, right after they're allocated.
This removes two out of three API calls - especially the tricky commit
step that needed to happen at just the right time between when the
page is "set up"
Memcg maintains private MEMCG_CACHE and NR_SHMEM counters. This
divergence from the generic VM accounting means unnecessary code
overhead, and creates a dependency for memcg that page->mapping is set
up at the time of charging, so that page types can be told apart.
Convert the generic accounting
On Thu, Mar 12, 2020 at 01:23:39PM -0700, Minchan Kim wrote:
> On Thu, Mar 12, 2020 at 01:40:26PM +0100, Vlastimil Babka wrote:
> > On 3/10/20 11:20 PM, Minchan Kim wrote:
> > > On Thu, Mar 05, 2020 at 07:15:10PM +0100, Vlastimil Babka wrote:
> > >> On 3/2/20 8:36 PM, Minchan Kim wrote:
> > >> >
When replacing one page with another one in the cache, we have to
decrease the file count of the old page's NUMA node and increase the
one of the new NUMA node, otherwise the old node leaks the count and
the new node eventually underflows its counter.
Fixes: 74d609585d8b ("page cache: Add and
The try/commit/cancel protocol that memcg uses dates back to when
pages used to be uncharged upon removal from the page cache, and thus
couldn't be committed before the insertion had succeeded. Nowadays,
pages are uncharged when they are physically freed; it doesn't matter
whether the insertion
The uncharge batching code adds up the anon, file, kmem counts to
determine the total number of pages to uncharge and references to
drop. But the next patches will remove the anon and file counters.
Maintain an aggregate nr_pages in the uncharge_gather struct.
Signed-off-by: Johannes Weiner
On Tue, Mar 10, 2020 at 05:42:51PM -0700, Minchan Kim wrote:
> On Fri, Mar 06, 2020 at 12:14:19PM +0100, Vlastimil Babka wrote:
> > On 3/2/20 8:36 PM, Minchan Kim wrote:
> > > There is a demand[1] to support pid as well pidfd for process_madvise
> > > to reduce unnecessary syscall to get pidfd if
On Tue, May 05, 2020 at 03:54:44PM -0600, Alex Williamson wrote:
> With conversion to follow_pfn(), DMA mapping a PFNMAP range depends on
> the range being faulted into the vma. Add support to manually provide
> that, in the same way as done on KVM with hva_to_pfn_remapped().
>
> Signed-off-by:
pt., 8 maj 2020 o 07:54 Heiner Kallweit napisał(a):
>
> On 08.05.2020 00:56, Jakub Kicinski wrote:
> > On Thu, 7 May 2020 19:03:44 +0200 Bartosz Golaszewski wrote:
> >>> To implement Edwin's suggestion? Makes sense, but I'm no expert, let's
> >>> also CC Heiner since he was asking about it last
Thanks Mark!
On Fri, 2020-05-08 at 18:17 +0100, Mark Brown wrote:
> On Fri, May 08, 2020 at 06:40:43PM +0300, Matti Vaittinen wrote:
> > Add a KUnit test for the linear_ranges helper.
> >
> > Signed-off-by: Matti Vaittinen
> > Reviewed-by: Brendan Higgins
>
> This now generates:
>
>
This is a continuation of my work to clean up exec so it's more
difficult problems are approachable.
The changes correct some comments, stop open coding mutex_lock_killable,
and move the point_of_no_return variable up to when the
point_of_no_return actually occurs.
I don't think there is
On Thu, 7 May 2020, Al Cooper wrote:
> Add a new EHCI driver for Broadcom STB SoC's. A new EHCI driver
> was created instead of adding support to the existing ehci platform
> driver because of the code required to workaround bugs in the EHCI
> controller. The primary workround is for a bug where
merged tag 'riscv-for-linus-5.7-rc4'
The following changes since commit 1d2cc5ac6f6668cc15216d51051103c61467d7e8:
Merge tag 'riscv-for-linus-5.7-rc4' of
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux (2020-04-29 09:25:32
-0700)
are available in the Git repository at:
The comment describes work that now happens in unshare_sighand so
move the comment where it makes sense.
Signed-off-by: "Eric W. Biederman"
---
fs/exec.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/fs/exec.c b/fs/exec.c
index 3cc40048cc65..d4387bc92292
Signed-off-by: "Eric W. Biederman"
---
fs/exec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/fs/exec.c b/fs/exec.c
index d4387bc92292..82106241ed53 100644
--- a/fs/exec.c
+++ b/fs/exec.c
@@ -1296,7 +1296,7 @@ void __set_task_comm(struct task_struct *tsk, const char
Oleg modified the code that did
"mutex_lock_interruptible(>cred_guard_mutex)" to return
-ERESTARTNOINTR instead of -EINTR, so that userspace will never see a
failure to grab the mutex.
Slightly earlier Liam R. Howlett defined mutex_lock_killable for
exactly the same situation but it does it a
On 5/8/20 4:21 AM, Andy Shevchenko wrote:
> Yeah, I have locally something like this and I didn't dare to upstream because
> there is an issue. We have this information per DMA controller, while we
> actually need this on per DMA channel basis.
>
> Above will work only for synthesized DMA with all
Like exec_mm_release sync_mm_rss is about flushing out the state of
the old_mm, which does not need to happen under exec_update_mutex.
Make this explicit by moving sync_mm_rss outside of exec_update_mutex.
Signed-off-by: "Eric W. Biederman"
---
fs/exec.c | 3 ++-
1 file changed, 2
Move the handing of the point of no return from search_binary_handler
into __do_execve_file so that it is easier to find, and to keep
things robust in the face of change.
Make it clear that an existing fatal signal will take precedence over
a forced SIGSEGV by not forcing SIGSEGV if a fatal
On Tue, Apr 28, 2020 at 09:14:16AM +0800, Jiaxun Yang wrote:
> Don't disable MEM/IO decoding when a device have both non_compliant_bars
> and mmio_always_on.
>
> That would allow us quirk devices with junk in BARs but can't disable
> their decoding.
>
> Signed-off-by: Jiaxun Yang
Acked-by:
Make the code more robust by marking the point of no return sooner.
This ensures that future code changes don't need to worry about how
they return errors if they are past this point.
This results in no actual change in behavior as __do_execve_file does
not force SIGSEGV when there is a pending
...
> Signed-off-by: Gustavo A. R. Silva
> ---
> drivers/net/wireless/quantenna/qtnfmac/bus.h |2
> drivers/net/wireless/quantenna/qtnfmac/qlink.h | 54
> -
> 2 files changed, 28 insertions(+), 28 deletions(-)
Reviewed-by: Sergey Matyukevich
Regards,
Sergey
Currently direct access mode is used on platforms that have AHB window
(memory mapped window) larger than flash size. This feature is limited
to TI platforms as non TI platforms have < 1MB of AHB window.
Therefore introduce a driver quirk to disable DAC mode and set it for
non TI compatibles. This
This series is a subset of "[PATCH v12 0/4] spi: cadence-quadspi: Add
support for the Cadence QSPI controller" by Ramuthevar,Vadivel MuruganX
that intended to move
cadence-quadspi driver to spi-mem framework
Those patches were trying to accomplish too many things in a single set
of patches and
Make sure to undo the prior changes done by the driver when exiting due
to failure to acquire reset lines.
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
From: Ramuthevar Vadivel Murugan
Move cadence-quadspi driver to use spi-mem framework. This is required
to make the driver support for SPI NAND flashes in future.
Driver is feature compliant with existing SPI NOR version.
Signed-off-by: Ramuthevar Vadivel Murugan
Signed-off-by: Vignesh
Cadence QSPI provides a way to automatically decode CS based on the
offset accessed within memory map window. This feature cannot be
supported in spi-mem framework as controller driver would not have
access to flash geometry. Therefore drop this feature in preparation to
moving to spi-mem.
Note
If driver fails to acquire DMA channel then don't initialize
rx_dma_complete struct as it won't be used.
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi-nor/controllers/cadence-quadspi.c
From: Ramuthevar Vadivel Murugan
Now that cadence-quadspi has been converted to use spi-mem framework,
move it under drivers/spi/
Update license header to match SPI subsystem style
Signed-off-by: Ramuthevar Vadivel Murugan
Signed-off-by: Vignesh Raghavendra
---
On 5/7/2020 6:54 PM, Robin Murphy wrote:
> On 2020-05-06 9:01 pm, vji...@codeaurora.org wrote:
>> From: Vijayanand Jitta
>>
>> When ever a new iova alloc request comes iova is always searched
>> from the cached node and the nodes which are previous to cached
>> node. So, even if there is free
On 5/8/20 7:32 AM, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.4.223 release.
> There are 308 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses
On Fri, 8 May 2020 16:40:42 +0200
Joerg Roedel wrote:
> From: Joerg Roedel
>
> These functions are not needed anymore because the vmalloc and ioremap
> mappings are now synchronized when they are created or teared down.
>
> Remove all callers and function definitions.
>
> Signed-off-by:
On Fri, May 8, 2020 at 3:31 PM David Rientjes wrote:
> It doesn't make sense because it's only being done here for the entire
> system, there are also per-node sysfs triggers so you could do something
> like iterate over the nodemask of all nodes with memory and trigger
> compaction manually and
On Thu, May 07, 2020 at 02:41:30AM +0200, Thomas Gleixner wrote:
> Greg,
Good morning Thomas, I hope the week has gone well for you, the same
to everyone else reading this.
> "Dr. Greg" writes:
> > As an aside, for those who haven't spent the last 5+ years of their
> > life working with this
On Fri, May 08, 2020 at 05:05:03PM +0200, Arnd Bergmann wrote:
> On Fri, May 8, 2020 at 5:00 PM Jason Gunthorpe wrote:
> >
> > On Fri, May 08, 2020 at 04:40:09PM +0200, Arnd Bergmann wrote:
> > > CONFIG_DEVICE_PRIVATE cannot be selected in configurations
> > > without ZONE_DEVICE:
> >
> > It is
On 5/8/20 12:16 PM, Konstantin Khlebnikov wrote:
On 08/05/2020 17.49, Waiman Long wrote:
On 5/8/20 8:23 AM, Konstantin Khlebnikov wrote:
Count of buckets is required for estimating average length of hash
chains.
Size of hash table depends on memory size and printed once at boot.
Let's expose
On Fri, May 08, 2020 at 12:53:34PM +0100, Mark Brown wrote:
> On Fri, May 08, 2020 at 02:26:04PM +0300, Andy Shevchenko wrote:
> > On Fri, May 08, 2020 at 01:53:02PM +0300, Serge Semin wrote:
>
> > > Multi-block support provides a way to map the kernel-specific SG-table so
> > > the DW DMA device
Hi Daniel,
On 07/05/20 06:13PM, Daniel Walker (danielwa) wrote:
> On Thu, May 07, 2020 at 11:33:46PM +0530, Pratyush Yadav wrote:
> > On 07/05/20 09:20AM, Daniel Walker wrote:
> > > Some chips have 4B opcodes, but there is no way to know if they have
> > > them. This device tree option allows
Hi Bjorn,
On Tue, May 05, 2020 at 03:16:08PM -0700, Bjorn Andersson wrote:
> On Fri 24 Apr 13:01 PDT 2020, Mathieu Poirier wrote:
>
> > When synchronizing with a remote processor, it is entirely possible that
> > the remoteproc core is not the life cycle manager. In such a case core
> >
Adding some Google folks to the party.
On Wed, Apr 22, 2020 at 12:52:56AM +0300, Jarkko Sakkinen wrote:
> Intel(R) SGX is a set of CPU instructions that can be used by applications
> to set aside private regions of code and data. The code outside the enclave
> is disallowed to access the memory
Some boards have a fixed regulator and can't reach the voltage set
by the OPP table.
Add a range where the minimal voltage is the target and the maximal
voltage is 1.2V.
Suggested-by: Ondřej Jirman
Signed-off-by: Clément Péron
---
.../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 60
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