Hi Zijun,
> Controller ID info got by VSC EDL_PATCH_GETVER is very
> important, so improve its log level from DEBUG to INFO.
>
> Signed-off-by: Zijun Hu
> ---
> Changes in v4:
> - correct coding style of qca_read_soc_version()
>
> Changes in v3:
> - correct coding style
>
> Changes in v2:
> -
On Mon, Jun 01, 2020 at 01:54:29PM +0800, kbuild test robot wrote:
> tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
> master
> head: 3d77e6a8804abcc0504c904bd6e5cdf3a5cf8162
> commit: 9553d16fa671b9621c5e2847d08bd90d3be3349c init/kconfig: Add LD_VERSION
> Kconfig
>
Remove redundant header files.
Signed-off-by: Baolin Wang
---
drivers/hwspinlock/sprd_hwspinlock.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/hwspinlock/sprd_hwspinlock.c
b/drivers/hwspinlock/sprd_hwspinlock.c
index 36dc803..b157495 100644
---
Hi Zijun,
> serdev_device_write() is not appropriate at here because
> serdev_device_write_wakeup() is not used to release completion hold
> by the former at @write_wakeup member of struct serdev_device_ops.
>
> Fix by using serdev_device_write_buf() instead of serdev_device_write().
>
>
Hi Zijun,
> QCA6390 memdump VSE sometimes come to bluetooth driver
> with wrong sequence number as illustrated as follows:
> frame # in dec: frame data in hex
> 1396: ff fd 01 08 74 05 00 37 8f 14
> 1397: ff fd 01 08 75 05 00 ff bf 38
> 1414: ff fd 01 08 86 05 00 fb 5e 4b
> 1399: ff fd 01 08 77
On Fri, 29 May 2020 at 14:16, Stephen Rothwell wrote:
>
> Hi all,
>
> In commit
>
> 7b16993c2bb2 ("mmc: sdhci-msm: Clear tuning done flag while hs400 tuning")
>
> Fixes tag
>
> Fixes: ff06ce4 ("mmc: sdhci-msm: Add HS400 platform support")
>
> has these problem(s):
>
> - SHA1 should be at
In old days, worker threads are not shared among different
workqueues and destroy_workqueue() used kthread_stop() to destroy
all workers before going to destroy workqueue structures.
And kthread_stop() can ensure the scheduled (worker->scheduled)
work items and the linked work items queued by
2020년 5월 30일 (토) 오전 12:12, Johannes Weiner 님이 작성:
>
> On Fri, May 29, 2020 at 03:48:00PM +0900, Joonsoo Kim wrote:
> > 2020년 5월 29일 (금) 오전 2:02, Johannes Weiner 님이 작성:
> > > On Thu, May 28, 2020 at 04:16:50PM +0900, Joonsoo Kim wrote:
> > > > 2020년 5월 27일 (수) 오후 10:43, Johannes Weiner 님이 작성:
> > >
From: Pierre-Louis Bossart
The use of drvdata mixes two structures. There was no harm the first
structure is embedded as the first element of the second, but that's
not good. Make sure all drvdata is based on the 'sdw_cdns' structure.
While we are at it, remove indirections for 'dev' and 'cdns'
From: Pierre-Louis Bossart
No need to test link_mask twice
Suggested-by: Rander Wang
Signed-off-by: Pierre-Louis Bossart
Signed-off-by: Bard Liao
---
drivers/soundwire/intel_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soundwire/intel_init.c
This series is to split the original "soundwire: intel: transition to 3
steps initialization" patch into different patches for better review.
It also address comments from Vinod.
Pierre-Louis Bossart (6):
soundwire: intel: cleanups for indirections/logs
soundwire: intel: clarify drvdata and
From: Pierre-Louis Bossart
The code can be simplified a bit to have a more consistent use of
'dev' and 'bus', as well as move definitions around. This will help
make the major changes in follow-up patches easier to review.
Signed-off-by: Pierre-Louis Bossart
Signed-off-by: Bard Liao
---
From: Pierre-Louis Bossart
Rather than a plain-vanilla init/exit, this patch provides 3 steps in
the initialization needed for driver selection, machine driver
selection and deal with power rail dependencies.
- ACPI scan: this step is done at a very early stage to detect the
presence of a
From: Pierre-Louis Bossart
It's not clear how this code ever worked, the link information is used
in intel.c but never passed as platform_data.
Signed-off-by: Pierre-Louis Bossart
Signed-off-by: Bard Liao
---
drivers/soundwire/intel_init.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: Pierre-Louis Bossart
Make error handling simpler with devm_ allocation.
Signed-off-by: Pierre-Louis Bossart
Signed-off-by: Bard Liao
---
drivers/soundwire/intel_init.c | 14 +-
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/drivers/soundwire/intel_init.c
pm_runtime_get_sync() increments the runtime PM usage counter even
the call returns an error code. Thus a corresponding decrement is
needed on the error handling path to keep the counter balanced.
Fix this by adding the missed function call.
Fixes: 13d6eb20fc79a ("i2c: imx-lpi2c: add runtime pm
On 05/28/20 17:32 PM, Ian Rogers wrote:
>
> So on tip/perf/core with:
> 1c0cd2dbb993 perf jvmti: Fix jitdump for methods without debug info
> 3ce17c1e52f4 perf jvmti: remove redundant jitdump line table entries
>
> I've been trying variants of:
>
> Before:
> /tmp/perf/perf record -k 1 -e cycles:u
Add support for profiles in device tree to allow
different fan settings for trip point temp/hyst/pwm.
Signed-off-by: Sandipan Patra
---
arch/arm64/boot/dts/nvidia/tegra194-p2972-.dts | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git
Add support for profiles mode settings.
This allows different fan settings for trip point temp/hyst/pwm.
Tegra194 has multiple fan-profiles support.
Signed-off-by: Sandipan Patra
---
PATCH V2:
Cleaned pwm_fan_remove support as it is not required.
drivers/hwmon/pwm-fan.c | 92
From: Sandor Yu
Initial support for i.MX8MQ MHDP Displayport.
Add MHDP DP PHY configutation.
The features are same as MHDP DP bridge driver.
Signed-off-by: Sandor Yu
---
drivers/gpu/drm/imx/Kconfig | 1 +
drivers/gpu/drm/imx/Makefile| 1 +
From: Sandor Yu
The patch set initial support for Cadence MHDP(HDMI/DP) drm bridge
driver and iMX8MQ HDMI/DP.
The first patch drm/rockchip: prepare common code for cdns and rk dpi/dp driver
is from the link https://patchwork.kernel.org/patch/10788309/
that still in reviewing.
Files in
From: Sandor Yu
Create new directory drm/bridge/cadence.
Cadence MHDP DP and HDMI bridge dirver will added later.
drm/rockchip/cdn-dp-reg.c will separate to three files.
- cdns-mhdp-common.c: Provide basic MHDP register read/write via mailbox.
public firmware load, event, edid and HPD
From: Sandor Yu
Add initial support for i.MX8MQ MHDP HDMI.
Add MHDP HDMI PHY configuration.
The features are same as mhdp hdmi bridge driver.
Signed-off-by: Sandor Yu
---
drivers/gpu/drm/imx/mhdp/Kconfig | 5 +-
drivers/gpu/drm/imx/mhdp/Makefile | 2 +-
From: Sandor Yu
Document the bindings used for the Cadence MHDP HDMI/DP bridge.
Signed-off-by: Sandor Yu
---
.../bindings/display/bridge/cdns,mhdp.yaml| 46 +++
.../devicetree/bindings/display/imx/mhdp.yaml | 59 +++
2 files changed, 105 insertions(+)
create
From: Sandor Yu
This adds initial support for cadence MHDP HDMI bridge driver.
Basic HDMI functions are supported, that include:
-Video mode set on-the-fly
-Cable hotplug detect
-MAX support resolution to 3096x2160@60fps
-HDMI audio
-AV infoframe
-EDID read
-SCDC read
Signed-off-by:
From: Sandor Yu
- Extracted common fields from cdn_dp_device to a new cdns_mhdp_device
structure which will be used by two separate drivers later on.
- Moved some datatypes (audio_format, audio_info, vic_pxl_encoding_format,
video_info) from cdn-dp-core.c to cdn-dp-reg.h.
- Changed prefixes
From: Sandor Yu
This adds initial support for MHDP DP bridge driver.
Basic DP functions are supported, that include:
-Video mode set on-the-fly
-Cable hotplug detect
-MAX support resolution to 3096x2160@60fps
-Support DP audio
-EDID read via AUX
Signed-off-by: Sandor Yu
---
Sat, May 30, 2020 at 05:54:29PM CEST, ido...@idosch.org wrote:
>On Sat, May 30, 2020 at 05:52:31PM +0300, Vadym Kochan wrote:
[...]
>> > WARNING: do not add new typedefs
>> > #1064: FILE: drivers/net/ethernet/marvell/prestera/prestera_hw.h:32:
>> > +typedef void (*prestera_event_cb_t)
>> I may
From: Dinghao Liu Sent: Monday, June 1, 2020 2:17 PM
> pm_runtime_get_sync() increments the runtime PM usage counter even the
> call returns an error code. Thus a corresponding decrement is needed on the
> error handling path to keep the counter balanced.
>
> Fix this by adding the missed
> +@rv depends on !patch@
> +expression from,to,size;
> +position p;
> +statement S1,S2;
> +@@
> +
> +* to = \(kvmalloc@p\|kvzalloc@p\)(size,\(GFP_KERNEL\|GFP_USER\));
> + if (to==NULL || ...) S1
> + if (copy_from_user(to, from, size) != 0)
> + S2
How does the SmPL asterisk functionality
Hi,
> If param_offset is not 0, the memcpy length shouldn't be the
> true descriptor length.
>
> Fixes: a4b0e8a4e92b ("scsi: ufs: Factor out ufshcd_read_desc_param")
> Signed-off-by: Bean Huo
> ---
> drivers/scsi/ufs/ufshcd.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff
Hi Marc,
On 2020/5/31 0:31, Marc Zyngier wrote:
> Hi Alex,
>
> On 2020-05-30 11:46, Alexandru Elisei wrote:
>> Hi,
>
> [...]
>
diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c
index 48d0ec44ad77..e6378162cdef 100644
--- a/virt/kvm/arm/arm.c
+++ b/virt/kvm/arm/arm.c
Hi Krzysztof,
On 29.05.2020 19:43, Krzysztof Kozlowski wrote:
> On Fri, May 29, 2020 at 02:49:40PM +0200, Marek Szyprowski wrote:
>> Add custom voltage regulator coupler for Exynos5800 SoCs, which require
>> coupling between "vdd_arm" and "vdd_int" regulators. This coupler ensures
>> that coupled
The following changes since commit 2ef96a5bb12be62ef75b5828c0aab838ebb29cb8:
Linux 5.7-rc5 (2020-05-10 15:16:58 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/fs/fscrypt/fscrypt.git tags/fscrypt-for-linus
for you to fetch changes up to
Hi Jorge,
On Mon, 1 Jun 2020 at 04:41, Jorge Ramirez-Ortiz wrote:
>
> Some secure elements like NXP's SE050 sit on I2C buses. For OP-TEE to
> control this type of cryptographic devices it needs coordinated access
> to the bus, so collisions and RUNTIME_PM dont get in the way.
>
> This trampoline
The following changes since commit 2ef96a5bb12be62ef75b5828c0aab838ebb29cb8:
Linux 5.7-rc5 (2020-05-10 15:16:58 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/fs/fscrypt/fscrypt.git tags/fsverity-for-linus
for you to fetch changes up to
On Monday, June 1, 2020 8:47:22 AM EEST Vignesh Raghavendra wrote:
> dma_request_chan_by_mask() can throw EPROBE_DEFER if DMA provider
> is not yet probed. Currently driver just falls back to using PIO mode
> (which is less efficient) in this case. Instead return probe deferral
> error as is so
On Monday, June 1, 2020 8:47:23 AM EEST Vignesh Raghavendra wrote:
> Drop redundant WREN command in cqspi_erase() as SPI NOR core takes care
> of sending WREN command before sending erase command.
>
> Signed-off-by: Vignesh Raghavendra
> ---
> drivers/mtd/spi-nor/controllers/cadence-quadspi.c |
Even in failed case of pm_runtime_get_sync, the usage_count
is incremented. In order to keep the usage_count with correct
value call pm_runtime_put_autosuspend.
Signed-off-by: Navid
---
drivers/power/supply/bq24190_charger.c | 26 ++
1 file changed, 18 insertions(+), 8
On 2020-06-01 09:37, Viresh Kumar wrote:
On 29-05-20, 19:47, Sibi Sankar wrote:
opp_np needs to be subjected
to NULL check as well.
No, it isn't. It should already be valid and is set by the OPP core.
Actually we don't need to do of_node_get(opp_table->np) and just use
np, I did that to not
2020년 5월 29일 (금) 오후 3:50, Joonsoo Kim 님이 작성:
>
> 2020년 5월 29일 (금) 오전 4:25, Vlastimil Babka 님이 작성:
> >
> > On 5/27/20 8:44 AM, js1...@gmail.com wrote:
> > > From: Joonsoo Kim
> > >
> > > This patchset clean-up the migration target allocation functions.
> > >
> > > * Changes on v2
> > > - add
> pm_runtime_get_sync() increments the runtime PM usage counter even
> the call returns an error code. Thus a corresponding decrement is
> needed on the error handling path to keep the counter balanced.
>
> Fix this by adding the missed function call.
How do you think about a wording variant like
On 01/06/2020 05:55, Benjamin Herrenschmidt wrote:
On Tue, 2020-05-26 at 21:35 +0300, Paraschiv, Andra-Irina wrote:
This was needed to have an identifier for the overall NE logic - PCI
dev, ioctl and misc dev.
The ioctl and misc dev logic has pr_* logs, but I can update them to
dev_* with
On Jun 01 2020, Zong Li wrote:
> Add the missing header in file, it was losed in original implementation.
s/losed/lost/
Andreas.
--
Andreas Schwab, sch...@linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1
"And now for something completely different."
On Monday, June 1, 2020 8:47:24 AM EEST Vignesh Raghavendra wrote:
> From: Ramuthevar Vadivel Murugan
>
>
> Move cadence-quadspi driver to use spi-mem framework. This is required
> to make the driver support for SPI NAND flashes in future.
>
> Driver is feature compliant with existing SPI NOR
On Mon, Jun 1, 2020 at 2:48 PM Andreas Schwab wrote:
>
> On Jun 01 2020, Zong Li wrote:
>
> > Add the missing header in file, it was losed in original implementation.
>
> s/losed/lost/
>
> Andreas.
Thanks for correcting, let me modify it in the next version.
> --
> Andreas Schwab,
Hi Jassi,
Client can not know how mailbox controller implements TX done. There is no
API in mailbox_client.h to get this information.
I think it is framework' responsibility, not client, to handle controller'
different behavior. Thanks!
Regards,
Joe
-邮件原件-
发件人: Jassi Brar
Hi Hans,
On Thu, 16 Apr 2020 11:35:41 +0200
Hans Verkuil wrote:
I'm very sorry I missed a lot of your reviews in my V2, that wasn't on
purpose. I'll fix this on the next iteration, sorry about that.
Thank you very much for your review !
Maxime
>+Helen Koike (rkisp1 maintainer)
>
>A quick
Use the u64_to_user_ptr(x) kernel macro to correctly cast u64 to void*
Reported-by: kbuild test robot
Reviewed-by: Omer Shpigelman
Signed-off-by: Oded Gabbay
---
drivers/misc/habanalabs/command_submission.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Tomer Tayar
Fix the following smatch error in unmap_device_va():
error: uninitialized symbol 'rc'.
Signed-off-by: Tomer Tayar
Reviewed-by: Oded Gabbay
Signed-off-by: Oded Gabbay
---
drivers/misc/habanalabs/memory.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Hi, Mark,
On Monday, June 1, 2020 8:47:25 AM EEST Vignesh Raghavendra wrote:
> From: Ramuthevar Vadivel Murugan
>
>
> Now that cadence-quadspi has been converted to use spi-mem framework,
> move it under drivers/spi/
>
> Update license header to match SPI subsystem style
>
> Signed-off-by:
From: Navid
Even in failed case of pm_runtime_get_sync, the usage_count
is incremented. In order to keep the usage_count with correct
value call pm_runtime_put_autosuspend.
Signed-off-by: Navid
---
drivers/power/supply/bq24190_charger.c | 26 ++
1 file changed, 18
Drop configuration of Flash size, erase size and page size
configuration. Flash size is needed only if using AHB decoder (BIT 23 of
CONFIG_REG) which is not used by the driver.
Erase size and page size are needed if IP is configured to send WREN
automatically. But since SPI NOR layer takes care of
Make sure to undo the prior changes done by the driver when exiting due
to failure to acquire reset lines.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
---
drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff
This series is a subset of "[PATCH v12 0/4] spi: cadence-quadspi: Add
support for the Cadence QSPI controller" by Ramuthevar,Vadivel MuruganX
that intended to move
cadence-quadspi driver to spi-mem framework
Those patches were trying to accomplish too many things in a single set
of patches and
dma_request_chan_by_mask() can throw EPROBE_DEFER if DMA provider
is not yet probed. Currently driver just falls back to using PIO mode
(which is less efficient) in this case. Instead return probe deferral
error as is so that driver will be re probed once DMA provider is
available.
Signed-off-by:
On Wed, May 27, 2020 at 02:41:04PM +0100, Lorenzo Pieralisi wrote:
> On Tue, May 26, 2020 at 09:21:57PM +0100, Will Deacon wrote:
> > Hi Lorenzo, Hanjun, [+Nick]
> >
> > On Thu, May 21, 2020 at 06:37:38PM +0100, Lorenzo Pieralisi wrote:
> > > On Thu, May 21, 2020 at 11:09:53AM +0100, Will Deacon
Drop redundant WREN command in cqspi_erase() as SPI NOR core takes care
of sending WREN command before sending erase command.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
---
drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 5 -
1 file changed, 5 deletions(-)
diff
Currently direct access mode is used on platforms that have AHB window
(memory mapped window) larger than flash size. This feature is limited
to TI platforms as non TI platforms have < 1MB of AHB window.
Therefore introduce a driver quirk to disable DAC mode and set it for
non TI compatibles. This
If driver fails to acquire DMA channel then don't initialize
rx_dma_complete struct as it won't be used.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
---
drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Ramuthevar Vadivel Murugan
Move cadence-quadspi driver to use spi-mem framework. This is required
to make the driver support for SPI NAND flashes in future.
Driver is feature compliant with existing SPI NOR version.
Signed-off-by: Ramuthevar Vadivel Murugan
Signed-off-by: Vignesh
From: Ramuthevar Vadivel Murugan
Now that cadence-quadspi has been converted to use spi-mem framework,
move it under drivers/spi/
Update license header to match SPI subsystem style
Signed-off-by: Ramuthevar Vadivel Murugan
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
---
On 01/06/2020 05:59, Benjamin Herrenschmidt wrote:
On Wed, 2020-05-27 at 00:21 +0200, Greg KH wrote:
There are a couple of data structures with more than one member and multiple
field sizes. And for the ones that are not, gathered as feedback from
previous rounds of review that should
On Fri, May 29, 2020 at 03:45:47PM -0600, Alex Williamson wrote:
> On Sun, 17 May 2020 22:52:45 -0400
> Yan Zhao wrote:
>
> > This is a virtual irq type.
> > vendor driver triggers this irq when it wants to notify userspace to
> > remap PCI BARs.
> >
> > 1. vendor driver triggers this irq and
On 01/06/20 12:30 pm, tudor.amba...@microchip.com wrote:
> Hi, Mark,
>
> On Monday, June 1, 2020 8:47:25 AM EEST Vignesh Raghavendra wrote:
>> From: Ramuthevar Vadivel Murugan
>>
>>
>> Now that cadence-quadspi has been converted to use spi-mem framework,
>> move it under drivers/spi/
>>
>>
Add the missing header in file, it was lost in original implementation.
The warning message as follows:
- no previous prototype for 'patch_text_nosync' [-Wmissing-prototypes]
- no previous prototype for 'patch_text' [-Wmissing-prototypes]
Changed in v2:
- Correct the typo of commit message.
Even in failed case of pm_runtime_get_sync, the usage_count
is incremented. In order to keep the usage_count with correct
value call appropriate put.
Signed-off-by: Navid Emamdoost
---
drivers/pwm/pwm-img.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git
On Mon, 1 Jun 2020 at 04:49, Jarkko Sakkinen
wrote:
>
> On Fri, May 29, 2020 at 11:26:59AM +0300, Maxim Uvarov wrote:
> > Some drivers (like ftpm) can operate only after tee-supplicant
> > runs because of tee-supplicant provides things like storage
> > services. This patch splits probe of non
On 01-06-20, 12:09, Sibi Sankar wrote:
> On 2020-06-01 09:37, Viresh Kumar wrote:
> > On 29-05-20, 19:47, Sibi Sankar wrote:
> > > opp_np needs to be subjected
> > > to NULL check as well.
> >
> > No, it isn't. It should already be valid and is set by the OPP core.
> > Actually we don't need to
On 01/06/2020 06:02, Benjamin Herrenschmidt wrote:
On Wed, 2020-05-27 at 09:49 +0100, Stefan Hajnoczi wrote:
What about feature bits or a API version number field? If you add
features to the NE driver, how will userspace detect them?
Even if you intend to always compile userspace against the
On Fri, May 29, 2020 at 10:13 PM Jens Axboe wrote:
>
> On 5/29/20 8:11 AM, Kaitao Cheng wrote:
> > There is a function named ilog2() exist which can replace blksize.
> > The generated code will be shorter and more efficient on some
> > architecture, such as arm64. And ilog2() can be optimized
On Sun, May 24, 2020 at 3:42 PM Jiri Olsa wrote:
>
> Adding the way to create pmu event without the actual
> PMU being in place. This way we can test metrics defined
> for any processors.
>
> The interface is to define fake_pmu in struct parse_events_state
> data. It will be used only in tests
syzbot has bisected this bug to:
commit f2c2e717642c66f7fe7e5dd69b2e8ff5849f4d10
Author: Andrey Konovalov
Date: Mon Feb 24 16:13:03 2020 +
usb: gadget: add raw-gadget interface
bisection log: https://syzkaller.appspot.com/x/bisect.txt?x=164afcf210
start commit: bdc48fa1
On 01/06/20, Sumit Garg wrote:
> Hi Jorge,
hey
>
> On Mon, 1 Jun 2020 at 04:41, Jorge Ramirez-Ortiz wrote:
> >
> > Some secure elements like NXP's SE050 sit on I2C buses. For OP-TEE to
> > control this type of cryptographic devices it needs coordinated access
> > to the bus, so collisions and
Use dev_pm_set_wake_irq() instead of flag IRQF_NO_SUSPEND to enable
wakeup system feature for both freeze(s2idle) and mem(deep).
Signed-off-by: Ran Wang
---
Change in v2:
- Remove wakeup-source control since the irq should be able to wakeup.
And this is not the case that RTC interrupt line
On 30/05/20 3:24 pm, Leo Yan wrote:
> From: Tan Xiaojun
>
> This patch is to add four options to synthesize events which are
> described as below:
>
> 'f': synthesize first level cache events
> 'm': synthesize last level cache events
> 't': synthesize TLB events
> 'a': synthesize remote
Hi Avri,
On Sat, 2020-05-30 at 20:37 +, Avri Altman wrote:
> > @@ -2801,11 +2801,17 @@ int ufshcd_query_flag(struct ufs_hba *hba, enum
> > query_opcode opcode,
> > {
> > struct ufs_query_req *request = NULL;
> > struct ufs_query_res *response = NULL;
> > - int err,
Hi Michael,
Le 07/12/2019 à 18:20, Christophe Leroy a écrit :
call_do_irq() and call_do_softirq() are simple enough to be
worth inlining.
Inlining them avoids an mflr/mtlr pair plus a save/reload on stack.
It also allows GCC to keep the saved ksp_limit in an nonvolatile reg.
This is inspired
On 01/06/20 04:26, Krish Sadhukhan wrote:
> On 5/29/20 8:39 AM, Paolo Bonzini wrote:
>> According to the AMD manual, the effect of turning off EFER.SVME while a
>> guest is running is undefined. We make it leave guest mode immediately,
>> similar to the effect of clearing the VMX bit in
Anup Patel 於 2020年6月1日 週一 下午1:07寫道：
>
> The head text section (i.e. _start, secondary_start_sbi, etc) and the
> init section fall under same page table level-1 mapping.
>
> Currently, the runtime CPU hotplug is broken because we are marking
> init section as non-executable which in-turn marks
On Sun, May 24, 2020 at 3:42 PM Jiri Olsa wrote:
>
> Adding parse_events_fake interface to parse events
> and use fake pmu event in case pmu event is parsed.
>
> This way it's possible to parse events from PMUs
> which are not present in the system. It's available
> only for testing purposes
On 01/06/20 01:11, Krish Sadhukhan wrote:
>>
>> + svm->vmcb->control.int_ctl =
>> + (svm->nested.ctl.int_ctl & ~mask) |
>> + (svm->nested.hsave->control.int_ctl & mask);
>
>
> If this is the very first VMRUN, do we have any int_ctl saved in hsave ?
Yes,
>
> On Tue, 19 May 2020 at 11:18, 冯锐 wrote:
> >
> > > On Tue, 28 Apr 2020 at 05:44, 冯锐 wrote:
> > > >
> > > > >
> > > > > On Mon, Apr 27, 2020 at 11:41 AM 冯锐
> > > wrote:
> > > > > >
> > > > > >
> > > > > > > On Sun, Apr 26, 2020 at 09:25:46AM +0800,
> > > > > > > rui_f...@realsil.com.cn
> > >
On 31.05.2020 21:19, Jiri Olsa wrote:
> On Mon, May 25, 2020 at 05:17:31PM +0300, Alexey Budankov wrote:
>
> SBIP
>
>> +int fdarray__add_stat(struct fdarray *fda, int fd, short revents)
>> +{
>> +int pos = fda->nr_stat;
>> +
>> +if (pos >= FDARRAY__STAT_ENTRIES_MAX)
>> +
Hi Alexander,
On 5/30/20 3:07 AM, Alexander Monakov wrote:
The driver performs an extra check if the IOMMU's capabilities advertise
presence of performance counters: it verifies that counters are writable
by writing a hard-coded value to a counter and testing that reading that
counter gives
On 31.05.2020 21:19, Jiri Olsa wrote:
> On Mon, May 25, 2020 at 05:19:45PM +0300, Alexey Budankov wrote:
>
> SNIP
>
>> @@ -544,12 +598,10 @@ static enum counter_recovery stat_handle_error(struct
>> evsel *counter)
>> static int __run_perf_stat(int argc, const char **argv, int run_idx)
>> {
On Sun, May 31, 2020 at 05:04:47PM -0700, Ian Rogers wrote:
> On Sun, May 31, 2020 at 9:22 AM Jiri Olsa wrote:
> >
> > Jin Yao reported the issue (and posted first versions of this change)
> > with groups being defined over events with different cpu mask.
> >
> > This causes assert aborts in
On 2020-06-01 05:09, Anup Patel wrote:
On Sun, May 31, 2020 at 4:23 PM Marc Zyngier wrote:
On 2020-05-31 11:06, Anup Patel wrote:
[...]
Also, the PLIC spec is now owned by RISC-V foundation (not SiFive) so
we will have to rename the driver to "irq-riscv-plic" and will have a
new
generic
> From: Peng Fan
> Sent: Monday, June 1, 2020 11:43 AM
>
> Add i.MX8MQ/M/N/P compatible string to support i.MX8M SoCs
>
> Signed-off-by: Peng Fan
Reviewed-by: Dong Aisheng
BTW, Anson,
will you continue to help convert MU binding into json schemas?
Regards
Aisheng
On Sun, May 24, 2020 at 3:42 PM Jiri Olsa wrote:
>
> The test goes through all metrics compiled for arch
> within pmu events and try to parse them.
>
> The test also defines its own list of metrics and
> tries to parse them. It's handy for developing.
>
> Signed-off-by: Jiri Olsa
> ---
>
Hi all,
In commit
eb3eabb28cf2 ("ntb_tool: pass correct struct device to dma_alloc_coherent")
Fixes tag
Fixes: 5648e56 ("NTB: ntb_perf: Add full multi-port NTB API support")
has these problem(s):
- SHA1 should be at least 12 digits long
Can be fixed by setting core.abbrev to 12 (or
Hi Sylwester,
On 5/30/20 1:32 AM, Sylwester Nawrocki wrote:
> From: Marek Szyprowski
>
> This patch adds interconnect support to exynos-mixer. The mixer works
> the same as before when CONFIG_INTERCONNECT is 'n'.
>
> For proper operation of the video mixer block we need to ensure the
>
> From: Peng Fan
> Sent: Monday, June 1, 2020 11:43 AM
>
> Add mu node to let A53 could communicate with M Core.
>
> Signed-off-by: Peng Fan
> ---
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 9 +
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 9 +
>
Hello!
On 31.05.2020 21:07, Vladimir Oltean wrote:
From: Vladimir Oltean
Sometimes debugging a device is easiest using devmem on its register
map, and that can be seen with /proc/iomem. But some device drivers have
many memory regions. Take for example a networking switch. Its memory
map
Intel(R) SGX is a set of CPU instructions that can be used by applications
to set aside private regions of code and data. The code outside the enclave
is disallowed to access the memory inside the enclave by the CPU access
control.
There is a new hardware unit in the processor called Memory
From: Sean Christopherson
Include SGX bit to the PF error codes and throw SIGSEGV with PF_SGX when
a #PF with SGX set happens.
CPU throws a #PF with the SGX bit in the event of Enclave Page Cache Map
(EPCM) conflict. The EPCM is a CPU-internal table, which describes the
properties for a enclave
The following commit has been merged into the irq/core branch of tip:
Commit-ID: d77aeb5d403d379ff458e04fc07b5b86700270f2
Gitweb:
https://git.kernel.org/tip/d77aeb5d403d379ff458e04fc07b5b86700270f2
Author:Ingo Molnar
AuthorDate:Mon, 01 Jun 2020 09:45:27 +02:00
Committer:
From: Sean Christopherson
Add X86_FEATURE_SGX_LC, which informs whether or not the CPU supports SGX
Launch Control.
Add MSR_IA32_SGXLEPUBKEYHASH{0, 1, 2, 3}, which when combined contain a
SHA256 hash of a 3072-bit RSA public key. SGX backed software packages, so
called enclaves, are always
From: Sean Christopherson
Add X86_FEATURE_SGX from CPUID.(EAX=7, ECX=1), which informs whether the
CPU has SGX.
Add X86_FEATURE_SGX1 and X86_FEATURE_SGX2 from CPUID.(EAX=12H, ECX=0),
which describe the level of SGX support available [1].
Add IA32_FEATURE_CONTROL_SGX_ENABLE. BIOS can use this
Add kernel parameter to disable Intel SGX kernel support.
Tested-by: Sean Christopherson
Reviewed-by: Sean Christopherson
Signed-off-by: Jarkko Sakkinen
---
Documentation/admin-guide/kernel-parameters.txt | 2 ++
arch/x86/kernel/cpu/feat_ctl.c | 9 +
2 files changed,
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