From: Eugen Hristev
Add SAMA7G5 specific PLL defines to be referenced in a phandle as a
PMC_TYPE_CORE clock.
Suggested-by: Claudiu Beznea
Signed-off-by: Eugen Hristev
[claudiu.bez...@microchip.com: adapt comit message, adapt sama7g5.c]
Signed-off-by: Claudiu Beznea
---
Hi,
SAMA7G5 is capable of DVFS. The supported CPU clock frequencies could be
obtained from CPU PLL. The hardware block diagram for clock feeding the
CPU is as follows:
++
+-->|divider1|--> CPU clock
|
Hi YouChing,
YouChing Lin wrote on Wed, 4 Nov 2020 19:47:22
+0800:
> The Macronix MX35LF2GE4AD / MX35LF4GE4AD are 3V, 2G / 4Gbit serial
> SLC NAND flash device (with on-die ECC).
>
> Validated by read, erase, read back, write, read back and nandtest
> on Xilinx Zynq PicoZed FPGA board which
Hi
On Wed, Nov 04, 2020 at 11:16:18AM -0500, Thara Gopinath wrote:
>
> Hi Cristian,
>
> On 10/28/20 4:29 PM, Cristian Marussi wrote:
> > Add basic protocol handles definitions and helpers support.
> > All protocols initialization code and SCMI drivers probing is still
> > performed using the
On 11/3/20 5:20 PM, Mike Rapoport wrote:
From: Mike Rapoport
When DEBUG_PAGEALLOC or ARCH_HAS_SET_DIRECT_MAP is enabled a page may be
not present in the direct map and has to be explicitly mapped before it
could be copied.
Introduce hibernate_map_page() that will explicitly use
On 11/4/2020 9:52 PM, Bjorn Helgaas wrote:
External email: Use caution opening links or attachments
On Wed, Nov 04, 2020 at 05:13:07PM +0530, Vidya Sagar wrote:
On 11/4/2020 2:37 AM, Bjorn Helgaas wrote:
On Tue, Nov 03, 2020 at 08:57:01AM +0530, Vidya Sagar wrote:
On 11/3/2020 4:32 AM,
Hi Christophe,
Christophe Leroy wrote on Wed, 04 Nov
2020 18:33:53 +0100:
> Hi Miquel,
>
> I'm unable to boot 5.10-rc1 on my boards. I get the following error:
>
> [4.125811] nand: device found, Manufacturer ID: 0xad, Chip ID: 0x76
> [4.131992] nand: Hynix NAND 64MiB 3,3V 8-bit
> [
On 11/4/20 6:12 PM, Joe Perches wrote:
[...]
I'm not too sure about the comments, but I can find the time to look
over the output and adjust that if that's something you'd want me to do.
Up to you. I hardly looked at the output.
I'd generally prefer to use a single line comment like
/* AC
[+cc Jani, Joonas, Rodrigo, David, Daniel]
On Wed, Nov 04, 2020 at 05:35:06PM +0530, Tejas Upadhyay wrote:
> JSL re-uses the same stolen memory as ICL and EHL.
>
> Cc: Lucas De Marchi
> Cc: Matt Roper
> Signed-off-by: Tejas Upadhyay
I don't plan to do anything with this since previous
On 11/3/20 5:20 PM, Mike Rapoport wrote:
From: Mike Rapoport
When CONFIG_DEBUG_PAGEALLOC is enabled, it unmaps pages from the kernel
direct mapping after free_pages(). The pages than need to be mapped back
before they could be used. Theese mapping operations use
__kernel_map_pages() guarded
On Wed, Nov 04, 2020 at 03:01:44PM +0100, Guennadi Liakhovetski wrote:
> Hi Mathieu, Arnaud,
>
> I've tried the patch set with my VirtIO / vhost audio implementation,
> in general it worked quite well,
Very good - it would be nice if you could add your "Tested-by:" tags.
>
> On Tue, Oct 27,
Add support of BT656 embedded synchronization bus.
This mode allows to save hardware synchro lines hsync & vsync by replacing
them with synchro codes embedded in data stream.
This bus type is only compatible with 8 bits width data bus.
Due to reserved values 0x00 & 0xff used for synchro codes,
Explicitly set bus-type to parallel mode in DCMI endpoint (bus-type=5).
Signed-off-by: Hugues Fruchet
---
arch/arm/boot/dts/stm32mp157c-ev1.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts
b/arch/arm/boot/dts/stm32mp157c-ev1.dts
index
Add support of BT656 embedded synchronization bus mode in DCMI driver.
Add "bus-type" property and make it required so that there is no
ambiguity between parallel mode (bus-type=5) and BT656 mode (bus-type=6).
BT656 mode allows to save hardware synchro lines hsync & vsync by replacing
them with
Explicitly set bus-type to parallel mode in DCMI endpoint (bus-type=5).
Signed-off-by: Hugues Fruchet
---
arch/arm/boot/dts/stm32429i-eval.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
b/arch/arm/boot/dts/stm32429i-eval.dts
index 67e7648..7e10ae7
Add support of BT656 embedded synchronization bus.
This mode allows to save hardware synchro lines hsync & vsync
by replacing them with synchro codes embedded in data stream.
Add "bus-type" property and make it required so that there is no
ambiguity between parallel mode (bus-type=5) and BT656
Hi Miquel,
I'm unable to boot 5.10-rc1 on my boards. I get the following error:
[4.125811] nand: device found, Manufacturer ID: 0xad, Chip ID: 0x76
[4.131992] nand: Hynix NAND 64MiB 3,3V 8-bit
[4.136173] nand: 64 MiB, SLC, erase size: 16 KiB, page size: 512,
OOB size: 16
[
On Tue, Nov 03, 2020 at 05:32:26PM +0100, Guennadi Liakhovetski wrote:
> Hi Mathieu,
>
> On Tue, Oct 27, 2020 at 11:52:13AM -0600, Mathieu Poirier wrote:
> > Move structure rpmsg_ns_msg to its own header file so that
> > it can be used by other entities.
> >
> > Signed-off-by: Mathieu Poirier
>
On Mon, Nov 2, 2020 at 5:05 PM Andrey Konovalov wrote:
>
> With the intoduction of hardware tag-based KASAN some kernel checks of
> this kind:
>
> ifdef CONFIG_KASAN
>
> will be updated to:
>
> if defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS)
>
> x86 and s390 use a trick to
On Wed, Nov 4, 2020 at 6:13 PM Joe Perches wrote:
>
> On Wed, 2020-11-04 at 16:48 +0100, Maximilian Luz wrote:
> > On 11/4/20 6:13 AM, Joe Perches wrote:
> >
> > [...]
> >
> > > > Yes. I scanned drivers/acpi for trailing whitespaces after I noticed a
> > > > couple of them. I did not explicitly
On Mon, Nov 2, 2020 at 5:04 PM Andrey Konovalov wrote:
>
> asm/kasan.h relies on pgd_t type that is defined in asm/page.h. Include
> asm/page.h from asm/kasan.h.
>
> Signed-off-by: Andrey Konovalov
> ---
> Change-Id: I369a8f9beb442b9d05733892232345c3f4120e0a
> ---
>
Hi Lee,
On Wed, Nov 04, 2020 at 04:24:14PM +, Lee Jones wrote:
> Fixes the following W=1 kernel build warning(s):
>
> drivers/input/keyboard/cros_ec_keyb.c:72: warning: cannot understand
> function prototype: 'struct cros_ec_bs_map '
>
> Cc: Dmitry Torokhov
> Cc: Benson Leung
> Cc:
Hi Lee,
On Wed, Nov 04, 2020 at 04:24:09PM +, Lee Jones wrote:
> Fixes the following W=1 kernel build warning(s):
>
> drivers/input/mouse/cyapa.c:130: warning: Function parameter or member 'reg'
> not described in 'cyapa_i2c_write'
> drivers/input/mouse/cyapa.c:130: warning: Excess
Hi Benjamin,
We are using hid driver to inject hid report for D-Pad and Hat
switch events, like:
[0x00, 0x00, 0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00],
Check the HID format dump from kernel, this will send a 0x1 on HID usage
GenericDesktop.HatSwitch.
Do you
On Wed, 2020-11-04 at 16:48 +0100, Maximilian Luz wrote:
> On 11/4/20 6:13 AM, Joe Perches wrote:
>
> [...]
>
> > > Yes. I scanned drivers/acpi for trailing whitespaces after I noticed a
> > > couple of them. I did not explicitly scan for other stuff like spaces
> > > where there should be tabs,
On 10/13/2020 12:34 PM, Peter Zijlstra wrote:
Subject: perf,mm: Handle non-page-table-aligned hugetlbfs
From: Peter Zijlstra
Date: Fri, 9 Oct 2020 11:09:27 +0200
A limited nunmber of architectures support hugetlbfs sizes that do not
align with the page-tables (ARM64, Power, Sparc64). Add
sound/soc/intel/skylake/skl-topology.c: In function 'skl_tplg_complete':
sound/soc/intel/skylake/skl-topology.c:3642:1: warning: the frame size of 1256
bytes is larger than 1024 bytes [-Wframe-larger-than=]
3642 | }
| ^
vim +3642 sound/soc/intel/skylake/skl-topology.c
The following commit has been merged into the core/urgent branch of tip:
Commit-ID: 9d820f68b2bdba5b2e7bf135123c3f57c5051d05
Gitweb:
https://git.kernel.org/tip/9d820f68b2bdba5b2e7bf135123c3f57c5051d05
Author:Thomas Gleixner
AuthorDate:Wed, 04 Nov 2020 14:06:23 +01:00
On Wed, Nov 4, 2020 at 11:55 AM Andrew Lunn wrote:
>
> > https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/drivers/net/ethernet/microchip/lan743x_main.c?h=v5.9.3=6f197fb63850b26ef8f70f1bfe5900e377910a5a
>
> If you look at that patch, you see:
>
> - ret =
Use raw_spinlock in order to fix spurious messages about invalid context
when spinlock debugging is enabled. This happens because there is a legit
nested raw_spinlock->spinlock locking usage within IRQ-related code. IRQ
core uses raw spinlock and then Tegra GPIO driver uses a nested spinlock.
The
Add lockdep class in order to fix debug warnings that are coming from a
legit nested use of irq_set_irq_wake() by the Tegra GPIO driver.
WARNING: possible recursive locking detected
...
(irq_set_irq_wake) from (tegra_gpio_irq_set_wake)
(tegra_gpio_irq_set_wake) from (irq_set_irq_wake)
On Fri, Oct 30, 2020 at 10:56:09PM +0530, Sai Prakash Ranjan wrote:
> Hi Mathieu,
>
> On 2020-10-30 22:18, Mathieu Poirier wrote:
> > On Fri, Oct 30, 2020 at 01:29:56PM +0530, Sai Prakash Ranjan wrote:
> > > Hello guys,
> > >
> > > On 2020-10-24 02:07, Mathieu Poirier wrote:
> > > > On Fri, Oct
On Wed, Nov 04, 2020 at 12:39:13PM +0100, Hagen Paul Pfeifer wrote:
> > On 11/03/2020 5:30 PM Mike Rapoport wrote:
> >
> > > > As long as the task share the file descriptor, they can share the
> > > > secretmem pages, pretty much like normal memfd.
> > >
> > > Including process_vm_readv() and
On Wed, Nov 04, 2020 at 07:55:39PM +0800, Alex Shi wrote:
> @@ -1380,6 +1383,14 @@ struct lruvec *mem_cgroup_page_lruvec(struct page
> *page, struct pglist_data *pgd
> return lruvec;
> }
>
> +/**
> + * lock_page_lruvec - return lruvec for the locked page.
I would say "lock and return
On Wed, Nov 4, 2020 at 7:28 AM Andrew Jones wrote:
>
> On Wed, Nov 04, 2020 at 10:00:17AM -0500, Peter Xu wrote:
> > On Wed, Nov 04, 2020 at 01:16:31PM +0100, Andrew Jones wrote:
> > > If you don't mind I'd like to try and cleanup / generalize / refactor
> > > demand_paging_test.c and
On Tue, Nov 03, 2020 at 09:25:58AM -0500, Joel Fernandes (Google) wrote:
> Add counting of segment lengths of segmented callback list.
>
> This will be useful for a number of things such as knowing how big the
> ready-to-execute segment have gotten. The immediate benefit is ability
> to trace how
Hello Thara,
On Wed, 4 Nov 2020 at 17:16, Thara Gopinath wrote:
>
>
> Hi Cristian,
>
> On 10/28/20 4:29 PM, Cristian Marussi wrote:
> > Add basic protocol handles definitions and helpers support.
> > All protocols initialization code and SCMI drivers probing is still
> > performed using the
From: Ioana Ciornei
This patch set adds support for Rx/Tx capabilities on DPAA2 switch port
interfaces as well as fixing up so major blunders in how we take care of
the switching domains. The netdev community considers this as a basic
features, thus it's sent against the staging tree before
On Wed, Nov 04, 2020 at 05:47:27PM +0100, Johan Hovold wrote:
> The parallel-port restore operations is called when a driver claims the
> port and is supposed to restore the provided state (e.g. saved when
> releasing the port).
>
> Fixes: b69578df7e98 ("USB: usbserial: mos7720: add support for
From: Ioana Ciornei
The DPAA2 Switch is not capable to handle traffic in a VLAN unaware
fashion, thus the previous handling of both the accepted upper devices
and the SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING flag was wrong.
Fix this by checking if the bridge that we are joining is indeed VLAN
From: Ioana Ciornei
Until now, the DPAA2 switch was not capable to properly setup it's
switching domains depending on the existence, or lack thereof, of a
upper bridge device. This meant that all switch ports of a DPSW object
were switching by default even though they were not under the same
From: Ioana Ciornei
On the Rx path, when a pull-dequeue operation is performed on a
software portal, available frame descriptors are put in a ring - a DMA
memory storage - for further usage. Create the needed rings for both
frame queues used on the control interface.
Signed-off-by: Ioana
From: Ioana Ciornei
Enable the CTRL_IF of the switch object, now that all the pieces are in
place (buffer and queue management, interrupts, NAPI instances etc).
Signed-off-by: Ioana Ciornei
---
drivers/staging/fsl-dpaa2/ethsw/dpsw-cmd.h | 2 ++
drivers/staging/fsl-dpaa2/ethsw/dpsw.c | 37
From: Ioana Ciornei
Introduce a new structure to hold all necessary info related to an RX
queue for the control interface and populate the FQ IDs.
We only have one Rx queue and one Tx confirmation queue on the control
interface, both shared by all the switch ports.
Signed-off-by: Ioana Ciornei
Hi Thara,
thanks for reviewing.
On Wed, Nov 04, 2020 at 11:16:06AM -0500, Thara Gopinath wrote:
> Hi Cristian,
>
> On 10/28/20 4:29 PM, Cristian Marussi wrote:
> > Extend common protocol registration routines and provide some new generic
> > protocols' init/deinit helpers that tracks protocols'
From: Ioana Ciornei
Allocate and setup a buffer pool, needed on the Rx path of the control
interface. Also, define the Rx buffer size seen by the WRIOP from the
PAGE_SIZE buffers seeded.
Signed-off-by: Ioana Ciornei
---
drivers/staging/fsl-dpaa2/ethsw/dpsw-cmd.h | 12 +++
From: Ioana Ciornei
Implement the .ndo_start_xmit() callback for the switch port interfaces.
For each of the switch ports, gather the corresponding queue
destination ID (QDID) necessary for Tx enqueueing.
We'll reserve 64 bytes for software annotations, where we keep a skb
backpointer used on
From: Ioana Ciornei
Setup interrupts on the control interface queues. We do not force an
exact affinity between the interrupts received from a specific queue and
a cpu.
Also, the DPSW object version is incremented since the
dpsw_ctrl_if_set_queue() API is introduced in the v8.4 object
(first
From: Ioana Ciornei
The dpaa2-ethsw supports only one Rx queue that is shared by all switch
ports. This means that information about which port was the ingress port
for a specific frame needs to be passed in metadata. In our case, the
Flow Context (FLC) field from the frame descriptor holds this
Add "enable state" column to the clk summary. It's handy to know actual
hardware state of all clocks for debugging purposes. In conjunction with
clk_ignore_unused, this tells us what unused clocks are left on after
bootloader without disabling the clocks. It's also s useful debugging
information
On Wed, Nov 04, 2020 at 11:39:47AM -0500, Sven Van Asbroeck wrote:
> Hi Andrew, many thanks for looking at this patch !
>
> On Wed, Nov 4, 2020 at 11:27 AM Andrew Lunn wrote:
> >
> > > Note that as a side-effect, the devicetree phy mode now no longer
> > > has a default, and always needs to be
The i.MX6QP rev 1.1 SoC on my board is mis-identified by Linux:
the log (incorrectly) shows "i.MX6Q rev 2.1".
Correct this by assuming that every SoC that identifies as
i.MX6Q with rev >= 2.0 is really an i.MX6QP.
Signed-off-by: Sven Van Asbroeck
---
Tree: v5.10-rc2
To: Shawn Guo
Cc: Russell
Memory controller is interconnected with memory clients and with the
External Memory Controller. Document new interconnect property which
turns memory controller into interconnect provider.
Acked-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
Document new OPP table and voltage regulator properties which are needed
for supporting dynamic voltage-frequency scaling of the memory controller.
Some boards may have a fixed core voltage regulator, hence it's optional
because frequency scaling still may be desired.
Reviewed-by: Rob Herring
External memory controller is interconnected with memory controller and
with external memory. Document new interconnect property which turns
External Memory Controller into interconnect provider.
Acked-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
The tegra_read_ram_code() is used by EMC drivers and we're going to make
these driver modular, hence this function needs to be exported.
Acked-by: Thierry Reding
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/fuse/tegra-apbmisc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
Drivers that use tegra_sku_info and have COMPILE_TEST are failing to be
build due to the missing stub for tegra_sku_info, thus add the missing
stub.
Signed-off-by: Dmitry Osipenko
---
include/soc/tegra/fuse.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/soc/tegra/fuse.h
This series brings initial support for memory interconnect to Tegra20,
Tegra30 and Tegra124 SoCs.
For the starter only display controllers and devfreq devices are getting
interconnect API support, others could be supported later on. The display
controllers have the biggest demand for interconnect
There is superfluous zero in the registers base address and registers
size should be twice bigger.
Acked-by: Rob Herring
Acked-by: Thierry Reding
Signed-off-by: Dmitry Osipenko
---
.../bindings/memory-controllers/nvidia,tegra20-emc.txt | 2 +-
1 file changed, 1 insertion(+), 1
Fix the size of Tegra20 EMC registers, which should be twice bigger.
Acked-by: Krzysztof Kozlowski
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra20.dtsi
Most of Host1x devices have at least one memory client. These clients
are directly connected to the memory controller. The new interconnect
properties represent the memory client's connection to the memory
controller.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
> Gesendet: Dienstag, 03. November 2020 um 11:16 Uhr
> Von: "Thomas Gleixner"
> Any architecture which selects PCI_MSI_ARCH_FALLBACKS and does not have
> irqdomain support runs into:
>
> if (!d)
> bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
>
> which in turn makes
On Wed, Nov 04, 2020 at 11:48:27AM +0100, Paul Kocialkowski wrote:
> Hi,
>
> On Tue 27 Oct 20, 19:44, Maxime Ripard wrote:
> > On Tue, Oct 27, 2020 at 10:52:21AM +0100, Paul Kocialkowski wrote:
> > > Hi,
> > >
> > > On Mon 26 Oct 20, 17:14, Maxime Ripard wrote:
> > > > i2c? :)
> > >
> > > Oops,
Each memory client has unique hardware ID, add these IDs.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
include/dt-bindings/memory/tegra124-mc.h | 68
1 file changed, 68 insertions(+)
diff --git a/include/dt-bindings/memory/tegra124-mc.h
Add EMC OPP DVFS table that will be used for dynamic scaling of memory
frequency/voltage. Update board device-trees with optional EMC core supply
and remove unsupported OPPs.
Signed-off-by: Dmitry Osipenko
---
.../boot/dts/tegra20-acer-a500-picasso.dts| 7 ++
Now Internal and External Memory Controllers are memory interconnection
providers. This allows us to use interconnect API for tuning of memory
configuration. EMC driver now supports OPPs and DVFS.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/Kconfig | 3 +-
Add interconnect properties to the Memory Controller, External Memory
Controller and the Display Controller nodes in order to describe hardware
interconnection.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra30.dtsi | 27 ++-
1 file changed, 26 insertions(+),
Add EMC OPP DVFS/DFS tables and interconnect paths that will be used for
dynamic memory bandwidth scaling based on memory utilization statistics.
Remove unsupported EMC OPPs from board device-trees.
Note that ACTMON watches all memory interconnect paths, but we use a
single CPU-READ interconnect
Add nvidia,memory-controller to the Tegra20 External Memory Controller
node. This allows to perform a direct lookup of the Memory Controller
instead of walking up the whole tree. This puts Tegra20 device-tree on
par with Tegra30+.
Signed-off-by: Dmitry Osipenko
---
Document EMC DFS OPP table and interconnect paths that will be used
for scaling of system's memory bandwidth based on memory utilization
statistics. Previously ACTMON was supposed to drive EMC clock rate
directly, but now it should do it using interconnect framework in order
to support shared
The i.MX6QP rev 1.1 SoC on my board is mis-identified by Linux:
the log (incorrectly) shows "i.MX6Q rev 2.1".
Correct this by assuming that every SoC that identifies as
i.MX6Q with rev >= 2.0 is really an i.MX6QP.
Signed-off-by: Sven Van Asbroeck
---
Tree: v5.10-rc2
To: Shawn Guo
Cc: Russell
Use devm_platform_ioremap_resource() helper which makes code a bit
cleaner.
Acked-by: Thierry Reding
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/tegra124-emc.c | 4 +---
drivers/memory/tegra/tegra20-emc.c | 4 +---
2 files changed, 2 insertions(+), 6 deletions(-)
diff --git
Each memory client has unique hardware ID, add these IDs.
Acked-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
include/dt-bindings/memory/tegra20-mc.h | 53 +
1 file changed, 53 insertions(+)
diff --git a/include/dt-bindings/memory/tegra20-mc.h
Add modularization support to the Tegra20 EMC driver, which now can be
compiled as a loadable kernel module.
Acked-by: Thierry Reding
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/Kconfig | 2 +-
drivers/memory/tegra/tegra20-emc.c | 17 -
2 files changed, 13
EMC driver will become mandatory after turning it into interconnect
provider because interconnect users, like display controller driver, will
fail to probe using newer device-trees that have interconnect properties.
Thus make EMC driver to probe even if timings are missing in device-tree.
Document new OPP table and voltage regulator properties which are needed
for supporting dynamic voltage-frequency scaling of the memory controller.
Some boards may have a fixed core voltage regulator, hence it's optional
because frequency scaling still may be desired.
Reviewed-by: Rob Herring
It's useful to know the total number of underflow events and currently
the debug stats are getting reset each time CRTC is being disabled. Let's
account the overall number of events that doesn't get a reset.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
Now Internal and External memory controllers are memory interconnection
providers. This allows us to use interconnect API for tuning of memory
configuration. EMC driver now supports OPPs and DVFS.
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/Kconfig
On Wed, Nov 04, 2020 at 09:44:04AM +0100, Daniel Vetter wrote:
> On Tue, Nov 3, 2020 at 11:09 PM Dan Williams wrote:
> > On Tue, Nov 3, 2020 at 1:28 PM Bjorn Helgaas wrote:
> > > On Fri, Oct 30, 2020 at 11:08:11AM +0100, Daniel Vetter wrote:
> > > > There's three ways to access PCI BARs from
EMC driver will become mandatory after turning it into interconnect
provider because interconnect users, like display controller driver, will
fail to probe using newer device-trees that have interconnect properties.
Thus make EMC driver to probe even if timings are missing in device-tree.
Add modularization support to the Tegra30 EMC driver, which now can be
compiled as a loadable kernel module.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/Kconfig | 2 +-
drivers/memory/tegra/mc.c | 3 +++
drivers/memory/tegra/tegra30-emc.c | 17 -
3
On Wed, 2020-11-04 at 16:12 +0100, Thomas Gleixner wrote:
> From: Mike Galbraith
Hrmph. How about a suggested-by, or just take it. That dinky diag hit
the mark (not _entirely_ by accident, but..;) is irrelevant, you did
all of the work to make it a patch.
-Mike
> Gratian managed to
This patch moves ACTMON driver away from generating OPP table by itself,
transitioning it to use the table which comes from device-tree. This
change breaks compatibility with older device-trees in order to bring
support for the interconnect framework to the driver. This is a mandatory
change which
Add interconnect properties to the Memory Controller, External Memory
Controller and the Display Controller nodes in order to describe hardware
interconnection.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra124.dtsi | 25 +
1 file changed, 25 insertions(+)
The platform_get_irq() prints error message telling that interrupt is
missing, hence there is no need to duplicated that message in the drivers.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/mc.c | 4 +---
drivers/memory/tegra/tegra20-emc.c | 1 -
Remove tegra20-devfreq in order to replace it with a EMC_STAT based
devfreq driver. Previously we were going to use MC_STAT based
tegra20-devfreq driver because EMC_STAT wasn't working properly, but
now that problem is resolved. This resolves complications imposed by
the removed driver since it
Add devfreq support to the Tegra20 EMC driver. Memory utilization
statistics will be periodically polled from the memory controller and
appropriate minimum clock rate will be selected by the devfreq governor.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/Kconfig | 2 +
Previously we were using count-weight of the T124 for T30 in order to
get EMC clock rate that was reasonable for T30. In fact the count-weight
should be x2 times smaller on T30, but then devfreq was producing a bit
too low EMC clock rate for ISO memory clients, like display controller
for example.
The latency allowness is calculated based on buffering capabilities of
memory clients. Add FIFO sizes to the Tegra30 memory clients.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/tegra30.c | 66 ++
1 file changed, 66 insertions(+)
diff --git
Add interconnect properties to the Memory Controller, External Memory
Controller and the Display Controller nodes in order to describe hardware
interconnection.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20.dtsi | 26 +-
1 file changed, 25 insertions(+), 1
Each memory client has unique hardware ID, add these IDs.
Acked-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
include/dt-bindings/memory/tegra30-mc.h | 67 +
1 file changed, 67 insertions(+)
diff --git a/include/dt-bindings/memory/tegra30-mc.h
Now Internal and External memory controllers are memory interconnection
providers. This allows us to use interconnect API for tuning of memory
configuration. EMC driver now supports OPPs and DVFS. MC driver now
supports tuning of memory arbitration latency, which needs to be done
for ISO memory
Add common SoC-agnostic ICC framework which turns Tegra Memory Controller
into a memory interconnection provider. This allows us to use interconnect
API for tuning of memory configurations.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
Add EMC OPP DVFS/DFS tables and interconnect paths that will be used for
dynamic memory bandwidth scaling based on memory utilization statistics.
Update board device-trees with optional EMC core supply and remove
unsupported OPPs.
Note that ACTMON watches all memory interconnect paths, but we use
Add modularization support to the Tegra124 EMC driver, which now can be
compiled as a loadable kernel module.
Note that EMC clock must be registered at clk-init time, otherwise PLLM
will be disabled as unused clock at boot time if EMC driver is compiled
as a module. Hence add a prepare/complete
External memory controller is interconnected with memory controller and
with external memory. Document new interconnect property which turns
External Memory Controller into interconnect provider.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
Display controller (DC) performs isochronous memory transfers, and thus,
has a requirement for a minimum memory bandwidth that shall be fulfilled,
otherwise framebuffer data can't be fetched fast enough and this results
in a DC's data-FIFO underflow that follows by a visual corruption.
The Memory
Memory controller is interconnected with memory clients and with the
External Memory Controller. Document new interconnect property which
turns memory controller into interconnect provider.
Signed-off-by: Dmitry Osipenko
---
.../bindings/memory-controllers/nvidia,tegra124-emc.yaml | 1 +
Memory controller is interconnected with memory clients and with the
External Memory Controller. Document new interconnect property which
turns memory controller into interconnect provider.
Acked-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
Add missing PTC memory client latency allowness entry to the Tegra MC
drivers.
This prevents erroneous clearing of MC_INTSTATUS 0x0 register during
of the LA programming in tegra_mc_setup_latency_allowance() due to the
missing entry. Note that this patch doesn't fix any known problems.
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