Add smem node to support shared memory manager on SDX55 platform.
Signed-off-by: Manivannan Sadhasivam
Reviewed-by: Vinod Koul
---
arch/arm/boot/dts/qcom-sdx55.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi
b/arch/arm/boot/dts/qcom-sdx55.dtsi
Hi!
> commit 0ebcdd702f49aeb0ad2e2d894f8c124a0acc6e23 upstream.
>
> For a null_blk device with zoned mode enabled is currently initialized
> with a number of zones equal to the device capacity divided by the zone
> size, without considering if the device capacity is a multiple of the
> zone
From: Vinod Koul
This adds rpmpd node and opps for this node to the SDX55 dts.
Signed-off-by: Vinod Koul
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/boot/dts/qcom-sdx55.dtsi | 51 +++
1 file changed, 51 insertions(+)
diff --git
From: Vinod Koul
SDX55-mtp features PM8150B pmic, so include the dts as well
Signed-off-by: Vinod Koul
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/boot/dts/qcom-sdx55-mtp.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/qcom-sdx55-mtp.dts
Add TCSR Mutex node to support Qualcomm Hardware Mutex block on SDX55
platform.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/boot/dts/qcom-sdx55.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi
b/arch/arm/boot/dts/qcom-sdx55.dtsi
index
Add qpic_bam node to support QPIC BAM DMA controller on SDX55 platform.
Signed-off-by: Manivannan Sadhasivam
Reviewed-by: Vinod Koul
---
arch/arm/boot/dts/qcom-sdx55.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi
From: Vinod Koul
This adds SPMI node to SDX55 dts.
Signed-off-by: Vinod Koul
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/boot/dts/qcom-sdx55.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi
From: Vinod Koul
This adds DTS for PMIC PMX55 found in Qualcomm platforms.
Signed-off-by: Vinod Koul
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/boot/dts/qcom-pmx55.dtsi | 84 +++
1 file changed, 84 insertions(+)
create mode 100644
Enable QPIC NAND on SDX55-MTP board.
Signed-off-by: Manivannan Sadhasivam
Reviewed-by: Vinod Koul
---
arch/arm/boot/dts/qcom-sdx55-mtp.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx55-mtp.dts
b/arch/arm/boot/dts/qcom-sdx55-mtp.dts
index
From: Vinod Koul
This adds the regulators found on SDX55 MTP.
Signed-off-by: Vinod Koul
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/boot/dts/qcom-sdx55-mtp.dts | 164 +++
1 file changed, 164 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx55-mtp.dts
Add qpic_nand node to support QPIC NAND controller on SDX55 platform.
Since there is no "aon" clock in SDX55, a dummy clock is provided.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/boot/dts/qcom-sdx55.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git
From: Vinod Koul
This adds pincontrol node to SDX55 dts.
Signed-off-by: Vinod Koul
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/boot/dts/qcom-sdx55.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi
b/arch/arm/boot/dts/qcom-sdx55.dtsi
Enable BAM DMA on SDX55-MTP board.
Signed-off-by: Manivannan Sadhasivam
Reviewed-by: Vinod Koul
---
arch/arm/boot/dts/qcom-sdx55-mtp.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx55-mtp.dts
b/arch/arm/boot/dts/qcom-sdx55-mtp.dts
index
From: Vinod Koul
SDX55-mtp features PMX55 pmic, so include the dts as well
Signed-off-by: Vinod Koul
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/boot/dts/qcom-sdx55-mtp.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/qcom-sdx55-mtp.dts
Add devicetree support for SDHCI controller found in Qualcomm SDX55
platform. The SDHCI controller is based on the MSM SDHCI v5 IP.
Hence, the support is added by reusing the existing sdhci driver with
"qcom,sdhci-msm-v5" as the fallback.
Signed-off-by: Manivannan Sadhasivam
---
From: Bjorn Andersson
Add a node for the ARM SMMU found in the SDX55.
Signed-off-by: Bjorn Andersson
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/boot/dts/qcom-sdx55.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi
Add devicetree binding for Qualcomm SDX55 SMMU.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Signed-off-by: Manivannan Sadhasivam
Reviewed-by: Vinod Koul
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
Hi Bjorn,
This series updates devicetree for the SDX55 platform and the MTP board.
Most of the SDX55 specific driver codes are already merged and some of
existing driver support got reused.
Thanks,
Mani
Changes in v3:
* Dropped interrupts property in spmi-gpio node
* Used dma-controller node
From: Vinod Koul
This adds reserved memory nodes to the SDX55 dtsi as defined by v6 of
the memory map
Signed-off-by: Vinod Koul
[mani: moved modem regions to board dts]
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/boot/dts/qcom-sdx55-mtp.dts | 21 +++
The SDHCI controller on SDX55 is based on MSM SDHCI v5 IP. Hence,
document the compatible with "qcom,sdhci-msm-v5" as the fallback.
While at it, let's also sort the compatibles in ascending order.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Signed-off-by: Manivannan Sadhasivam
Reviewed-by:
On 6.01.21 12:44, HenryC Chen (陳建豪) wrote:
-Original Message-
From: Georgi Djakov [mailto:georgi.dja...@linaro.org]
Sent: Wednesday, January 06, 2021 4:14 PM
To: HenryC Chen (陳建豪)
Cc: Rob Herring; Matthias Brugger; Stephen Boyd; Ryan Case; Mark Brown; Mark
Rutland; Nicolas Boichat; Fan
The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: cb7f4a8b1fb426a175d1708f05581939c61329d4
Gitweb:
https://git.kernel.org/tip/cb7f4a8b1fb426a175d1708f05581939c61329d4
Author:Ying-Tsun Huang
AuthorDate:Tue, 15 Dec 2020 15:07:20 +08:00
Changed spinlock array to single. It is preparation for irq support which
is shared between two channels that's why spinlock should be only one.
Signed-off-by: Srinivas Neeli
---
Changes in V4:
-None.
Changes in V3:
-Created new patch for spinlock changes.
---
drivers/gpio/gpio-xilinx.c | 25
Add support for suspend and resume, pm runtime suspend and resume.
Added free and request calls.
Signed-off-by: Srinivas Neeli
---
Changes in V4:
-Adjust code to remove conflicts.
Changes in V3:
-Created new patch for suspend and resume.
---
drivers/gpio/gpio-xilinx.c | 94
Add check to see if gpio-width property does not exceed 32.
If it exceeds then return -EINVAL.
Signed-off-by: Srinivas Neeli
---
Changes in V4:
-New patch.
---
drivers/gpio/gpio-xilinx.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpio/gpio-xilinx.c
On Wed, Jan 06, 2021 at 07:48:51PM +0800, 李捷 wrote:
> From 0fbcd7e386898d829d3000d094358a91e626ee4a Mon Sep 17 00:00:00 2001
> From: Jie Li
> Date: Mon, 7 Dec 2020 08:05:07 +0800
> Subject: [PATCH] uio: uio_pci_generic: don't fail probe if pdev->irq equals to
> IRQ_NOTCONNECTED
>
> Some devices
Adds interrupt support to the Xilinx GPIO driver so that rising and
falling edge line events can be supported. Since interrupt support is
an optional feature in the Xilinx IP, the driver continues to support
devices which have no interrupt provided.
Depends on OF_GPIO framework for of_xlate
Common pattern of handling deferred probe can be simplified with
dev_err_probe(). Less code and also it prints the error value.
Signed-off-by: Srinivas Neeli
---
Changes in V4:
-New patch
---
drivers/gpio/gpio-xilinx.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git
This patch series does the following:
-Simplify with dev_err_probe().
-Reduce spinlock array to array.
-Add interrupt support
-Add support for suspend and resume
-Add check for gpio-width
---
Changes in V4:
-Created new patch to simplify code with dev_err_probe().
-Updated minor review comments.
://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Viresh-Kumar/scripts-dtc-Start-building-fdtoverlay-and-fdtdump/20210106-181140
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: x86_64-randconfig-a013-20210106 (attached
On Wed, Jan 06, 2021 at 06:29:53PM +0800, ting...@codeaurora.org wrote:
> Hi Will and Mark,
Hi Tingwei,
> In recent implementation of save/restore ARM debug registers in
> EL2/EL3, we found it's necessary to know whether self-host debug is
> enabled so EL2/EL3 can avoid saving/restoring debug
On Wed, 6 Jan 2021 10:45:30 +1000
Pavana Sharma wrote:
> Thanks Marek for catching this.
>
> I will have a closer look and update the patchset.
I also sent a reply patch with subject
"patch fixing mv88e6393x SERDES IRQ for Pavana's series"
it contains the changes necessary to your series.
On Wed, Jan 6, 2021 at 12:39 PM Ralf Schlatterbeck wrote:
>
> The hd44780 displays are often used with pcf8574 based I/O expanders.
> Add example to documentation.
>
> Signed-off-by: Ralf Schlatterbeck
Since Geert suggested it, it is customary to write Suggested-by: Geert
Uytterhoeven above
On Wed, Jan 6, 2021 at 1:12 PM Miguel Ojeda
wrote:
>
> - Normally, you will want to use scripts/get_maintainer.pl to know
> to whom send a given change. In this case, I am Cc'ing Rob, Geert and
> the devicetree mailing list which were missing.
(Actually Cc'ing Rob.)
Cheers,
Miguel
On Wed, Jan 06, 2021 at 11:53:59AM +, Mark Rutland wrote:
> On Tue, Jan 05, 2021 at 03:47:26PM +, Russell King - ARM Linux admin
> wrote:
> > Hi,
>
> Hi Russell,
>
> > This is an update on where I am with this long standing issue at the
> > current time.
> >
> > Since 5.4, I have been
On Wed, Jan 6, 2021 at 12:37 PM Ralf Schlatterbeck wrote:
>
> The Hitachi HD44780 is often used together with a PCF8574 based I2C
> I/O expander. It was non-obvious to me that the existing parallel
> connected version of the auxdisplay driver can already handle this
> configuration with
On Wed, Jan 06, 2021 at 01:04:04PM +0100, Johan Hovold wrote:
> On Tue, Jan 05, 2021 at 04:19:02PM +0100, Greg Kroah-Hartman wrote:
> > The correct user/kernel api for vibrator devices is the Input rumble
> > api, not a random sysfs file like the greybus vibrator driver currently
> > uses.
> >
>
This patchset implements the asynchronous mode support for ARMv8.5-A
Memory Tagging Extension (MTE), which is a debugging feature that allows
to detect with the help of the architecture the C and C++ programmatic
memory errors like buffer overflow, use-after-free, use-after-return, etc.
MTE is
MTE provides a mode that asynchronously updates the TFSR_EL1 register
when a tag check exception is detected.
To take advantage of this mode the kernel has to verify the status of
the register at:
1. Context switching
2. Return to user/EL0 (Not required in entry from EL0 since the kernel
mte_assign_mem_tag_range() is called on production KASAN HW hot
paths. It makes sense to optimize it in an attempt to reduce the
overhead.
Optimize mte_assign_mem_tag_range() based on the indications provided at
[1].
[1]
MTE provides an asynchronous mode for detecting tag exceptions. In
particular instead of triggering a fault the arm64 core updates a
register which is checked by the kernel at the first entry after the tag
exception has occurred.
Add support for MTE asynchronous mode.
The exception handling
Architectures supported by KASAN HW can provide a light mode of
execution. On an MTE enabled arm64 hw for example this can be identified
with the asynch mode of execution. If an async exception occurs, the
arm64 core updates a register which is asynchronously detected the next
time in which the
On Thu, Dec 24, 2020 at 12:10:07PM +0530, Sai Prakash Ranjan wrote:
> commit ecd7274fb4cd ("iommu: Remove unused IOMMU_SYS_CACHE_ONLY flag")
> removed unused IOMMU_SYS_CACHE_ONLY prot flag and along with it went
> the memory type setting required for the non-coherent masters to use
> system cache.
On Tue, Jan 05, 2021 at 03:47:26PM +, Russell King - ARM Linux admin wrote:
> Hi,
Hi Russell,
> This is an update on where I am with this long standing issue at the
> current time.
>
> Since 5.4, I have been struggling with several of my ARM64 systems, of
> different SoC vendors and
On 1/5/21 5:07 PM, Suzuki K Poulose wrote:
> On 1/5/21 9:29 AM, Anshuman Khandual wrote:
>>
>>
>> On 1/4/21 9:58 PM, Suzuki K Poulose wrote:
>>>
>>> Hi Anshuman,
>>>
>>> On 12/23/20 10:03 AM, Anshuman Khandual wrote:
Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is
Hi,
a few more fixes that arrived before the end of the year. Please pull,
thanks.
- a bunch of fixes related to transaction handle lifetime wrt various
operations (umount, remount, qgroup scan, orphan cleanup)
- async discard scheduling fixes
- fix item size calculation when item keys
The hd44780 displays are often used with pcf8574 based I/O expanders.
Add example to documentation.
Signed-off-by: Ralf Schlatterbeck
---
.../bindings/auxdisplay/hit,hd44780.yaml | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git
On Wed, Jan 06, 2021 at 04:08:10PM +0530, Shradha Todi wrote:
> get_features ops of pci_epc_ops may return NULL, causing NULL pointer
> dereference in pci_epf_test_bind function. Let us add a check for
> pci_epc_feature pointer in pci_epf_test_bind before we access it to avoid
> any such NULL
On Wed, Jan 6, 2021 at 6:50 PM Maxime Ripard wrote:
>
> Hi!
>
> On Sun, Jan 03, 2021 at 05:06:31AM -0600, Samuel Holland wrote:
> > This series adds system (complete power down) and runtime (clock gate)
> > PM hooks to the RSB controller driver. Tested on A64 and H6.
> >
> > Samuel Holland (4):
>
On 06.01.2021 01:58, Yang Shi wrote:
> The following patch is going to add nr_deferred into shrinker_map, the change
> will
> make shrinker_map not only include map anymore, so rename it to a more general
> name. And this should make the patch adding nr_deferred cleaner and readable
> and make
On Wed, Jan 06, 2021 at 05:46:22PM +0800, Qinglang Miao wrote:
>
>
> 在 2021/1/6 16:09, Markus Elfring 写道:
> > > > > A null-ptr-deref bug is reported by Hulk Robot like this:
> > > >
> > > > Can it be clearer to use the term “null pointer dereference” for the
> > > > final commit message?
> > >
On Wed, Jan 6, 2021 at 7:06 PM Maxime Ripard wrote:
>
> On Mon, Jan 04, 2021 at 10:54:19AM +, André Przywara wrote:
> > On 03/01/2021 10:00, Samuel Holland wrote:
> > > On boards where the only peripheral connected to PL0/PL1 is an X-Powers
> > > PMIC, configure the connection to use the RSB
On Wed 06-01-21 12:22:57, David Hildenbrand wrote:
> On 06.01.21 11:42, Michal Hocko wrote:
> > On Wed 06-01-21 10:56:19, David Hildenbrand wrote:
> > [...]
> >> Note that this is not sufficient in the general case. I already
> >> mentioned that we effectively override an already initialized
The Hitachi HD44780 is often used together with a PCF8574 based I2C
I/O expander. It was non-obvious to me that the existing parallel
connected version of the auxdisplay driver can already handle this
configuration with appropriate device tree magic. This patch documents
the necessary incantations
On 06.01.2021 01:58, Yang Shi wrote:
> Now shrinker's nr_deferred is per memcg for memcg aware shrinkers, add to
> parent's
> corresponding nr_deferred when memcg offline.
>
> Signed-off-by: Yang Shi
> ---
> include/linux/memcontrol.h | 1 +
> mm/memcontrol.c| 1 +
> mm/vmscan.c
> -Original Message-
> From: Shradha Todi
> Sent: Wednesday, January 6, 2021 4:20 PM
> To: linux-kernel@vger.kernel.org; linux-...@vger.kernel.org
> Cc: jingooh...@gmail.com; gustavo.pimen...@synopsys.com;
> r...@kernel.org; lorenzo.pieral...@arm.com; bhelg...@google.com;
>
> -Original Message-
> From: Shradha Todi
> Sent: Wednesday, January 6, 2021 4:15 PM
> To: linux-kernel@vger.kernel.org; linux-...@vger.kernel.org
> Cc: jingooh...@gmail.com; gustavo.pimen...@synopsys.com;
> r...@kernel.org; lorenzo.pieral...@arm.com; bhelg...@google.com;
>
Hi
On Wed, Jan 06, 2021 at 10:29:17AM +, Jonathan Cameron wrote:
> On Tue, 5 Jan 2021 23:09:20 +
> Jyoti Bhayana wrote:
>
> > Hi Jonathan,
> >
> > > So, sensor_max_range can effectively be exposed as a combination of
> > > scale and the *_raw_avail for a raw read (via the read_avail
On 01/05/21 08:44, Alexei Starovoitov wrote:
> > Any pointer to an example test I could base this on?
>
> selftests/bpf/
I was hoping for something more elaborate. I thought there's something already
there that do some verification for raw tracepoint that I could either extend
or replicate.
On 06.01.21 11:42, Michal Hocko wrote:
> On Wed 06-01-21 10:56:19, David Hildenbrand wrote:
> [...]
>> Note that this is not sufficient in the general case. I already
>> mentioned that we effectively override an already initialized memmap.
>>
>> ---
>>
>> [SECTION ]
>> Before:
: microblaze-randconfig-r016-20210106 (attached as .config)
compiler: microblaze-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
#
https
From: Chunguang Xu
Compared to direct pointer traversal, introducing a macro
will make the code more concise. But the introduction of
macros will make rq_qos_xxx() produce a redundant judgment,
usually this may not be a big problem.
Signed-off-by: Chunguang Xu
---
block/blk-rq-qos.c | 45
On Tue, Jan 05, 2021 at 12:34:14PM +0100, Borislav Petkov wrote:
> From: Borislav Petkov
>
> During boot, identify_secondary_cpu() calls at some point
> validate_apic_and_package_id() which calls topology_update_die_map() to
> update/verify the physical to logical DIE map of the CPUs on the
On Thu, Dec 17, 2020 at 02:31:18PM -0800, Reinette Chatre wrote:
> +#ifdef CONFIG_SMP
> +static void update_task_closid_rmid(struct task_struct *t)
> +{
> + if (task_curr(t))
> + smp_call_function_single(task_cpu(t), _update_task_closid_rmid,
> +
On 06.01.2021 01:58, Yang Shi wrote:
> Now nr_deferred is available on per memcg level for memcg aware shrinkers, so
> don't need
> allocate shrinker->nr_deferred for such shrinkers anymore.
>
> The prealloc_memcg_shrinker() would return -ENOSYS if !CONFIG_MEMCG or memcg
> is disabled
> by
On Tue, Jan 05, 2021 at 04:04:34PM -0800, Dexuan Cui wrote:
> When a Linux VM runs on Hyper-V, if the host toolstack doesn't support
> hibernation for the VM (this happens on old Hyper-V hosts like Windows
> Server 2016, or new Hyper-V hosts if the admin or user doesn't declare
> the hibernation
On 06.01.2021 01:58, Yang Shi wrote:
> Currently the number of deferred objects are per shrinker, but some slabs,
> for example,
> vfs inode/dentry cache are per memcg, this would result in poor isolation
> among memcgs.
>
> The deferred objects typically are generated by __GFP_NOFS
On Mon, Jan 04, 2021 at 10:54:19AM +, André Przywara wrote:
> On 03/01/2021 10:00, Samuel Holland wrote:
> > On boards where the only peripheral connected to PL0/PL1 is an X-Powers
> > PMIC, configure the connection to use the RSB bus rather than the I2C
> > bus. Compared to the I2C controller
On Wed, 2021-01-06 at 18:52 +0800, Ikjoon Jang wrote:
> On Wed, Jan 6, 2021 at 6:42 PM Weiyi Lu wrote:
> >
> > On Wed, 2021-01-06 at 18:25 +0800, Ikjoon Jang wrote:
> > > On Tue, Dec 22, 2020 at 9:14 PM Weiyi Lu wrote:
> > > >
> > > > Add MT8192 basic clock providers, include topckgen,
On Tue, Jan 05, 2021 at 06:20:05PM +, Michael Kelley wrote:
> From: Wei Liu Sent: Tuesday, January 5, 2021 9:51 AM
> >
> > We've observed crashes due to an empty cpu mask in
> > hyperv_flush_tlb_others. Obviously the cpu mask in question is changed
> > between the cpumask_empty call at the
On Sun, Jan 03, 2021 at 04:00:03AM -0600, Samuel Holland wrote:
> The Allwinner H6 SoC contains an RSB controller. It is almost completely
> undocumented, so it was missed when doing the initial SoC bringup.
>
> This series adds the clock/reset, pin configuration, and device tree
> node needed to
On Tue, Jan 05, 2021 at 04:52:28PM -0600, Josh Poimboeuf wrote:
> On Tue, Jan 05, 2021 at 12:48:20PM -0800, Randy Dunlap wrote:
> > On 1/4/21 6:50 PM, Stephen Rothwell wrote:
> > > Hi all,
> > >
> > > Changes since 20210104:
> > >
> >
> > on x86_64:
> >
> > vmlinux.o: warning: objtool:
On 2021-01-06 05:59, Chia-Wei, Wang wrote:
The eSPI interrupt controller acts as a SW IRQ number
decoder to correctly control/dispatch interrupts of
the eSPI peripheral, virtual wire, out-of-band, and
flash channels.
Signed-off-by: Chia-Wei, Wang
---
drivers/irqchip/Makefile | 2
> On Mon, 28 Dec 2020 16:14:17 -0500 Konstantin Ryabitsev wrote:
> > On Mon, Dec 28, 2020 at 01:05:26PM -0800, Florian Fainelli wrote:
> > > On 12/28/2020 12:23 PM, Konstantin Ryabitsev wrote:
> > > > On Thu, Dec 24, 2020 at 01:57:40PM -0800, Florian Fainelli wrote:
> > > Konstantin,
On Tue, Jan 05, 2021 at 12:16:11PM -0600, Bjorn Andersson wrote:
> On Tue 05 Jan 06:26 CST 2021, Manivannan Sadhasivam wrote:
>
> > From: Vinod Koul
> >
> > This adds the regulators found on SDX55 MTP.
> >
> > Signed-off-by: Vinod Koul
> > Signed-off-by: Manivannan Sadhasivam
> > ---
> >
This patch fixes some spelling typos in Kconfig.
Signed-off-by: Masanari Iida
---
arch/arm/mach-ixp4xx/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index f7211b57b1e7..c4f719993190 100644
---
If migration happens while L2 entry with an injected event to L2 is pending,
we weren't including the event in the migration state and it would be
lost leading to L2 hang.
Fix this by queueing the injected event in similar manner to how we queue
interrupted injections.
This can be reproduced by
On Wed, Jan 6, 2021 at 6:42 PM Weiyi Lu wrote:
>
> On Wed, 2021-01-06 at 18:25 +0800, Ikjoon Jang wrote:
> > On Tue, Dec 22, 2020 at 9:14 PM Weiyi Lu wrote:
> > >
> > > Add MT8192 basic clock providers, include topckgen, apmixedsys,
> > > infracfg and pericfg.
> > >
> > > Signed-off-by: Weiyi Lu
This is VMX version of the same issue as I reproduced on SVM.
Unlike SVM, this version has 2 pending issues to resolve.
1. This seems to break 'vmx' kvm-unit-test in
'error code <-> (!URG || prot_mode) [+]' case.
The test basically tries to do nested vm entry with unrestricted guest disabled,
Refactor the logic that is dealing with parsing of an injected event to a
separate function.
This will be used in the next patch to deal with the events that L1 wants to
inject to L2 in a way that survives migration.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/vmx/vmx.c | 60
From: Yingjie Wang
In rvu_mbox_handler_cgx_mac_addr_get()
and rvu_mbox_handler_cgx_mac_addr_set(),
the msg is expected only from PFs that are mapped to CGX LMACs.
It should be checked before mapping,
so we add the is_cgx_config_permitted() in the functions.
Fixes: 85482bb ("af/rvu_cgx: Fix
The size parameter is unsigned long type which can accept size > 4GB. In
that case, the upper limit address must be programmed. Add support to
program the upper limit address and set INCREASE_REGION_SIZE in case size >
4GB.
Signed-off-by: Shradha Todi
---
v1: https://lkml.org/lkml/2020/12/20/187
get_features ops of pci_epc_ops may return NULL, causing NULL pointer
dereference in pci_epf_test_bind function. Let us add a check for
pci_epc_feature pointer in pci_epf_test_bind before we access it to avoid
any such NULL pointer dereference and return -ENOTSUPP in case
pci_epc_feature is not
Since outbound iATU permits size to be greater than 4GB for which the
support is also available, allow EP function to send u64 size instead of
truncating to u32.
Signed-off-by: Shradha Todi
---
v1: https://lkml.org/lkml/2020/12/18/690
v2:
Addressed Bjorn's review on to keep commit message
It is possible to exit the nested guest mode, entered by
svm_set_nested_state prior to first vm entry to it (e.g due to pending event)
if the nested run was not pending during the migration.
In this case we must not switch to the nested msr permission bitmap.
Also add a warning to catch similar
The code to store it on the migration exists, but no code was restoring it.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/nested.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86/kvm/svm/nested.c
index 6208d3a5a3fdb..c1a3d0e996add 100644
---
If migration happens while L2 entry with an injected event to L2 is pending,
we weren't including the event in the migration state and it would be
lost leading to L2 hang.
Fix this by queueing the injected event in similar manner to how we queue
interrupted injections.
This can be reproduced by
This should prevent bad things from happening if the user calls the
KVM_SET_NESTED_STATE twice.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/nested.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86/kvm/svm/nested.c
index
We overwrite most of vmcb fields while doing so, so we must
mark it as dirty.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/nested.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86/kvm/svm/nested.c
index 3aa18016832d0..de3dbb5407206 100644
---
Hi!
On Sun, Jan 03, 2021 at 05:06:31AM -0600, Samuel Holland wrote:
> This series adds system (complete power down) and runtime (clock gate)
> PM hooks to the RSB controller driver. Tested on A64 and H6.
>
> Samuel Holland (4):
> bus: sunxi-rsb: Move OF match table
> bus: sunxi-rsb: Split
Refactor the logic that is dealing with parsing of an injected event to a
separate function.
This will be used in the next patch to deal with the events that L1 wants to
inject to L2 in a way that survives migration.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/svm.c | 58
This is a series of fixes to nested SVM, that finally makes my kvm on kvm
stress test pass, and fix various other issues/regressions.
Patches 1-2 are a fix for disappearing interrupts in L2 on migration which
usually make the L2 hang.
Same issue happens on VMX and WIP, patches for this will be
> -Original Message-
> From: Georgi Djakov [mailto:georgi.dja...@linaro.org]
> Sent: Wednesday, January 06, 2021 4:14 PM
> To: HenryC Chen (陳建豪)
> Cc: Rob Herring; Matthias Brugger; Stephen Boyd; Ryan Case; Mark Brown; Mark
> Rutland; Nicolas Boichat; Fan Chen (陳凡); JamesJJ Liao (廖建智);
On Thu, 17 Dec 2020, Lee Jones wrote:
> Start all helpers with "MFD_CELL_".
>
> Cc: Linus Walleij
> Cc: Matthias Brugger
> Cc: Gene Chen
> Cc: linux-media...@lists.infradead.org
> Signed-off-by: Lee Jones
> ---
> drivers/mfd/ab8500-core.c | 42 +++---
>
On Wed, Jan 6, 2021 at 6:47 PM Nicolas Boichat wrote:
>
> On Wed, Jan 6, 2021 at 4:46 PM Hsin-Yi Wang wrote:
> >
> > Config dsi node for mt8183 kukui. Set panel and ports.
> >
> > Signed-off-by: Hsin-Yi Wang
> > ---
> > .../arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 38 +++
> >
On Wed, Jan 6, 2021 at 4:46 PM Hsin-Yi Wang wrote:
>
> Config dsi node for mt8183 kukui. Set panel and ports.
>
> Signed-off-by: Hsin-Yi Wang
> ---
> .../arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 38 +++
> 1 file changed, 38 insertions(+)
>
> diff --git
On Wed, 2021-01-06 at 18:25 +0800, Ikjoon Jang wrote:
> On Tue, Dec 22, 2020 at 9:14 PM Weiyi Lu wrote:
> >
> > Add MT8192 basic clock providers, include topckgen, apmixedsys,
> > infracfg and pericfg.
> >
> > Signed-off-by: Weiyi Lu
> > ---
> > drivers/clk/mediatek/Kconfig |8 +
> >
Hi!
On 1/5/21 4:36 PM, Luck, Tony wrote:
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 0f2e55faaf7f..b74093803154 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -8432,11 +8432,8 @@ F: drivers/i3c/
>> F: include/linux/i3c/
>>
>> IA64 (Itanium) PLATFORM
>> -M: Tony Luck
>> -M:
On Thu, Dec 17, 2020 at 05:31:50PM +, Michael Kelley wrote:
> These Hyper-V changes are problematic as we want to keep hyperv_timer.c
> architecture independent. While only the code for x86/x64 is currently
> accepted upstream, code for ARM64 support is in progress. So we need
> to use
On Wed 06-01-21 20:29:00, Alexey Kardashevskiy wrote:
> This is a workaround to fix a null derefence crash:
>
> [cb01f840] cb01f880 (unreliable)
> [cb01f880] c0769a3c bdev_evict_inode+0x21c/0x370
> [cb01f8c0] c070bacc evict+0x11c/0x230
>
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