1. MAX_NUMNODES is base on CONFIG_NODES_SHIFT, the default value of the
latter is very small now.
2. Suppose the default value of MAX_NUMNODES is enlarged to 64, so the
size of numa_distance is 4K, it's still acceptable if run the Image
on other processors.
3. It will make function __node_
At present, the distances must equal in both direction for each node
pairs. For example: the distance of node B->A must the same to A->B.
But we really don't have to do this.
Signed-off-by: Zhen Lei
---
Documentation/devicetree/bindings/numa.txt | 12
1 file changed, 8 insertions(+)
Hi
On 2016年09月01日 12:20, Doug Anderson wrote:
Hi,
On Wed, Aug 31, 2016 at 7:29 PM, Ziyuan Xu wrote:
This is fine to pick up _only_ if you don't care about suspend/resume.
If you care about suspend/resume then someone needs to first write a
patch that will re-init all "corecfg" values after p
To make each percpu area allocated from its local numa node. Without this
patch, all percpu areas will be allocated from the node which cpu0 belongs
to.
Signed-off-by: Zhen Lei
---
arch/arm64/Kconfig | 8
arch/arm64/mm/numa.c | 52
On Thu, Sep 01, 2016 at 07:47:10AM +1000, Benjamin Herrenschmidt wrote:
> > OK, for giggles, could you (or Balbir) check what happens if you take
> > that sync out?
> The problem is no amount of testing can tell you it works for sure :-)
It breaking does prove the negative though, so still inter
1. Remove the old binding code.
2. Read the nid of cpu0 from dts.
3. Fallback the nid of cpu0 to 0 when numa=off is set in bootargs.
Signed-off-by: Zhen Lei
---
arch/arm64/kernel/smp.c | 1 +
arch/arm64/mm/numa.c| 16 ++--
2 files changed, 11 insertions(+), 6 deletions(-)
diff
This warning has been printed in of_numa_parse_cpu_nodes before.
Signed-off-by: Zhen Lei
Acked-by: Rob Herring
---
drivers/of/of_numa.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/of/of_numa.c b/drivers/of/of_numa.c
index c1bd62c..625b057 100644
--- a/dr
When calling 'snd_pcm_format_physical_width', SNDRV_PCM_FORMAT_LAST is a
valid value, so don't skip it.
Signed-off-by: Christophe JAILLET
---
Un-tested
---
sound/soc/omap/omap-pcm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/omap/omap-pcm.c b/sound/soc/omap/oma
On 01/09/16 07:47, Benjamin Herrenschmidt wrote:
> On Wed, 2016-08-31 at 15:31 +0200, Peter Zijlstra wrote:
>> On Wed, Aug 31, 2016 at 07:28:18AM +1000, Benjamin Herrenschmidt
>> wrote:
>>
>>>
>>> On powerpc we have a sync deep in _switch to achieve that.
>>
>> OK, for giggles, could you (or Balb
On Wed, Aug 31, 2016 at 09:15:30AM -0700, Andi Kleen wrote:
> > >
> > > >
> > > > I've already made some changes in pmu-events/* to support
> > > > this hierarchy to see how bad the change would be.. and
> > > > it's not that bad ;-)
> > >
> > > Everything has to be automated, please no manual c
drivers/net/ethernet/qlogic/qed/qed_dcbx.c:1230:13-20: WARNING: kzalloc should
be used for dcbx_info, instead of kmalloc/memset
drivers/net/ethernet/qlogic/qed/qed_dcbx.c:1192:13-20: WARNING: kzalloc should
be used for dcbx_info, instead of kmalloc/memset
Use kzalloc rather than kmalloc follow
On Thu, Sep 1, 2016 at 2:31 PM, Jorik Jonker wrote:
> Hi,
>
> A bit tricky to reply to two mails in one, as I think my reply relates to
> both, but here it goes.
>
> On 1 September 2016 at 04:42, Chen-Yu Tsai wrote:
>>
>> On Thu, Sep 1, 2016 at 3:30 AM, wrote:
>> > From: Jorik Jonker
>> >
>> >
VM_IOREMAP is used to access hardware through a mechanism called
I/O mapped memory. Android binder is a IPC machanism which will
not access I/O memory.
Also VM_IOREMAP has alignment requiement which may not needed in
binder.
__get_vm_area_node()
{
...
if (flags & VM_IOREMAP)
align
Commit-ID: 3976b0380b315651137ce4321b1171ac0a1d26ed
Gitweb: http://git.kernel.org/tip/3976b0380b315651137ce4321b1171ac0a1d26ed
Author: Andy Shevchenko
AuthorDate: Wed, 31 Aug 2016 16:57:13 +0300
Committer: Ingo Molnar
CommitDate: Thu, 1 Sep 2016 08:22:42 +0200
x86/platform/intel-mid: E
Commit-ID: dd8d6ec672f9796528a31033084a4947817d6316
Gitweb: http://git.kernel.org/tip/dd8d6ec672f9796528a31033084a4947817d6316
Author: Andy Shevchenko
AuthorDate: Wed, 31 Aug 2016 16:57:12 +0300
Committer: Ingo Molnar
CommitDate: Thu, 1 Sep 2016 08:22:42 +0200
x86/platform/intel-mid: E
On Thu, 2016-09-01 at 06:11 +0200, Mike Galbraith wrote:
> I don't see a great alternative to turning it off off the top of my
> head, at least for processors with multiple LLCs.
Here of course I mean other than saying it's just not worth worrying
about such old processors, iff it's only old dogs
Hi,
(trying again in plaintext, sorry for the HTML spam...)
A bit tricky to reply to two mails in one, as I think my reply relates
to both, but here it goes.
On 1 September 2016 at 04:42, Chen-Yu Tsai wrote:
> On Thu, Sep 1, 2016 at 3:30 AM, wrote:
>> From: Jorik Jonker
>>
>> This enables th
>>> Mark D Rustad schrieb am 31.08.2016 um 17:32 in
>>> Nachricht
:
> Ulrich Windl wrote:
>
>> So without partition the throughput is about twice as high! Why?
>
> My first thought is that by starting at block 0 the accesses were aligned
> with the flash block size of the device. By starting
On Thu, Sep 01, 2016 at 06:01:35AM +, Nava kishore Manne wrote:
> Ping!!
ping what?
I don't see a patch here, and nothing is in my to-review queue about
this.
Perhaps send it again?
confused,
greg k-h
Op 31-08-16 om 21:07 schreef Gustavo Padovan:
> From: Gustavo Padovan
>
> There is now a new property called FENCE_FD attached to every plane
> state that receives the sync_file fd from userspace via the atomic commit
> IOCTL.
>
> The fd is then translated to a fence (that may be a fence_collectio
On Tue, Aug 23, 2016 at 03:16:10PM -0700, York Sun wrote:
> Replace obsolete simple_strtoul() with kstrtoul().
>
> Signed-off-by: York Sun
> ---
> drivers/edac/fsl_ddr_edac.c | 30 --
> 1 file changed, 24 insertions(+), 6 deletions(-)
Applied, thanks.
--
Regards/Gr
* Dmitry Safonov wrote:
> Changes from v3:
> - proper ifdefs around vdso_image_32
> - missed Reviewed-by tag
> arch/x86/entry/vdso/vma.c | 81
> +++
> arch/x86/ia32/ia32_signal.c | 2 +-
> arch/x86/include/asm/compat.h | 8 ++--
> arch/x
On Wed, Aug 31, 2016 at 04:23:52PM +0100, Liviu Dudau wrote:
> On Wed, Aug 31, 2016 at 03:07:49PM +0200, Greg Kroah-Hartman wrote:
> > On Fri, Aug 05, 2016 at 01:11:45PM +0200, Nicolai Stange wrote:
> > > Brian Starkey writes:
> > >
> > > > On Tue, Aug 02, 2016 at 07:31:36PM +0200, Nicolai Stange
Hi Stephen,
On Thu, Sep 1, 2016 at 6:10 AM, Stephen Boyd wrote:
> The HSIC USB controller on qcom SoCs has an integrated all
> digital phy controlled via the ULPI viewport.
>
> Cc: Kishon Vijay Abraham I
> Cc:
> Signed-off-by: Stephen Boyd
> ---
> .../devicetree/bindings/phy/qcom,usb-hsic-ph
We get a few warnings when building kernel with W=1:
drivers/isdn/hardware/mISDN/hfcmulti.c:568:1: warning: no previous declaration
for 'enablepcibridge' [-Wmissing-declarations]
drivers/isdn/hardware/mISDN/hfcmulti.c:574:1: warning: no previous declaration
for 'disablepcibridge' [-Wmissing-decla
On Wed, Aug 31, 2016 at 7:36 PM, Dan Williams wrote:
> On Wed, Aug 31, 2016 at 7:57 AM, Matthew Wilcox
> wrote:
>> I'm not at all against the idea of having a tree which supports ranges,
>> except that we already have one; the interval tree. Did you investigate
>> using the interval tree for
On Tue, Aug 23, 2016 at 03:14:03PM -0700, York Sun wrote:
> Add DDR EDAC for ARM-based compatible controllers. Both big-endian
> and little-endian are supported, as specified in device tree.
>
> Signed-off-by: York Sun
>
> ---
> Change log
> v5: Update author and copyright for the new driver
>
The KMS helpers (drm_atomic_helper_check_modeset/mode_fixup) pass
encoder->bridge directly to drm_bridge_mode_fixup, which expects a
valid pointer, or NULL (in which case it just returns).
Clear encoder->bridge if a bridge is not found, instead of keeping
the ERR_PTR value.
Since other drm_bridge
On Wed, Aug 31, 2016 at 1:53 AM, Ross Zwisler
wrote:
> On Tue, Aug 30, 2016 at 03:21:24PM -0700, Dan Williams wrote:
>> On Tue, Aug 30, 2016 at 3:03 PM, Ross Zwisler
>> wrote:
>> > On Tue, Aug 30, 2016 at 02:56:17PM -0700, Dan Williams wrote:
>> >> On Mon, Aug 29, 2016 at 11:52 AM, Matthew Wilcox
On Thu, Sep 01, 2016 at 11:17:23AM +0530, Aneesh Kumar K.V wrote:
> Joonsoo Kim writes:
>
> > On Tue, Aug 30, 2016 at 04:09:37PM +0530, Aneesh Kumar K.V wrote:
> >> Joonsoo Kim writes:
> >>
> >> > 2016-08-29 18:27 GMT+09:00 Aneesh Kumar K.V
> >> > :
> >> >> js1...@gmail.com writes:
> >> >>
> >
Hi Shunqian,
On 2016年09月01日 07:06, Shunqian Zheng wrote:
We would prefer the 2016M as 2.0G than 1992M which seems odd, adding
it to big cpu clk rate table then we can set 2016M in dts.
Signed-off-by: Shunqian Zheng
---
drivers/clk/rockchip/clk-rk3399.c | 1 +
1 file changed, 1 insertion(+)
2016-09-01 13:46 GMT+08:00 Li, Liang Z :
>> Subject: Re: [PATCH v3 kernel 0/7] Extend virtio-balloon for fast
>> (de)inflating
>> & fast live migration
>>
>> 2016-08-08 14:35 GMT+08:00 Liang Li :
>> > This patch set contains two parts of changes to the virtio-balloon.
>> >
>> > One is the change f
Joonsoo Kim writes:
> On Tue, Aug 30, 2016 at 04:09:37PM +0530, Aneesh Kumar K.V wrote:
>> Joonsoo Kim writes:
>>
>> > 2016-08-29 18:27 GMT+09:00 Aneesh Kumar K.V
>> > :
>> >> js1...@gmail.com writes:
>> >>
>> >>> From: Joonsoo Kim
>> >>>
>> >>> Hello,
>> >>>
>> >>> Changes from v4
>> >>> o R
> Subject: Re: [PATCH v3 kernel 0/7] Extend virtio-balloon for fast
> (de)inflating
> & fast live migration
>
> 2016-08-08 14:35 GMT+08:00 Liang Li :
> > This patch set contains two parts of changes to the virtio-balloon.
> >
> > One is the change for speeding up the inflating & deflating process
You are a recipient to Mrs Julie Leach Donation of $3 million USD. Contact
(julieleac...@gmail.com) for claims.
On 31 August 2016 at 21:00, Rafał Miłecki wrote:
> On 31 August 2016 at 20:23, Alan Stern wrote:
>> On Tue, 30 Aug 2016, Rafał Miłecki wrote:
>>> Not really as it won't cover some pretty common use cases. Many home
>>> routers have few USB ports (2-5) and only 1 USB LED. It has to be
>>> possible
> Hi Bharat,
> > @@ -561,7 +561,7 @@ static int nwl_pcie_init_irq_domain(struct
> > nwl_pcie
> *pcie)
> > }
> >
> > pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node,
> > - INTX_NUM,
> > +
On Wed, Aug 31, 2016 at 01:38:35PM -0700, Andrey Vagin wrote:
> On Tue, Aug 30, 2016 at 7:56 PM, Serge E. Hallyn wrote:
> > On Fri, Aug 26, 2016 at 04:08:08PM -0700, Andrei Vagin wrote:
> >> +struct ns_common *ns_get_owner(struct ns_common *ns)
> >> +{
> >> + struct user_namespace *my_user_ns
On Wednesday 31 August 2016 07:38 PM, Heiko Stübner wrote:
> Hi,
>
> Am Samstag, 20. August 2016, 10:53:37 schrieb Shawn Lin:
>> This patch to add a generic PHY driver for rockchip PCIe PHY.
>> Access the PHY via registers provided by GRF (general register
>> files) module.
>>
>> Signed-off-by:
Hi Catalin, Will,
On Thu, Sep 01, 2016 at 12:51:09PM +0800, Leo Yan wrote:
> Enable common modules for power management; one is to enable
> CPUFREQ_DT driver; the driver is used by many platforms by passing OPP
> table from device tree.
>
> Also enables thermal related drivers. Firstly we need en
Enable common modules for power management; one is to enable
CPUFREQ_DT driver; the driver is used by many platforms by passing OPP
table from device tree.
Also enables thermal related drivers. Firstly we need enable
configuration CPU_THERMAL for CPU cooling device driver, this will bind
thermal z
2016-08-08 14:35 GMT+08:00 Liang Li :
> This patch set contains two parts of changes to the virtio-balloon.
>
> One is the change for speeding up the inflating & deflating process,
> the main idea of this optimization is to use bitmap to send the page
> information to host instead of the PFNs, to r
Hi,
On Wed, Aug 31, 2016 at 7:29 PM, Ziyuan Xu wrote:
>> This is fine to pick up _only_ if you don't care about suspend/resume.
>> If you care about suspend/resume then someone needs to first write a
>> patch that will re-init all "corecfg" values after power is turned on.
>
>
> Do you mean corec
On 08/31/2016 08:39 PM, Shawn Lin wrote:
Hi Guenter,
Thanks for your review, and I think it still not too late
for nitpicking as it isn't merged to next branch. :)
We have amend the code a bit, so probably we fixed some of
the minor issues against V10. But some of them are really
personal taste
On Wed, 2016-08-31 at 17:52 +0200, Vincent Guittot wrote:
> On 31 August 2016 at 12:36, Mike Galbraith wrote:
> > On Wed, 2016-08-31 at 12:18 +0200, Mike Galbraith wrote:
> > > On Wed, 2016-08-31 at 12:01 +0200, Peter Zijlstra wrote:
> >
> > > > So 43f4d66637bc ("sched: Improve sysbench performan
From: robert.f...@collabora.com
Date: Mon, 29 Aug 2016 09:32:14 -0400
> This is a resubmission of v3, since the netdev
> mailinlist was not sent the previous submission.
>
> This series improves power management of the asix driver.
...
Series applied, thanks.
Three different patches all with the same Subject line, so I can't
apply this stuff.
You must make the subject lines unique so that someone reading
the "git shortlog" can tell what is different in each change.
From: James Pettigrew
The NanoPi NEO is a minimal H3 based SBC. It comes with 256/512M RAM, a
micro SD slot, 10/100Mbit ethernet and a single USB-A port.
Signed-off-by: James Pettigrew
---
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 126 ++
On 08/31/2016 05:32 PM, Omar Sandoval wrote:
On Wed, Aug 31, 2016 at 11:05:45AM -0600, Jens Axboe wrote:
Add wbc_to_write_flags(), which returns the write modifier flags to use,
based on a struct writeback_control. No functional changes in this
patch, but it prepares us for factoring other wbc f
Few commits and patch changed according to Greg's comments.
Regards
Alex
>From 186c534b0b8b9649fbfce05b0b4f90f764c571a4 Mon Sep 17 00:00:00 2001
From: Alex Shi
Date: Tue, 16 Aug 2016 15:29:01 +0800
Subject: [PATCH 2/4] cpu: expose pm_qos_resume_latency for each cpu
Adding /sys/devices/sy
From: Julia Lawall
Date: Thu, 1 Sep 2016 00:21:23 +0200
> Check for ethtool_ops structures that are only stored in the ethtool_ops
> field of a net_device structure or passed as the second argument to
> netdev_set_default_ethtool_ops. These contexts are declared const, so
> ethtool_ops structur
From: Julia Lawall
Date: Thu, 1 Sep 2016 00:21:19 +0200
> Check for ethtool_ops structures that are only stored in the ethtool_ops
> field of a net_device structure or passed as the second argument to
> netdev_set_default_ethtool_ops. These contexts are declared const, so
> ethtool_ops structur
From: Julia Lawall
Date: Thu, 1 Sep 2016 00:21:22 +0200
> Check for ethtool_ops structures that are only stored in the ethtool_ops
> field of a net_device structure or passed as the second argument to
> netdev_set_default_ethtool_ops. These contexts are declared const, so
> ethtool_ops structur
On 09/01/2016 11:39 AM, Alex Shi wrote:
> User can set values on each of cpu, like limit 100ms on cpu0, that means
> the cpu0 response time should be in 100ms in possible idle. It similar
> with DMA_LATENCY, but that request is for all cpu. This is just for
> particular cpu, like a interrupt pine
On Tuesday 30 August 2016 09:41 PM, Nilay Vaish wrote:
On 28 August 2016 at 16:00, Madhavan Srinivasan
wrote:
diff --git a/kernel/events/core.c b/kernel/events/core.c
index 274288819829..e16bf4d057d1 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -5371,16 +5371,24 @@ u64 __at
Fintek F81866 is a LPC to 6 UARTs SuperIO. It has fully functional UARTs
likes F81216H. It's also need check the IRQ mode with system assigned,
but the configuration is not the same with F81216 series.
F81866 IRQ Mode setting:
0xf0
Bit1: IRQ_MODE0
Bit0: Shar
Fintek F81865 is a LPC to 6 UARTs SuperIO. It has less functional UARTs
likes F81866. It's also need check the IRQ mode with system assigned,
but the configuration is not the same with F81216 series.
F81865 IRQ Mode setting:
0xf0
Bit1: IRQ_MODE0
Bit0: Share mode (always
If we need to access SuperIO registers, It should write register offset
to base_addr and read/write value to base_addr + 1 to perform read/write.
We can make it more simply with write/read functions.
This patch add sio_read_reg()/sio_write_reg()/sio_write_mask_reg() to
reduce SuperIO register oper
Set IRQ Mode when port probed in find_base_port()
It should hold the IO port premission via fintek_8250_enter_key() and
release via fintek_8250_exit_key() when we configure the SuperIO.
This patch will move all SuperIO configure operations to find_base_port()
to reduce fintek_8250_enter_key()/fin
We change the position of fintek_8250_set_irq_mode() above the
find_base_port() to eliminate the prototype define.
Signed-off-by: Ji-Ze Hong (Peter Hong)
---
drivers/tty/serial/8250/8250_fintek.c | 19 ---
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/drivers/tty
Fintek F81216 is a LPC to 4 UARTs device. It's the F81216 series but
support less functional than F81216AD/F81216H
The following list is brief descriptions of F81216 series:
F81216H (0105)
9Bit/High baud rate(not implements with mainline)
RS485, 128Bytes FIFO (implemented)
F81216
Hi Guenter,
Thanks for your review, and I think it still not too late
for nitpicking as it isn't merged to next branch. :)
We have amend the code a bit, so probably we fixed some of
the minor issues against V10. But some of them are really
personal taste, if you still insist on that, I will be o
The Fintek F81216H had maximum 128Bytes FIFO, but some BIOS configurated
as normal 16Bytes FIFO. This patch will set 128Bytes FIFO and trigger
level multiplier as 4x when F81216H detected.
Default 16550A trigger level is 8Bytes. When this patch applied, the
trigger level will change to 8Byte x 4 =
The following patches will fix the Fintek LPC to UARTs IRQ mode mismatch
issue, code refactoring and this series patches should follow by patch
rename IRQ_MODE macro on
'commit 87a713c8ffca ("8250/fintek: rename IRQ_MODE macro")'.
with tty-linus branch.
Some BIOS only use _OSI("Linux") to distingu
>> @@ -376,6 +377,8 @@ int register_cpu(struct cpu *cpu, int num)
>>
>> per_cpu(cpu_sys_devices, num) = &cpu->dev;
>> register_cpu_under_node(num, cpu_to_node(num));
>> +if (dev_pm_qos_expose_latency_limit(&cpu->dev, 0))
>> +pr_debug("CPU%d: add resume latency failed\n"
在 2016/9/1 6:56, Rafael J. Wysocki 写道:
On Wednesday, August 31, 2016 07:48:14 PM Dongdong Liu wrote:
Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_acpi_init() to get RC config resource
with hardcoded range address and setup ecam mapping.
在 2016/9/1 10:29, Ziyuan Xu 写道:
Hi,
On 2016年09月01日 01:42, Doug Anderson wrote:
Hi,
On Sun, Aug 28, 2016 at 8:25 PM, Shawn Lin
wrote:
On 2016/8/29 10:50, Elaine Zhang wrote:
On 08/27/2016 11:05 PM, Shawn Lin wrote:
On 2016/8/27 21:41, Ziyuan Xu wrote:
Control power domain for eMMC via g
On Tuesday 30 August 2016 09:31 PM, Nilay Vaish wrote:
On 28 August 2016 at 16:00, Madhavan Srinivasan
wrote:
Patchset to extend PERF_SAMPLE_REGS_INTR to include
platform specific PMU registers.
Patchset applies cleanly on tip:perf/core branch
It's a perennial request from hardware folks to
Hello
This is very surprising,
Bike, brand, guitar, camera, TV, telephone 50% discount and free shipping
www .slooone .com
On Thu, Sep 1, 2016 at 3:30 AM, wrote:
> From: Jorik Jonker
>
> This adds proper pinmux definitions for i2c0 and i2c1. Although H3 has a third
> i2c controller, these are not exposed on my boards. If someone actually has a
> H3 board with an exposed i2c2, they could add the third.
>
> Signed-off
It missed to handle TRACE_BPUTS so messages recorded by trace_bputs()
will be shown with symbol info unnecessarily.
You can see it with the trace_printk sample code:
# cd /sys/kernel/tracing/
# echo sys_sync > set_graph_function
# echo 1 > options/sym-offset
# echo function_graph > curren
On Thu, Sep 1, 2016 at 3:30 AM, wrote:
> From: Jorik Jonker
>
> This enables the i2c0/i2c1 peripherals of the SoC. There is actually a third
> controller, but I do not have a board on hands on which i2c2 is exposed in
> such
> a way that I can verify that it works.
If they are listed in the ma
Hi Dave,
On Wed, 31 Aug 2016 16:52:22 -0400
David Long wrote:
> From: "David A. Long"
>
> Kprobes searches backwards a finite number of instructions to determine if
> there is an attempt to probe a load/store exclusive sequence. It stops when
> it hits the maximum number of instructions or a l
Hi,
On 2016年09月01日 01:42, Doug Anderson wrote:
Hi,
On Sun, Aug 28, 2016 at 8:25 PM, Shawn Lin wrote:
On 2016/8/29 10:50, Elaine Zhang wrote:
On 08/27/2016 11:05 PM, Shawn Lin wrote:
On 2016/8/27 21:41, Ziyuan Xu wrote:
Control power domain for eMMC via genpd to reduce power consumption.
Use an unified new dev variable instead of &pdev->dev and p->dev
in probe function.
Reviewed-by: Heikki Krogerus
Signed-off-by: Kefeng Wang
---
Hi Greg, updated, based on tty-testing branch :)
v1->v2:
1) Add Heikki's reviewed-by
2) Rebase on tty-testing branch of
git://git.kernel.org/pub/scm/
Sorry, please ignore, send wrong patch.
On 2016/9/1 9:34, Kefeng Wang wrote:
> Use an unified new dev variable instead of &pdev->dev and p->dev
> in probe function.
>
> Signed-off-by: Kefeng Wang
> ---
> drivers/tty/serial/8250/8250_dw.c | 45
> ---
> 1 file
Will Deacon writes:
> On Sat, Aug 27, 2016 at 04:19:50PM +, Stefan Wahren wrote:
>> Patch 7f1d642fbb5c ("drivers/perf: arm-pmu: Fix handling of SPI lacking
>> interrupt-affinity property") unintended also fixes perf_event support
>> for bcm2835 which doesn't have PMU interrupts. Unfortunately
在 2016/8/31 19:48, Arnd Bergmann 写道:
On Wednesday, August 31, 2016 7:48:14 PM CEST Dongdong Liu wrote:
+static struct hisi_rc_res rc_res[] = {
+ {
+ HIP05,
+ {
+ DEFINE_RES_MEM(0xb007, SZ_4K),
+ DEFINE_RES_MEM(0x
Hi Doug,
Last replied email HTML HEAD error, resend it.
在 2016/8/30 5:22, Douglas Anderson 写道:
Depending on a number of factors including:
- Which exact Rockchip SoC we're working with
- How deep we suspend
- Which i2c port we're on
We might lose the state of the i2c registers at suspend time.
On 8/31/16 13:57, Aaro Koskinen wrote:
> This series implements multiple RX group support that should improve
> the networking performance on multi-core OCTEONs. Basically we register
> IRQ and NAPI for each group, and ask the HW to select the group for
> the incoming packets based on hash.
>
> Te
在 2016/8/31 19:45, Arnd Bergmann 写道:
On Wednesday, August 31, 2016 7:48:12 PM CEST Dongdong Liu wrote:
+
+/* HipXX PCIe host only supports 32-bit config access */
+int hisi_pcie_common_cfg_read(void __iomem *reg_base, int where, int size,
+ u32 *val)
+{
+ u32 r
> After a code cleanup, we get a harmless warning about a variable
> that is unused when CONFIG_FS_POSIX_ACL is disabled:
>
> drivers/staging/lustre/lustre/llite/xattr.c: In function
> 'll_xattr_get_common':
> drivers/staging/lustre/lustre/llite/xattr.c:312:24: error: unused variable
> 'lli' [-
> A patch to change to page accounting code (in v4.8-rc1) conflicts with
> a change to lustre (in staging-next for v4.9), and fortunately gets
> detected using a gcc warning:
>
> In file included from /git/arm-soc/include/linux/mm.h:1001:0,
> from /git/arm-soc/include/linux/highm
Hi, Mimi
On 08/30/16 at 06:40pm, Mimi Zohar wrote:
> From: Thiago Jung Bauermann
>
> This patch uses the kexec buffer passing mechanism to pass the
> serialized IMA binary_runtime_measurements to the next kernel.
>
> Changelog v2:
> - Fix build issue by defining a stub ima_add_kexec_buffer and
On Wed, Aug 31, 2016 at 05:28:26PM -0700, David Rientjes wrote:
2. store_mem_state() still needs a tweak, right? It was only
returning -EINVAL by accident, due to the convoluted sequence I
listed in the patch.
Yes, absolutely. It returning -EINVAL for "nline" is what is accidently
preserving
This driver is for Fintek F81532/F81534 USB to Serial Ports IC.
F81532 spec:
https://drive.google.com/file/d/0B8vRwwYO7aMFOTRRMmhWQVNvajQ/view?usp=
sharing
F81534 spec:
https://drive.google.com/file/d/0B8vRwwYO7aMFV29pQWJqbVBNc00/view?usp=
sharing
Features:
1. F81532 is 1-to-2 & F81534 is 1-to-4
On 8/31/16 14:20, Aaro Koskinen wrote:
> On Wed, Aug 31, 2016 at 09:20:07AM -0700, Ed Swierk wrote:
>> Here's my workaround:
>
> [...]
>
>> -static int cvm_oct_poll(struct oct_rx_group *rx_group, int budget)
>> +static int cvm_oct_poll(int group, int budget)
>> {
>> const int coreid =
On 31/08/16 17:28, Peter Zijlstra wrote:
> On Wed, Aug 31, 2016 at 01:41:33PM +1000, Balbir Singh wrote:
>> On 30/08/16 22:19, Peter Zijlstra wrote:
>>> On Tue, Aug 30, 2016 at 06:49:37PM +1000, Balbir Singh wrote:
The origin of the issue I've seen seems to be related to
rwsem s
Use an unified new dev variable instead of &pdev->dev and p->dev
in probe function.
Signed-off-by: Kefeng Wang
---
drivers/tty/serial/8250/8250_dw.c | 45 ---
1 file changed, 23 insertions(+), 22 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_dw.c
b/
You are a recipient to Mrs Julie Leach Donation of $3 million USD. Contact (
julieleach...@outlook.com ) for claims.
Somewhere along the way the autofs expire operation has changed to
hold a spin lock over expired dentry selection. The autofs indirect
mount expired dentry selection is complicated and quite lengthy so
it isn't appropriate to hold a spin lock over the operation.
Commit 47be6184 added a might_sleep
Hi all,
I received a question regarding back-porting the support for the G29
racing wheel to 3.10 (Android in particular), and after some collaborative
work we determined that changes between 3.10 and 4.7 are actually pretty
minimal and self contained.
After copying the HEAD 'hid-lg.[ch]' and 'hid
On Fri, Aug 26, 2016 at 9:47 AM, Ley Foon Tan wrote:
> Altera PCIe IP can be configured as rootport or device and they might have
> same vendor ID. It will cause the system hang issue if Altera PCIe is in
> endpoint mode and work with other PCIe rootport that from other vendors.
>
> This series of
This fixes pointer panic when using inline_dentry, which was triggered when
backporting to 3.10.
Signed-off-by: Jaegeuk Kim
---
fs/f2fs/dir.c| 2 +-
fs/f2fs/inline.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/fs/f2fs/dir.c b/fs/f2fs/dir.c
index 9316d8a..2fb20fc 10
On 08/31/16 09:19, Joe Perches wrote:
> Convert it to the preferred const struct pci_device_id instead.
Reviewed-by: Bart Van Assche
On (08/31/16 13:15), Andrew Morton wrote:
> > On (08/30/16 15:03), Andrew Morton wrote:
> > > > __printk_nmi_flush() can be called from nmi_panic(), therefore it has to
> > > > test whether it's executed in NMI context and thus must route the
> > > > messages
> > > > through deferred printk() or v
On Wed, Aug 31, 2016 at 3:53 PM, Srinivas Pandruvada
wrote:
> On Wed, 2016-08-31 at 13:43 -0700, Matt Ranostay wrote:
>> On Wed, Aug 31, 2016 at 1:29 PM, Pandruvada, Srinivas
>> wrote:
>> >
>> > On Wed, 2016-08-31 at 13:24 -0700, Matt Ranostay wrote:
>> > >
>> > > On Wed, Aug 31, 2016 at 1:18 PM,
The ULPI bus can be built as a module, and it will soon be
calling these functions when it supports probing devices from DT.
Export them so they can be used by the ULPI module.
Cc: Rob Herring
Cc:
---
drivers/of/device.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/of/device.c
The core framework already handles setting this parameter with a
platform quirk. Add the appropriate flag so that we always set
AHBBURST to 0. Technically DT should be doing this, but we always
do it for msm chipidea devices so setting the flag in the driver
works just as well. If the burst needs t
In the case of ULPI devices, we want to be able to load the
driver before registering the device so that we don't get stuck
in a loop waiting for the phy module to appear and failing usb
controller probe. Currently we request the ulpi module via the
ulpi ids, but in the DT case we might need to req
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