We already have the DEFINE_SHOW_ATTRIBUTE. There is no need to define
such a macro, so remove DEFINE_SIMPLE_DEBUGFS_FILE. Also use the
DEFINE_SHOW_ATTRIBUTE macro to simplify some code.
Signed-off-by: Yangtao Li
---
.../ethernet/chelsio/cxgb4/cxgb4_debugfs.c| 113 --
On 12/14/18 22:41, Thomas Schöbel-Theuer wrote:
On 12/14/18 22:24, Andy Lutomirski wrote:
I'm talking about x32, which is a different beast.
So from my viewpoint the mentioned roadmap / timing requirements will
remain the same, whatever you are dropping.
Enterprise-critical use cases
Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code.
Signed-off-by: Yangtao Li
---
net/6lowpan/debugfs.c | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/net/6lowpan/debugfs.c b/net/6lowpan/debugfs.c
index 24915e0bb9ea..6c152f9ea26e 100644
---
Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code.
Signed-off-by: Yangtao Li
---
net/ipv4/ipconfig.c | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/net/ipv4/ipconfig.c b/net/ipv4/ipconfig.c
index 88212615bf4c..fcb817d0eb24 100644
--- a/net/ipv4/ipconfig.c
Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code.
Signed-off-by: Yangtao Li
---
net/sunrpc/rpc_pipe.c | 19 +++
net/sunrpc/stats.c| 14 +-
2 files changed, 4 insertions(+), 29 deletions(-)
diff --git a/net/sunrpc/rpc_pipe.c b/net/sunrpc/rpc_pipe.c
index
On 21/10/18 12:10 pm, Andrew Donnellan wrote:
The linux.conf.au Kernel Miniconf is happening once again, this time in
Christchurch on 22 Jan 2019.
*** Submissions close on 2018-12-16, 23:59 AoE, with early submissions
(before 2018-11-16, 23:59 AoE) given priority. ***
This deadline is in
Hi Tom and Masami,
On Sat, Dec 15, 2018 at 2:29 AM Tom Zanussi wrote:
>
> Hi Masami,
>
> On Sat, 2018-12-15 at 01:31 +0900, Masami Hiramatsu wrote:
> > On Mon, 10 Dec 2018 18:01:34 -0600
> > Tom Zanussi wrote:
> >
> > > From: Tom Zanussi
> > >
> > > Since every var ref for a trigger has an
On Wed, Dec 12, 2018 at 04:52:58PM +0100, Daniel Lezcano wrote:
> On 12/12/2018 16:47, Manivannan Sadhasivam wrote:
> > Hi Daniel,
> >
> > On Wed, Dec 12, 2018 at 04:07:53PM +0100, Daniel Lezcano wrote:
> >> On 10/12/2018 18:35, Manivannan Sadhasivam wrote:
> >>> Add clock driver for RDA Micro
On Fri, Dec 14, 2018 at 12:38 PM Bjorn Helgaas wrote:
>
> [+cc Trent]
>
> On Thu, Dec 06, 2018 at 12:15:50PM +, Lorenzo Pieralisi wrote:
> > On Wed, Dec 05, 2018 at 11:35:42PM -0800, Andrey Smirnov wrote:
> > > Everyone:
> > >
> > > This series contains changes I made in order to enable
On Fri, Dec 14, 2018 at 12:30 PM Bjorn Helgaas wrote:
>
> [+cc Gustavo for fallthrough annotation]
>
> On Wed, Dec 05, 2018 at 11:35:45PM -0800, Andrey Smirnov wrote:
> > Add code needed to support i.MX8MQ variant.
>
> > @@ -245,7 +253,8 @@ static void imx6_pcie_reset_phy(struct imx6_pcie
> >
Add compatible strings for the SiFive E51 family of CPU cores to the
RISC-V CPU compatible string documentation. The E51 CPU core is
described in:
https://static.dev.sifive.com/FU540-C000-v1.0.pdf
Cc: Rob Herring
Cc: Mark Rutland
Cc: Palmer Dabbelt
Cc: Albert Ou
Cc:
Add DT binding documentation for the SiFive FU540 SoC. This
SoC is documented at:
https://static.dev.sifive.com/FU540-C000-v1.0.pdf
This file is originally based on
Documentation/devicetree/bindings/arm/ti/k3.txt.
Cc: Rob Herring
Cc: Mark Rutland
Cc: Palmer Dabbelt
Cc: Albert Ou
Cc:
Add initial support for the SiFive FU540-C000 SoC. This is a 28nm SoC
based around the SiFive U54-MC core complex and a TileLink
interconnect.
This file is expected to grow considerably as more device drivers are
added to the kernel.
Cc: Rob Herring
Cc: Mark Rutland
Cc: Palmer Dabbelt
Cc:
Add DT binding documentation for boards based on the SiFive FU540 SoC.
The first board, the HiFive Unleashed A00 (FU540), is described here:
https://static.dev.sifive.com/HiFive-Unleashed-Getting-Started-Guide-v1p1.pdf
Cc: Rob Herring
Cc: Mark Rutland
Cc: Palmer Dabbelt
Cc: Albert Ou
Cc:
Add support for building flattened DT files from DT source files under
arch/riscv/boot/dts. Follow existing kernel precedent from other SoC
architectures.
Start by adding initial support for the SiFive FU540 SoC, and the
development board that uses it, the SiFive HiFive Unleashed A00.
Applies
Add initial board data for the SiFive HiFive Unleashed A00.
Currently the data populated in this DT file describes the board
DRAM configuration and the external clock sources that supply the
PRCI.
Cc: Rob Herring
Cc: Mark Rutland
Cc: Palmer Dabbelt
Cc: Albert Ou
Cc:
Similar to what's implemented for ARM64, add support for building
DTB files from DT source data for RISC-V boards.
This patch starts with the infrastructure needed for SiFive boards.
Cc: Palmer Dabbelt
Cc: Albert Ou
Signed-off-by: Paul Walmsley
Signed-off-by: Paul Walmsley
---
Add compatible strings for the SiFive U54 family of CPU cores to the
RISC-V CPU compatible string documentation. The U54 CPU cores are
described in:
https://static.dev.sifive.com/FU540-C000-v1.0.pdf
Cc: Rob Herring
Cc: Mark Rutland
Cc: Palmer Dabbelt
Cc: Albert Ou
Cc:
Andy Lutomirski dixit:
>x32 is not this at all. The kernel ABI part of x32 isn't ILP32. It's
>IP32, 32-bit size_t, and *64-bit* long. The core kernel doesn't
Yeah, I was looking at this from userspace PoV, as I said I’m not
a Linux kernel programmer.
In BSD we have register_t which is
The latest maintenance release Git v2.20.1 is now available at
the usual places.
The tarballs are found at:
https://www.kernel.org/pub/software/scm/git/
The following public repositories all have a copy of the 'v2.20.1'
tag and the 'maint' branch that the tag points at:
url =
On 2018/12/14 13:56, zhangjun wrote:
> IOMAP uses PG_private a little different with buffer_head based
> filesystem.
> It uses it as marker and when set, the page counter is not incremented,
> migrate_page_move_mapping() assumes that PG_private indicates a counter
> of +1.
> so, we have to pass
Changeset 9b6f7e163cd0 ("mm: rework memcg kernel stack accounting")
will result in fork failing if allocating a kernel stack for a task
in dup_task_struct exceeds the kernel memory allowance for that cgroup.
Unfortunately, it also results in a crash.
This is due to the code jumping to free_stack
On Fri, 15 Jun 2018 21:01:53 +
Bart Van Assche wrote:
> Hello Steven,
Sorry about the 6 month old reply. I just noticed this email buried in
my INBOX (I triage my INBOX to find emails like this that got missed).
And yes I missed your reply as well :-/
>
> If I run the following commands
Reviewed-by: Sagi Grimberg
From: Yonglong Liu
There will be a large number of MAC pause frames on the net,
which caused tx timeout of net device. And then the net device
was reset to try to recover it. So that is not useful, and will
cause some other problems.
So need doubled ndev->watchdog_timeo if device watchdog
From: Yonglong Liu
1.In "hns_nic_init_irq", if request irq fail at index i,
the function return directly without releasing irq resources
that already requested.
2.In "hns_nic_net_up" after "hns_nic_init_irq",
if exceptional branch occurs, irqs that already requested
are not release.
From: Yonglong Liu
There are two test cases:
1. Remove the 4 modules:hns_enet_drv/hns_dsaf/hnae/hns_mdio,
and install them again, must use "ifconfig down/ifconfig up"
command pair to bring port to work.
This patch calls phy_stop function when init phy to fix this bug.
2. Remove the 2
From: Yonglong Liu
If there are packets in hardware when changing the speed or duplex,
it may cause hardware hang up.
This patch adds the code to wait rx fbd clean up when ae stopped.
Signed-off-by: Yonglong Liu
Signed-off-by: Peng Li
---
drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c |
From: Yonglong Liu
The ntuple-filters features is forced on by chip.
But it shows "ntuple-filters: off [fixed]" when use ethtool.
This patch make it correct with "ntuple-filters: on [fixed]".
Signed-off-by: Yonglong Liu
Signed-off-by: Peng Li
---
drivers/net/ethernet/hisilicon/hns/hns_enet.c
From: Yonglong Liu
In some case, when mac enable|disable and adjust link, may cause hard to
link(or abnormal) between mac and phy. This patch adds the code for rx PCS
to avoid this bug.
Disable the rx PCS when driver disable the gmac, and enable the rx PCS
when driver enable the mac.
This patchset introduces some code improvements and fixes
for the identified problems in the HNS driver.
Every patch is independent.
Yonglong Liu (10):
net: hns: Incorrect offset address used for some registers.
net: hns: All ports can not work when insmod hns ko after rmmod.
net: hns:
From: Yonglong Liu
After resetting dsaf to try to repair chip error such as ecc error,
the net device will be open if net interface is up. But at this time
if there is the users set the net device up with the command ifconfig,
the net device will be opened twice consecutively.
Function
From: Yonglong Liu
According to the hip06 Datasheet:
1. The offset of INGRESS_SW_VLAN_TAG_DISC should be 0x1A00+4*all_chn_num
2. The offset of INGRESS_IN_DATA_STP_DISC should be 0x1A50+4*all_chn_num
Signed-off-by: Yonglong Liu
Signed-off-by: Peng Li
---
From: Yonglong Liu
Create a net bridge, add eth and vnet to the bridge. The vnet is used
by a virtual machine. When ping the virtual machine from the outside
host and the virtual machine send multicast at the same time, the ping
package will lost.
The multicast package send to the eth, eth will
From: Yonglong Liu
According to the hip06 datasheet:
1.Six registers use wrong address:
RCB_COM_SF_CFG_INTMASK_RING
RCB_COM_SF_CFG_RING_STS
RCB_COM_SF_CFG_RING
RCB_COM_SF_CFG_INTMASK_BD
RCB_COM_SF_CFG_BD_RINT_STS
DSAF_INODE_VC1_IN_PKT_NUM_0_REG
2.The offset of
Add devicetree support for 96Boards Chameleon96 board from Novtech, Inc.
based on Altera CycloneV SoC FPGA. This board is one of the Consumer
Edition boards of the 96Boards family and has the following key features:
* SoC - Intel Cyclone V SoC FPGA
* GPU - Graphics based on Intel Video Suite for
Hello,
This patchset adds board support for Chameleon96 board from Novetech
based on Intel Cyclone V SoC FPGA. This board is one of the Consumer
Edition boards of the 96Boards family and has the following key features:
* SoC - Intel Cyclone V SoC FPGA
* GPU - Graphics based on Intel Video
Add vendor prefix for NovTech, Inc.
Signed-off-by: Manivannan Sadhasivam
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree/bindings/vendor-prefixes.txt
On Thu, 13 Dec 2018 17:09:35 +
James Morse wrote:
> Hi Steven,
>
> I gave this branch a spin, but I hit the WARN_ON() fairly easily:
Thanks for testing!
Can you see if this patch fixes it for you?
-- Steve
diff --git a/kernel/trace/fgraph.c b/kernel/trace/fgraph.c
index
On Fri, 2018-12-14 at 11:45 -0800, Matthew Wilcox wrote:
> On Fri, Dec 14, 2018 at 11:40:45AM -0800, Joe Perches wrote:
> > On Fri, 2018-12-14 at 10:13 -0800, Matthew Wilcox wrote:
> > > On Fri, Dec 14, 2018 at 10:07:18AM -0800, Roman Gushchin wrote:
> > > > +/*
> > > > + * Allocate a region of
On 12/14/18 3:59 AM, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 4.4.168 release.
There are 88 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be
On 12/14/18 4:00 AM, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 4.9.146 release.
There are 51 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be
On 12/14/18 3:59 AM, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 4.14.89 release.
There are 89 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be
On 12/14/18 3:58 AM, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 4.19.10 release.
There are 142 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be
From: Keith Busch
Add memblock based enumeration of memory-side-cache of System RAM.
Detect the capability in early init through HMAT tables, and set the
size in the address range memblocks if a direct mapped side cache is
present.
Cc:
Cc: "Rafael J. Wysocki"
Cc: Dave Hansen
Cc: Andy
Changes since v4: [1]
* Default the randomization to off and enable it dynamically based on
the detection of a memory side cache advertised by platform firmware.
In the case of x86 this enumeration comes from the ACPI HMAT. (Michal
and Mel)
* Improve the changelog of the patch that
Randomization of the page allocator improves the average utilization of
a direct-mapped memory-side-cache. Memory side caching is a platform
capability that Linux has been previously exposed to in HPC
(high-performance computing) environments on specialty platforms. In
that instance it was a
When freeing a page with an order >= shuffle_page_order randomly select
the front or back of the list for insertion.
While the mm tries to defragment physical pages into huge pages this can
tend to make the page allocator more predictable over time. Inject the
front-back randomness to preserve
In preparation for runtime randomization of the zone lists, take all
(well, most of) the list_*() functions in the buddy allocator and put
them in helper functions. Provide a common control point for injecting
additional behavior when freeing pages.
Cc: Michal Hocko
Cc: Dave Hansen
From: Keith Busch
Parsing entries in an ACPI table had assumed a generic header
structure. There is no standard ACPI header, though, so less common
layouts with different field sizes required custom parsers to go through
their subtable entry list.
Create the infrastructure for adding different
On 12/14/18 2:23 AM, Ard Biesheuvel wrote:
> On Fri, 14 Dec 2018 at 05:08, Qian Cai wrote:
>> Also tried to move the local TLB flush part around a bit inside
>> __cpu_setup(), although it did complete kdump some times, it did trigger
>> "Synchronous Exception" in EFI after a cold-reboot fairly
Clang warns:
drivers/pci/pci-driver.c:1603:21: error: unused variable 'attr'
[-Werror,-Wunused-variable]
Commit e5361ca29f2f ("ACPI / scan: Refactor _CCA enforcement") removed
attr's use and replaced it with its assigned value so it is no longer
needed.
Signed-off-by: Nathan Chancellor
---
On Thu, Dec 06, 2018 at 01:23:32PM +, David HERNANDEZ SANCHEZ wrote:
> Calling stm_thermal_read_factory_settings before clocking
> internal peripheral causes bad register values and makes
> temperature computation wrong.
>
> Calling stm_thermal_read_factory_settings inside
>
"kernelci.org bot" writes:
> gtucker/kernelci-stable boot bisection: v4.19.9 on meson-gxbb-p200
>
> Summary:
> Start: be53d23e68c2 Linux 4.19.9
> Details:https://kernelci.org/boot/id/5c13e85d59b5144a340a819d
> Plain log:
>
> > diff --git a/arch/alpha/include/uapi/asm/socket.h
> > b/arch/alpha/include/uapi/asm/socket.h
> > index 00e45c80e574..352e3dc0b3d9 100644
> > --- a/arch/alpha/include/uapi/asm/socket.h
> > +++ b/arch/alpha/include/uapi/asm/socket.h
> > @@ -3,6 +3,7 @@
> > #define _UAPI_ASM_SOCKET_H
> >
> >
We are compiling PCI code today for systems with ACPI and no PCI
device present. Remove the useless code and reduce the tight
dependency.
Signed-off-by: Sinan Kaya
Acked-by: Bjorn Helgaas # PCI parts
---
arch/x86/include/asm/pci_x86.h | 7 +++
drivers/acpi/Kconfig | 1 -
Now that we allow CONFIG_PCI to be unset, remove useless code from ACPICA
too.
Signed-off-by: Sinan Kaya
---
drivers/acpi/acpica/Makefile| 2 +-
drivers/acpi/acpica/achware.h | 9 +
include/acpi/platform/aclinux.h | 4
3 files changed, 14 insertions(+), 1 deletion(-)
diff
Remove PCI dependent code out of iort.c when CONFIG_PCI is not defined.
Signed-off-by: Sinan Kaya
---
drivers/acpi/arm64/iort.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
index 70f4e80b9246..d0f68607efe6 100644
---
ACPI and PCI are no longer coupled to each other. Specify requirements
for both when pulling in code.
Signed-off-by: Sinan Kaya
---
arch/arm64/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index ea2ab0330e3a..bcb6262044d8
Getting ready to allow CONFIG_PCI to be unset with ACPI enabled. Stub out
acpi_os_read_pci_configuration and acpi_os_write_pci_configuration
functions when CONFIG_PCI is not defined.
Signed-off-by: Sinan Kaya
---
drivers/acpi/osl.c | 14 ++
1 file changed, 14 insertions(+)
diff
Make PCI reboot conditional on PCI support being present on the kernel
configuration.
Signed-off-by: Sinan Kaya
---
drivers/acpi/reboot.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/acpi/reboot.c b/drivers/acpi/reboot.c
index 6fa9c2a4cfe9..d75e637ee36a
Hi Peter,
On Thu, Dec 13, 2018 at 7:53 PM Peter Zijlstra wrote:
>
> On Thu, Dec 13, 2018 at 06:17:41PM +0900, Masahiro Yamada wrote:
> > Revert the following commits:
> >
> > - 5bdcd510c2ac9efaf55c4cbd8d46421d8e2320cd
> > ("x86/jump-labels: Macrofy inline assembly code to work around GCC
> >
On 12/14/18 12:03 PM, Matthew Wilcox wrote:
> On Fri, Dec 14, 2018 at 11:53:31AM -0800, Dave Hansen wrote:
>> On 12/14/18 11:48 AM, Matthew Wilcox wrote:
>>> I think we can do better than a proxy object with bit 0 set. I'd go
>>> for allocating something like this:
>>>
>>> struct dynamic_page {
On Wed, 12 Dec 2018 09:21:43 +0100
Auger Eric wrote:
> Hi Jacob,
>
> On 9/21/18 12:06 AM, Jacob Pan wrote:
> > On Tue, 18 Sep 2018 16:24:51 +0200
> > Eric Auger wrote:
> >
> >> From: Jacob Pan
> >>
> >> Device faults detected by IOMMU can be reported outside IOMMU
> >> subsystem for
On Fri, Dec 14, 2018 at 11:19:59AM +0100, Michal Hocko wrote:
>[Your From address seems to have a typo (linux.bm.com) - fixed]
>
>On Fri 14-12-18 10:33:55, Zaslonko Mikhail wrote:
>[...]
>> Yes, it might still trigger PF_POISONED_CHECK if the first page
>> of the pageblock is left uninitialized
This patch adds HW Command Queue for supported Tegra SDMMC
controllers.
Tegra SDHCI with Quirk SDHCI_QUIRK2_BROKEN_64_BIT_DMA disables the
use of 64_BIT DMA to disable 64-bit addressing mode access to the
system memory and sdhci_cqe_enable using flag SDHCI_USE_64_BIT_DMA
for ADMA32/ADMA2 Vs
From: Duncan Laurie
This EC is an incompatible variant of the typical Chrome OS embedded
controller. It uses the same low-level communication and a similar
protocol with some significant differences. The EC firmware does
not support the same mailbox commands so it is not registered as a
From: Duncan Laurie
The Wilco Embedded Controller can return extended events that
are not handled by standard ACPI objects. These events can
include hotkeys which map to standard functions like brightness
controls, or information about EC controlled features like the
charger or battery.
These
A Property is typically a data item that is stored to NVRAM.
Each of these data items has an index associated with it
known as the Property ID (PID). The Property ID is
used by the system BIOS (and EC) to refer to the Property.
Properties may have variable lengths. Many features are
implemented
The Wilco Embedded Controller is able to send telemetry data
which is useful for enterprise applications. A daemon running on
the OS sends a command (possibly with args) to the EC via
this sysfs interface, and the EC responds over the sysfs interface
with the response. Both the request and the
Hi Pavel,
On Fri, Dec 14, 2018 at 3:24 PM Pavel Machek wrote:
>
>
> I believe I have hardware problem, but I'm kind of hoping software
> could help me...?
>
> Mouse wheel on my machine started glitching on my machine, generating
> double-clicks when I click it once. Which unfortunately is quite
Legacy attributes are EC properties that are non-chromebook specific,
ones which existed before the EC was modified for Chromebooks (as I
understand it at least). This adds no new behavior, but just refactors
the existing legacy attributes so adding more attributes in the future
will work in an
From: Duncan Laurie
This Embedded Controller has an internal RTC that is exposed
as a standard RTC class driver with read/write functionality.
> hwclock --show --rtc /dev/rtc1
2007-12-31 16:01:20.460959-08:00
> hwclock --systohc --rtc /dev/rtc1
> hwclock --show --rtc /dev/rtc1
2018-11-29
Create "peakshift" and "advanced_battery_charging" directories
within the "properties" directory, and create the relevant
attributes within these. These properties have to do with
configuring some of the advanced power management options that
prolong battery health and reduce energy use at peak
From: Duncan Laurie
Add some sample sysfs attributes for the Wilco EC that show how
the mailbox interface works.
> cat /sys/bus/platform/devices/GOOG000C\:00/version
Label: 99.99.99
SVN Revision : 738ed.99
Model Number : 08;8
Build Date : 08/30/18
Signed-off-by: Duncan Laurie
The Chromebook named wilco contains a different Embedded Controller
than the rest of the chromebook series, and thus the kernel requires
a different driver than the already existing and generalized
cros_ec_* drivers. Specifically, this driver adds support for getting
and setting the RTC on the EC,
From: Duncan Laurie
In order to allow this code to be re-used, remove the dependency
on the rest of the cros_ec code from the cros_ec_lpc_mec functions.
Instead of using a hardcoded register base address of 0x800 have
this be passed in to cros_ec_lpc_mec_init(). The existing cros_ec
use case
From: Duncan Laurie
Add a sysfs attribute that allows sending raw commands to the EC.
This is useful for development and debug but should not be enabled
in a production environment.
> echo 00 f0 38 00 03 00 > /sys/bus/platform/devices/GOOG000C\:00/raw
> cat
>
> On Fri, 14 Dec 2018 at 13:56, James Morse wrote:
> >
> > Hi Dongjiu Geng,
> >
> > On 14/12/2018 10:15, Dongjiu Geng wrote:
> > > When user space do memory recovery, it will check whether KVM and
> > > guest support the error recovery, only when both of them support,
> > > user space will
On 12/14/18 3:10 AM, David Hildenbrand wrote:
> The usage of PG_reserved and how PG_reserved pages are to be treated is
> buried deep down in different parts of the kernel. Let's shine some light
> onto these details by documenting current users and expected
> behavior.
>
> Especially, clarify on
gengdongjiu 将撤回邮件“[RFC RESEND PATCH] kvm: arm64: export memory error recovery
capability to user space”。
>
> On Fri, 14 Dec 2018 at 13:56, James Morse wrote:
> >
> > Hi Dongjiu Geng,
> >
> > On 14/12/2018 10:15, Dongjiu Geng wrote:
> > > When user space do memory recovery, it will check whether KVM and
> > > guest support the error recovery, only when both of them support,
> > > user space will do
On Fri, Dec 14, 2018 at 05:59:17PM -0600, Dr. Greg wrote:
> On Wed, Dec 12, 2018 at 08:00:36PM +0200, Jarkko Sakkinen wrote:
>
> Good evening, I hope the week has gone well for everyone.
>
> > On Mon, Dec 10, 2018 at 04:49:08AM -0600, Dr. Greg wrote:
> > > In the meantime, I wanted to confirm
On Wed, Dec 12, 2018 at 08:00:36PM +0200, Jarkko Sakkinen wrote:
Good evening, I hope the week has gone well for everyone.
> On Mon, Dec 10, 2018 at 04:49:08AM -0600, Dr. Greg wrote:
> > In the meantime, I wanted to confirm that your jarkko-sgx/master
> > branch contains the proposed driver that
44d8047f1d8 ("binder: use standard functions to allocate fds")
exposed a pre-existing issue in the binder driver.
fdget() is used in ksys_ioctl() as a performance optimization.
One of the rules associated with fdget() is that ksys_close() must
not be called between the fdget() and the fdput().
[+cc Rafael, Len, linux-acpi, linux-kernel]
Thanks a lot for working on this! I've been hoping somebody would
push on the PMU issue because there are some real wrinkles to work
out.
On Fri, Dec 14, 2018 at 09:10:55PM +0800, Jonathan Cameron wrote:
> The Hip08 SoCs contain relatively detailed
The function ipu_csi_init_interface() was inverting the F-bit for
NTSC case, in the CCIR_CODE_1/2 registers. The result being that
for NTSC bottom-top field order, the CSI would swap fields and
capture in top-bottom order.
Instead, base field swap on the field order of the input to the CSI,
and
On 12/13/18 4:59 AM, Philipp Zabel wrote:
Hi Steve,
On Tue, 2018-10-16 at 17:00 -0700, Steve Longerbeam wrote:
The function ipu_csi_init_interface() was inverting the F-bit for
NTSC case, in the CCIR_CODE_1/2 registers. The result being that
for NTSC bottom-top field order, the CSI would
From: "Gustavo A. R. Silva"
Date: Tue, 11 Dec 2018 14:10:08 -0600
> vr.mifi is indirectly controlled by user-space, hence leading to
> a potential exploitation of the Spectre variant 1 vulnerability.
>
> This issue was detected with the help of Smatch:
>
> net/ipv6/ip6mr.c:1845 ip6mr_ioctl()
On 2018-12-14 10:26 pm, Bjorn Helgaas wrote:
[+cc Lorenzo, Robin, Logan]
On Fri, Dec 14, 2018 at 04:33:19PM +, Sinan Kaya wrote:
ACPI IORT table code relies on pci_request_acs() to be present. Define
a stub function when CONFI_PCI is not set.
This doesn't seem like the simplest approach
Hello, I have sent the transaction details.
---
This email has been checked for viruses by Avast antivirus software.
https://www.avast.com/antivirus
On Fri, Dec 14, 2018 at 2:12 PM Arnd Bergmann wrote:
>
> Upstream commit 3e9efc3299dd ("i2c: aspeed: Handle master/slave combined irq
> events
> properly") reworked the interrupt handling and fixed a warning in the process:
>
> drivers/i2c/busses/i2c-aspeed.c: In function 'aspeed_i2c_bus_irq':
>
I believe I have hardware problem, but I'm kind of hoping software
could help me...?
Mouse wheel on my machine started glitching on my machine, generating
double-clicks when I click it once. Which unfortunately is quite
annoying: texts are pasted twice, two tabs are closed instead of one,
From: Deepa Dinamani
Date: Tue, 11 Dec 2018 12:25:12 -0800
> The series introduces new socket timestamps that are
> y2038 safe.
Please address Willem's feedback, thank you.
On 12/10/18 2:05 PM, Maran Wilson wrote:
> For certain applications it is desirable to rapidly boot a KVM virtual
> machine. In cases where legacy hardware and software support within the
> guest is not needed, Qemu should be able to boot directly into the
> uncompressed Linux kernel binary
On Fri, Dec 14, 2018 at 01:04:11PM -0800, David Rientjes wrote:
> On Wed, 12 Dec 2018, Vlastimil Babka wrote:
>
> > > Regarding the role of direct reclaim in the allocator, I think we need
> > > work on the feedback from compaction to determine whether it's
> > > worthwhile.
> > > That's
Hi Pawel,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on usb/usb-testing]
[also build test WARNING on v4.20-rc6 next-20181214]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day
Compaction is inherently race-prone as a suitable page freed during compaction
can be allocated by any parallel task. This patch uses a capture_control
structure to isolate a page immediately when it is freed by a direct compactor
in the slow path of the page allocator.
Remote compaction is expensive and possibly counter-productive. Locality
is expected to often have better performance characteristics than remote
high-order pages. For small allocations, it's expected that locality is
generally required or fallbacks are possible. For larger allocations such
as
Similar to the migration scanner, this uses the free lists to quickly
locate a migration target. The search is different in that lower orders
will be searched for a suitable high PFN if necessary but the search
is still bound. This is justified on the grounds that the free scanner
typically scans
1 - 100 of 1344 matches
Mail list logo
