On 23-04-19, 16:28, Georgi Djakov wrote:
> If the OPP bandwidth values are populated, we want to switch also the
> interconnect bandwidth in addition to frequency and voltage.
>
> Signed-off-by: Georgi Djakov
> ---
> drivers/opp/core.c | 9 -
> 1 file changed, 8 insertions(+), 1
On Tue, Apr 23, 2019 at 9:22 PM Eduardo Valentin wrote:
>
> Hello,
>
> On Tue, Apr 02, 2019 at 06:12:44PM +0200, Daniel Lezcano wrote:
> > The module support for the thermal subsystem makes little sense:
> > - some subsystems relying on it are not modules, thus forcing the
> >framework to be
On (04/23/19 09:48), Steven Rostedt wrote:
> > RFC
> >
> > Normally, we grab console_sem lock before we iterate consoles
> > list, which is necessary if we want to be race free. The only exception
> > to this rule is console_flush_on_panic(). However, it seems that we are
> > not fully
Is anyone going to pick this patch up?
Add support for Synopsys DesignWare core IP based PCIe host controller
present in Tegra194 SoC.
Signed-off-by: Vidya Sagar
---
Changes since [v4]:
* None
Changes since [v3]:
* None
Changes since [v2]:
* Changed 'nvidia,init-speed' to 'nvidia,init-link-speed'
* Changed 'nvidia,pex-wake' to
ZQ,
On Fri, Apr 12, 2019 at 3:22 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Refactor the Mobiveil PCIe Host Bridge IP driver to make
> it easier to add support for both RC and EP mode driver.
> This patch moved the Mobiveil driver to an new directory
> 'drivers/pci/controller/mobiveil' and
On Tue, 23 Apr 2019 at 11:56, Enric Balletbo i Serra
wrote:
>
> Hi Tomeu,
>
> On 23/4/19 10:11, Tomeu Vizoso wrote:
> > Callers don't expect it to return NULL, but an error code.
> >
> > Fixes Oops such as the one below, when one tries to set a governor that
> > isn't available:
> >
> > Unable to
On Tue, Apr 23, 2019 at 05:25:00PM +0200, Sebastian Andrzej Siewior wrote:
> On 2019-04-15 13:04:03 [+0200], To Paul E. McKenney wrote:
> >
> > good so nothing important so far. I hope the box gets to TREE08 soon.
>
> test completed. Nothing new.
That took some time! Thank you for running it!
On 23-04-19, 16:28, Georgi Djakov wrote:
> In addition to frequency and voltage, some devices may have bandwidth
> requirements for their interconnect throughput - for example a CPU
> or GPU may also need to increase or decrease their bandwidth to DDR
> memory based on the current operating
Add PCIe host controller driver for DesignWare core based
PCIe controller IP present in Tegra194.
Signed-off-by: Vidya Sagar
---
Changes since [v4]:
* None
Changes since [v3]:
* None
Changes since [v2]:
* None
Changes since [v1]:
* Changed CONFIG_PCIE_TEGRA194 from 'y' to 'm'
Add P2U (PIPE to UPHY) and PCIe controller nodes to device tree.
The Tegra194 SoC contains six PCIe controllers and twenty P2U instances
grouped into two different PHY bricks namely High-Speed IO (HSIO-12 P2Us)
and NVIDIA High Speed (NVHS-8 P2Us) respectively.
Signed-off-by: Vidya Sagar
---
Synopsys DesignWare core based PCIe controllers in Tegra 194 SoC interface
with Universal PHY (UPHY) module through a PIPE2UPHY (P2U) module.
For each PCIe lane of a controller, there is a P2U unit instantiated at
hardware level. This driver provides support for the programming required
for each
Enable PCIe controller nodes to enable respective PCIe slots on
P2972- board. Following is the ownership of slots by different
PCIe controllers.
Controller-0 : M.2 Key-M slot
Controller-1 : On-board Marvell eSATA controller
Controller-3 : M.2 Key-E slot
Signed-off-by: Vidya Sagar
---
Changes
Add support for Tegra194 P2U (PIPE to UPHY) module block which is a glue
module instantiated one for each PCIe lane between Synopsys Designware core
based PCIe IP and Universal PHY block.
---
Changes since [v4]:
* None
Changes since [v3]:
* None
Changes since [v2]:
* Changed node label to
Add support for Tegra194 PCIe controllers. These controllers are based
on Synopsys DesignWare core IP.
Signed-off-by: Vidya Sagar
---
Changes since [v4]:
* None
Changes since [v3]:
* None
Changes since [v2]:
* Using only 'Cx' (x-being controller number) format to represent a controller
*
Add support to enable CDM (Configuration Dependent Module) register check
for any data corruption based on the device-tree flag 'enable-cdm-check'.
Signed-off-by: Vidya Sagar
Acked-by: Gustavo Pimentel
---
Changes since [v4]:
* None
Changes since [v3]:
* None
Changes since [v2]:
* Changed
Add support to enable CDM (Configuration Dependent Module) registers check
for any data corruption. CDM registers include standard PCIe configuration
space registers, Port Logic registers and iATU and DMA registers.
Refer Section S.4 of Synopsys DesignWare Cores PCI Express Controller Databook
Some host controllers need to know the existence of clkreq signal routing to
downstream devices to be able to advertise low power features like ASPM L1
substates. Without clkreq signal routing being present, enabling ASPM L1 sub
states might lead to downstream devices falling off the bus. Hence a
Export pcie_bus_config to enable host controller drivers setting it to a
specific configuration be able to build as loadable modules
Signed-off-by: Vidya Sagar
---
Changes since [v4]:
* None
Changes since [v3]:
* None
Changes since [v2]:
* None
Changes since [v1]:
* This is a new patch in v2
Remove multiple write enable and disable sequences of dbi registers as
Tegra194 implements writes to BAR-0 register (offset: 0x10) controlled by
DBI write-lock enable bit thereby not allowing any further writes to BAR-0
register in config space to take place. Hence disabling write permission
only
Move PCIe config space capability search API to common DesignWare file
as this can be used by both host and ep mode codes.
Signed-off-by: Vidya Sagar
Acked-by: Gustavo Pimentel
---
Changes from [v4]:
* Removed redundant APIs in pcie-designware-ep.c file after moving them
to pcie-designware.c
Add extended configuration space capability search API using struct dw_pcie *
pointer
Signed-off-by: Vidya Sagar
Acked-by: Gustavo Pimentel
---
Changes from [v4]:
* None
Changes from [v3]:
* None
Changes from [v2]:
* None
Changes from [v1]:
* This is a new patch in v2 series
Export pcie_pme_disable_msi() & pcie_pme_no_msi() APIs to enable drivers
using this API be able to build as loadable modules.
Signed-off-by: Vidya Sagar
---
Changes from [v4]:
* None
Changes from [v3]:
* None
Changes from [v2]:
* Exported pcie_pme_no_msi() API after making
Hi ,
Sorry for spam,
when is the plan to merge this patch.
Regards
Gaurav
On 4/16/2019 4:45 PM, Gaurav Kohli wrote:
Hi ,
I have reviewed and tested for both enabled and disabled and working as
expected.
Please feel free to add:
Reviewed-by: Gaurav Kohli
Tested-by: Gaurav Kohli
Add #defines only for the Data Link Feature and Physical Layer 16.0 GT/s
features.
Signed-off-by: Vidya Sagar
Reviewed-by: Thierry Reding
---
Changes from [v4]:
* None
Changes from [v3]:
* None
Changes from [v2]:
* Updated commit message and description to explicitly mention that defines are
Tegra194 has six PCIe controllers based on Synopsys DesignWare core.
There are two Universal PHY (UPHY) blocks with each supporting 12(HSIO:
Hisg Speed IO) and 8(NVHS: NVIDIA High Speed) lanes respectively.
Controllers:0~4 use UPHY lanes from HSIO brick whereas Controller:5 uses
UPHY lanes from
Currently IRQ remains enabled after .remove, later if device is probed,
IRQ is requested before .thermal_init, this may cause IRQ function be
called before device is initialized.
this patch disables interrupt in .remove, to ensure irq function
only be called after device is fully initialized.
Currently IRQF_SHARED type interrupt line is allocated, but it
is not appropriate, as the interrupt line isn't shared between
different devices, instead IRQF_ONESHOT is the proper type.
By changing interrupt type to IRQF_ONESHOT, now irq handler is
no longer needed, as clear of interrupt status
There are issues with interrupt handling in rcar_gen3_thermal driver.
Currently IRQ is remain enabled after .remove, later if device is probed,
IRQ is requested before .thermal_init, this may cause IRQ function be
triggered but not able to clear IRQ status, thus cause system to hang.
Since the
Hi all,
Today's linux-next merge of the tip tree got a conflict in:
arch/arm64/include/asm/Kbuild
between commit:
c67fdc1f00cb ("arch: mostly remove ")
from the asm-generic tree and commit:
46ad0840b158 ("locking/rwsem: Remove arch specific rwsem files")
from the tip tree.
I fixed it
Let's reparent memcg slab memory on memcg offlining. This allows us
to release the memory cgroup without waiting for the last outstanding
kernel object (e.g. dentry used by another application).
So instead of reparenting all accounted slab pages, let's do reparent
a relatively small amount of
Hi Helmut,
> -Original Message-
> From: Helmut Grohne
> Sent: Tuesday, April 23, 2019 6:15 PM
> To: Naga Sureshkumar Relli
> Cc: bbrezil...@kernel.org; miquel.ray...@bootlin.com; rich...@nod.at;
> dw...@infradead.org; computersforpe...@gmail.com; marek.va...@gmail.com;
> linux-
>
Altera MSI IP is a soft IP and is only available after
FPGA image is programmed.
Make driver modulable to support use case FPGA image is programmed
after kernel is booted. User proram FPGA image in kernel then only load
MSI driver module.
Signed-off-by: Ley Foon Tan
---
Altera PCIe Rootport IP is a soft IP and is only available after
FPGA image is programmed.
Make driver modulable to support use case FPGA image is programmed
after kernel is booted. User proram FPGA image in kernel then only load
PCIe driver module.
Signed-off-by: Ley Foon Tan
---
# Why do we need this?
We've noticed that the number of dying cgroups is steadily growing on most
of our hosts in production. The following investigation revealed an issue
in userspace memory reclaim code [1], accounting of kernel stacks [2],
and also the mainreason: slab objects.
The underlying
Initialize kmem_cache->memcg_params.memcg pointer in
memcg_link_cache() rather than in init_memcg_params().
Once kmem_cache will hold a reference to the memory cgroup,
it will simplify the refcounting.
For non-root kmem_caches memcg_link_cache() is always called
before the kmem_cache becomes
Let's separate the page counter modification code out of
__memcg_kmem_uncharge() in a way similar to what
__memcg_kmem_charge() and __memcg_kmem_charge_memcg() work.
This will allow to reuse this code later using a new
memcg_kmem_uncharge_memcg() wrapper, which calls
__memcg_kmem_unchare_memcg()
Currently the page accounting code is duplicated in SLAB and SLUB
internals. Let's move it into new (un)charge_slab_page helpers
in the slab_common.c file. These helpers will be responsible
for statistics (global and memcg-aware) and memcg charging.
So they are replacing direct
On 04/18/2019 06:14 AM, Quentin Perret wrote:
> On Tuesday 16 Apr 2019 at 15:38:39 (-0400), Thara Gopinath wrote:
>> +/**
>> + * Function to update thermal pressure from cooling device
>> + * or any framework responsible for capping cpu maximum
>> + * capacity.
>> + */
>> +void
On Tue, Apr 23, 2019 at 02:31:18PM +0530, Bharath Vedartham wrote:
> This patch fixes the sparse warning:
> warning: restricted __fs16 degrades to integer
>
> inode->ui_u1.oldids.ui_suid is of type __fs16, a restricted integer.
> 0X is a 16 bit unsigned integer. Use __force to fix the sparse
On Wed, Apr 24, 2019 at 4:49 AM Kees Cook wrote:
>
> This refactors the stack memory initialization configs in order to
> keep things together when adding Clang stack initialization, and in
> preparation for future heap memory initialization configs.
>
> I intend to carry this in the gcc-plugins
On Tue, Apr 23, 2019 at 4:57 PM Andy Lutomirski wrote:
>
> To clarify, this is “fail if you can’t find the files to install, but don’t
> even try to check whether those files are up to date”, right?
Ack. Exactly because the whole "check whether the files are
up-to-date" is generally part of the
On Wed, Apr 24, 2019 at 4:36 AM Kees Cook wrote:
>
> On Thu, Apr 11, 2019 at 6:39 PM Masahiro Yamada
> wrote:
> >
> > On Fri, Apr 12, 2019 at 3:01 AM Kees Cook wrote:
> > >
> > > Right now kernel hardening options are scattered around various Kconfig
> > > files. This can be a central place to
Friendly ping...
> From: Zhiqiang Liu
>
> In proc_dointvec_jiffies func, the write value is only checked
> whether it is larger than INT_MAX. If the write value is less
> than zero, it can also be successfully writen in the data.
>
> However, in some scenarios, users would adopt the data to
On 24-04-19, 10:32, andy.t...@nxp.com wrote:
> From: Yuantian Tang
>
> Enable cpufreq feature on ls1028a chip by adding its compatible
> string.
>
> Signed-off-by: Yuantian Tang
> ---
> drivers/cpufreq/qoriq-cpufreq.c |1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff
On Wed, Apr 24, 2019 at 1:12 PM Vidya Sagar wrote:
>
> On 4/24/2019 2:02 AM, Bjorn Helgaas wrote:
> > On Tue, Apr 23, 2019 at 01:57:19PM +0530, Vidya Sagar wrote:
> >> Move PCIe config space capability search API to common DesignWare file
> >> as this can be used by both host and ep mode codes.
>
On Wed, Apr 24, 2019 at 8:40 AM Linus Torvalds
wrote:
>
> On Tue, Apr 23, 2019 at 11:47 AM Andy Lutomirski wrote:
> >
> > Hmm. I suppose an alternative would be for vdso_install to fail if
> > the vdso isn't built?
>
> I absolutely abhor even the concept of building the kernel as root,
> and I
Enable CONFIG_THERMAL_STATISTICS to extend the sysfs interface
for thermal cooling devices and expose some useful statistics.
Signed-off-by: Anson Huang
---
arch/arm/configs/imx_v6_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig
> -Original Message-
> From: Guo Ren
> Sent: Wednesday, April 24, 2019 03:08
> To: Gary Guo
> Cc: Christoph Hellwig ; linux-a...@vger.kernel.org; Palmer
> Dabbelt ; Andrew Waterman ; Arnd
> Bergmann ; Anup Patel ; Xiang
> Xiaoyan ; linux-kernel@vger.kernel.org; Mike
> Rapoport ;
On 4/24/2019 2:05 AM, Bjorn Helgaas wrote:
On Tue, Apr 23, 2019 at 01:57:20PM +0530, Vidya Sagar wrote:
Add extended configuration space capability search API using struct dw_pcie *
pointer
Signed-off-by: Vidya Sagar
Acked-by: Gustavo Pimentel
---
Changes from [v3]:
* None
Changes from
On 4/24/2019 2:02 AM, Bjorn Helgaas wrote:
On Tue, Apr 23, 2019 at 01:57:19PM +0530, Vidya Sagar wrote:
Move PCIe config space capability search API to common DesignWare file
as this can be used by both host and ep mode codes.
Signed-off-by: Vidya Sagar
Acked-by: Gustavo Pimentel
---
Changes
On 2019-04-23 at 11:02 -0300, Fabio Estevam wrote:
> Hi Robin,
>
> On Tue, Apr 23, 2019 at 10:50 AM Robin Gong
> wrote:
> >
> >
> > This reverts commit df07101e1c4a29e820df02f9989a066988b160e6.
> You need to provide a detailed explanation in the commit log as to
> why
> the revert is needed.
Gentle ping...
> -Original Message-
> From: Anson Huang
> Sent: Wednesday, April 10, 2019 9:47 AM
> To: thierry.red...@gmail.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; s.ha...@pengutronix.de; ker...@pengutronix.de;
> feste...@gmail.com; li...@armlinux.org.uk;
On 04/20/19 at 01:57P, Borislav Petkov wrote:
> On Thu, Apr 18, 2019 at 11:41:15AM +0800, WANG Chao wrote:
> > count_threshol == 1 isn't working as expected. CEC only does soft
> > offline the second time the same pfn is hit by a correctable error.
>
> So this?
>
> ---
> diff --git
Remove .owner field if calls are used which set it automatically
Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci
Signed-off-by: YueHaibing
---
drivers/staging/kpc2000/kpc_spi/spi_driver.c | 1 -
1 file changed, 1 deletion(-)
diff --git
Remove duplicated include.
Signed-off-by: YueHaibing
---
drivers/staging/kpc2000/kpc2000/kp2000_module.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/staging/kpc2000/kpc2000/kp2000_module.c
b/drivers/staging/kpc2000/kpc2000/kp2000_module.c
index 661b0b74ed66..fa3bd266ba54 100644
From: Yuantian Tang
Enable cpufreq feature on ls1028a chip by adding its compatible
string.
Signed-off-by: Yuantian Tang
---
drivers/cpufreq/qoriq-cpufreq.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/cpufreq/qoriq-cpufreq.c
From: Yuantian Tang
Add ls1028a chip compatible string in binding document.
Signed-off-by: Yuantian Tang
---
.../devicetree/bindings/clock/qoriq-clock.txt |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
From: Lakshmi Ramasubramanian
Signed-off-by: Lakshmi Ramasubramanian
---
When CONFIG_KEXEC_VERIFY_SIG is selected the signature on
the new kernel image is verified in kexec_file_load.
The signature is embedded in the kernel image file.
This change returns the pointer to the verified
Hi Gary,
On Tue, Apr 23, 2019 at 03:57:30PM +, Gary Guo wrote:
> >>> Another point is we could get more attribute bits by modify the riscv
> >>> spec:
> >>> - Remove Global bit, I think it's duplicate with the User bit in linux.
> >>
> >> It is in Linux, but it is conceptually very
On 2019/4/24 1:44, Sean Christopherson wrote:
On Tue, Apr 23, 2019 at 11:23:59AM +0800, Like Xu wrote:
On 2019/4/23 2:35, Sean Christopherson wrote:
#define F(x) bit(X86_FEATURE_##x)
int kvm_update_cpuid(struct kvm_vcpu *vcpu)
@@ -426,6 +436,7 @@ static inline int __do_cpuid_ent(struct
The traceevnt lib is used by perf tool, when execute 'perf test -v 6' it
outputs error log on ARM64 platform:
running test 33 '*:*'trace-cmd: No such file or directory
[...]
trace-cmd: Invalid argument
The trace event parsing code originally came from trace-cmd so it keeps
the tag string
On 2019-04-17 03:39, Jarkko Sakkinen wrote:
diff --git a/arch/x86/include/uapi/asm/sgx.h b/arch/x86/include/uapi/asm/sgx.h
index 7bf627ac4958..3b80acde8671 100644
--- a/arch/x86/include/uapi/asm/sgx.h
+++ b/arch/x86/include/uapi/asm/sgx.h
@@ -16,6 +16,8 @@
_IOW(SGX_MAGIC, 0x01, struct
On Mon, Apr 22, 2019 at 7:52 AM Jonathan Cameron wrote:
>
> On Tue, 16 Apr 2019 04:45:51 -0400
> Brian Masney wrote:
>
> > Convert the tsl2772 device tree bindings to the new YAML format.
> >
> > Signed-off-by: Brian Masney
> Hi Brian,
>
> Good to see this. I'm afraid it's all a bit new to me
From: Yuantian Tang
Enable clock driver by adding clock configuration for ls1028a chip.
Signed-off-by: Yuantian Tang
---
drivers/clk/clk-qoriq.c | 68 +++
1 files changed, 68 insertions(+), 0 deletions(-)
diff --git a/drivers/clk/clk-qoriq.c
Hi Matthias,
On Tue, 23 Apr 2019 17:12:10 -0700 Matthias Kaehlcke wrote:
>
> Commit 3560af5a56b5 ("ARM: dts: qcom-apq8064: Set 'xo_board' as
> ref clock of the DSI PHY") specifies the non-existing phandle
> 'xo_board' as DSI PHY ref clk. Fix this by using the correct
> phandle is 'cxo_board'.
>
Add auxadc device node for MT8183
Signed-off-by: Zhiyong Tao
---
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 4
arch/arm64/boot/dts/mediatek/mt8183.dtsi| 10 ++
2 files changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
The commit adds mt8183 compatible node in binding document.
Signed-off-by: Zhiyong Tao
---
Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt
This series includes two patches:
1.Add mt8183 auxadc compatible node in binding document.
1.Add mt8183 auxadc device node.
Changes in patch v2:
1)change auxadc compatible node in binding document for mt8183.
Zhiyong Tao (2):
dt-bindings: adc: mt8183: add binding document
arm64: dts: mt8183:
On 2019-04-23 17:26, Sean Christopherson wrote:
On Tue, Apr 23, 2019 at 11:29:24PM +, Jethro Beekman wrote:
On 2019-04-22 14:58, Sean Christopherson wrote:
Now that the core SGX code is approaching stability, I'd like to start
sending RFCs for the EPC virtualization and KVM bits to hash
On Tue, Apr 23, 2019 at 4:34 PM Tycho Andersen wrote:
>
> On Tue, Apr 23, 2019 at 04:31:45PM -0700, Kees Cook wrote:
> > On Tue, Apr 23, 2019 at 3:09 PM Kees Cook wrote:
> > >
> > > On Wed, Mar 6, 2019 at 12:14 PM Tycho Andersen wrote:
> > > >
> > > > As the comment notes, the return codes for
Local variable *reserved* of remove_dquot_ref() is only used if
define CONFIG_QUOTA_DEBUG, but not ebraced in CONFIG_QUOTA_DEBUG
macro, which leads to unused-but-set-variable warning when compiling.
This patch ebrace it into CONFIG_QUOTA_DEBUG macro like what is done
in add_dquot_ref().
When ACRN hypervisor is detected, the hypercall is needed so that the
ACRN guest can query/config some settings. For example: it can be used
to query the resources in hypervisor and manage the CPU/memory/device/
interrupt for the guest operating system.
So add the hypercall so that ACRN guest can
Add a special Kconfig symbol X86_HV_CALLBACK_VECTOR so that the guests
using the hypervisor interrupt callback counter can select and thus
enable that counter. Select it when xen or hyperv support is enabled.
No functional changes.
Signed-off-by: Zhao Yakui
Reviewed-by: Borislav Petkov
---
Linux kernel uses the HYPERVISOR_CALLBACK_VECTOR for hypervisor upcall
vector. And it is already used for Xen and HyperV.
After ACRN hypervisor is detected, it will also use this defined vector
to notify ACRN guest.
Co-developed-by: Jason Chen CJ
Signed-off-by: Jason Chen CJ
Signed-off-by: Zhao
ACRN is an open-source hypervisor maintained by Linux Foundation.
It is built for embedded IOT with small footprint and real-time features.
Add the ACRN guest support so that it allows Linux to be booted under
ACRN hypervisor. Following this patch it will setup the upcall
notification vector and
ACRN is a flexible, lightweight reference hypervisor, built with real-time
and safety-criticality in mind, optimized to streamline embedded development
through an open source platform. It is built for embedded IOT with small
footprint and real-time features. More details can be found
in
On Thu, Apr 18, 2019 at 2:46 PM Chris Chiu wrote:
>
> Some of latest ASUS laptops support new fn-lock mode switching.
> This commit detect whether if the fn-lock option is enabled in
> BIOS setting, and toggle the fn-lock mode via a new WMI DEVID
> 0x00100023 when the corresponding notify code
On Tue, 2019-04-23 at 16:35 +0200, Matthias Brugger wrote:
>
> On 22/04/2019 13:54, Zhiyong Tao wrote:
> > The commit adds mt8183 compatible node in binding document.
> >
> > Signed-off-by: Zhiyong Tao
> > ---
> > Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt | 1 +
> > 1 file
On Tue, Apr 23, 2019 at 10:54:47PM +0200, Jonas Witschel wrote:
On 2019-04-09 15:44, Jarkko Sakkinen wrote:
On Mon, Apr 08, 2019 at 02:01:38PM +0200, Thibaut Sautereau wrote:
[...]
What's the status of this patch now? It's needed in linux-5.0.y as TPM
2.0 support is currently broken with those
Hi,
On Tue, Apr 23, 2019 at 09:28:48PM +0200, Arnd Bergmann wrote:
> The following changes since commit 9e98c678c2d6ae3a17cb2de55d17f69dddaa231b:
>
> Linux 5.1-rc1 (2019-03-17 14:22:26 -0700)
>
> are available in the Git repository at:
>
>
On Tue, Apr 23, 2019 at 11:29:24PM +, Jethro Beekman wrote:
> On 2019-04-22 14:58, Sean Christopherson wrote:
> >+Cc Jethro
> >
> >On Wed, Apr 17, 2019 at 01:39:25PM +0300, Jarkko Sakkinen wrote:
> >>Intel Software Guard eXtensions (SGX) is a set of CPU instructions that
> >>can be used by
On 4/23/19 11:34 AM, Yang Shi wrote:
On 4/23/19 10:52 AM, Michal Hocko wrote:
On Wed 24-04-19 00:43:01, Yang Shi wrote:
The commit 7635d9cbe832 ("mm, thp, proc: report THP eligibility for
each
vma") introduced THPeligible bit for processes' smaps. But, when
checking
the eligibility for
Hi all,
Commit
a9f58c456e9d ("drm/vmwgfx: Be more restrictive when dirtying resources")
is missing a Signed-off-by from its committer.
--
Cheers,
Stephen Rothwell
pgpp4oxkN5hTJ.pgp
Description: OpenPGP digital signature
Hi Wen,
On Wed, Apr 24, 2019 at 07:32:05AM +0800, Wen Yang wrote:
> The refcount of fw_np has already been decreased by of_find_matching_node()
> so it shouldn't be used anymore.
> This patch adds an of_node_get() before of_find_matching_node() to avoid
> the use-after-free problem.
>
> Fixes:
On Tue, Apr 23, 2019 at 10:23:17PM +0200, Greg Kroah-Hartman wrote:
> On Thu, Apr 18, 2019 at 09:56:02AM +0200, Paolo Bonzini wrote:
> > On 18/04/19 09:38, Takashi Iwai wrote:
> > > Hi,
> > >
> > > we've got a regression report on the recent 5.0.x kernel, starting
> > > from 5.0.6, where Windows
> +
> +void sched_core_enqueue(struct rq *rq, struct task_struct *p)
> +{
...
> +}
> +
> +void sched_core_dequeue(struct rq *rq, struct task_struct *p)
> +{
...
> +}
> +
> +/*
> + * Find left-most (aka, highest priority) task matching @cookie.
> + */
> +struct task_struct
From: Prakhar Srivastava
Signed-off-by: Prakhar Srivastava
---
Currently for soft reboot(kexec_file_load) the kernel file and
signature is measured by IMA. The cmdline args used to load the kernel
is not measured.
The boot aggregate that gets calculated will have no change since the
EFI loader
From: Prakhar Srivastava
Signed-off-by: Prakhar Srivastava
---
Currently for soft reboot(kexec_file_load) the kernel file and
signature is measured by IMA. The cmdline args used to load the kernel
is not measured.
The boot aggregate that gets calculated will have no change since the
EFI loader
From: Prakhar Srivastava
Signed-off-by: Prakhar Srivastava
---
Currently for soft reboot(kexec_file_load) the kernel file and
signature is measured by IMA. The cmdline args used to load the kernel
is not measured.
The boot aggregate that gets calculated will have no change since the
EFI loader
From: Prakhar Srivastava
Signed-off-by: Prakhar Srivastava
---
Currently for soft reboot(kexec_file_load) the kernel file and
signature is measured by IMA. The cmdline args used to load the kernel
is not measured.
The boot aggregate that gets calculated will have no change since the
EFI loader
From: Prakhar Srivastava
Signed-off-by: Prakhar Srivastava
---
Currently for soft reboot(kexec_file_load) the kernel file and
signature is measured by IMA. The cmdline args used to load the kernel
is not measured.
The boot aggregate that gets calculated will have no change since the
EFI loader
Commit 3560af5a56b5 ("ARM: dts: qcom-apq8064: Set 'xo_board' as
ref clock of the DSI PHY") specifies the non-existing phandle
'xo_board' as DSI PHY ref clk. Fix this by using the correct
phandle is 'cxo_board'.
Fixes: 3560af5a56b5 ("ARM: dts: qcom-apq8064: Set 'xo_board' as ref clock of
the DSI
On 4/23/19 9:18 AM, Vineeth Remanan Pillai wrote:
> +/* real prio, less is less */
> +static inline bool __prio_less(struct task_struct *a, struct task_struct *b,
> bool core_cmp)
> +{
> + u64 vruntime;
> +
> + int pa = __task_prio(a), pb = __task_prio(b);
> +
> + if (-pa < -pb)
> +
OF/DT core has a hook for architecture specific logical cpuid to hartid
mapping. By implementing this, we can pass the logical cpu id to cpu
node parsing functions.
Fix the instances where logical cpuid is expected as an argument in
of_get_cpu_node.
Signed-off-by: Atish Patra
---
If nr_cpus command line option is set, maximum possible cpu should be
set to that value.
Signed-off-by: Atish Patra
---
arch/riscv/kernel/smpboot.c | 10 +-
2 files changed, 9 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/kernel/smpboot.
diff --git
Assorted command line option fixes for RISC-V.
Changes from v2->v3.
1. Merged patch 1 & 2 into one patch.
Changes from v1->v2.
1. Update pr_err string in patch (4/4) as per review.
Atish Patra (3):
RISC-V: Add RISC-V specific arch_match_cpu_phys_id
RISC-V: Implement nosmp commandline option.
nosmp command line option sets max_cpus to zero. No secondary harts
will boot if this is enabled. But present cpu mask will still point to
all possible masks.
Fix present cpu mask for nosmp usecase.
Signed-off-by: Atish Patra
---
arch/riscv/kernel/smpboot.c | 12 +++-
1 file changed,
On Tue, 23 Apr 2019 22:03:18 +0200
Peter Zijlstra wrote:
> On Tue, Apr 23, 2019 at 09:55:59PM +0200, Peter Zijlstra wrote:
> > On Tue, Apr 23, 2019 at 03:41:32PM -0400, Waiman Long wrote:
>
> > > I saw a number of instances of
> > > preempt_enable_no_resched() without right next a schedule().
> On Apr 23, 2019, at 4:38 PM, Linus Torvalds
> wrote:
>
>> On Tue, Apr 23, 2019 at 11:47 AM Andy Lutomirski wrote:
>>
>> Hmm. I suppose an alternative would be for vdso_install to fail if
>> the vdso isn't built?
>
> I absolutely abhor even the concept of building the kernel as root,
>
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