The HEVC HANTRO driver needs to know the number of bits to skip at
the beginning of the slice header.
That is a hardware specific requirement so create a dedicated control
that this purpose.
Signed-off-by: Benjamin Gaignard
---
version 5:
- Be even more verbose in control documentation.
- Do no
Implement all the logic to get G2 hardware decoding HEVC frames.
It support up level 5.1 HEVC stream.
It doesn't support yet 10 bits formats or scaling feature.
Add HANTRO HEVC dedicated control to skip some bits at the beginning
of the slice header. That is very specific to this hardware so can't
Add variant to IMX8M to enable G2/HEVC codec.
Define the capabilities for the hardware up to 3840x2160.
G2 doesn't have postprocessor, use the same clocks and got it
own interruption.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Philipp Zabel
---
version 7:
- Add Philipp Reviewed-by tag.
vers
Split VPU node in two: one for G1 and one for G2 since they are
different hardware blocks.
Add syscon for hardware control block.
Remove reg-names property that is useless.
Each VPU node only need one interrupt.
Change G2 assigned clock to match to the specifications.
In the both nodes all the cloc
Make sure that V4L2_PIX_FMT_HEVC_SLICE is correctly handle by v4l2
of the driver.
Signed-off-by: Benjamin Gaignard
---
drivers/staging/media/hantro/hantro_v4l2.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/staging/media/hantro/hantro_v4l2.c
b/drivers/staging/media/hantro/hantro_
Define which HEVC profiles (up to level 5.1) and features
(no scaling, no 10 bits) are supported by the driver.
Signed-off-by: Benjamin Gaignard
---
drivers/staging/media/hantro/hantro.h | 3 ++
drivers/staging/media/hantro/hantro_drv.c | 58 +++
2 files changed, 61 inse
If the variant doesn't offert postprocessed formats make sure it will
be ok.
Signed-off-by: Benjamin Gaignard
---
drivers/staging/media/hantro/hantro.h | 8 ++--
drivers/staging/media/hantro/hantro_postproc.c | 14 ++
drivers/staging/media/hantro/hantro_v4l2.c | 4
Add decode params control and it associated structure to regroup
all the information that are needed to decode a reference frame as
it is describe in ITU-T Rec. H.265 section "8.3.2 Decoding process
for reference picture set".
Adapt Cedrus driver to these changes.
Signed-off-by: Benjamin Gaignard
In order to be able to share the control hardware block between
VPUs use a syscon instead a ioremap it in the driver.
To keep the compatibility with older DT if 'nxp,imx8mq-vpu-ctrl'
phandle is not found look at 'ctrl' reg-name.
With the method it becomes useless to provide a list of register
names
Add fields and flags as they are defined in
7.4.3.3.1 "General picture parameter set RBSP semantics of the
H.265 ITU specification.
Signed-off-by: Benjamin Gaignard
---
.../userspace-api/media/v4l/ext-ctrls-codec.rst| 14 ++
include/media/hevc-ctrls.h | 4
Change hantro_codec_ops run prototype from 'void' to 'int'.
This allow to cancel the job if an error occur while configuring
the hardware.
Signed-off-by: Benjamin Gaignard
---
version 5:
- forward hantro_h264_dec_prepare_run() return value in case
of error
drivers/staging/media/hantro/hantr
Add 'nxp,imx8mq-vpu-ctrl' in the list of possible syscon.
It will used to access to the VPU control registers.
Signed-off-by: Benjamin Gaignard
Acked-by: Rob Herring
---
version 7:
- Add Rob ack
Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
Introducing G2 hevc video decoder lead to modify the bindings to allow
to get one node per VPUs.
VPUs share one hardware control block which is provided as a phandle on
an syscon.
Each node got now one reg and one interrupt.
Add a compatible for G2 hardware block: nxp,imx8mq-vpu-g2.
To be compatib
The IMX8MQ got two VPUs but until now only G1 has been enabled.
This series aim to add the second VPU (aka G2) and provide basic
HEVC decoding support.
To be able to decode HEVC it is needed to add/update some of the
structures in the uapi. In addition of them one HANTRO dedicated
control is requ
On Mon, Mar 29, 2021 at 02:43:48PM +0800, Chao Yu wrote:
...
> > > > +
> > > > +static int erofs_load_compr_cfgs(struct super_block *sb,
> > > > +struct erofs_super_block *dsb)
> > > > +{
> > > > + struct erofs_sb_info *sbi;
> > > > + struct page *page;
From: Ira Weiny
ext2_dotdot() and ext2_find_entry() both require ext2_put_page() to be
called after successful return. For some of the calls this
corresponding put was hidden in ext2_set_link and ext2_delete_entry().
Match up ext2_put_page() with ext2_dotdot() and ext2_find_entry() in the
funct
From: Ira Weiny
kmap is inefficient and can be abused so it is being phased out in favor of
kmap_local_page where possible.
ext2 uses kmap in ext2_[get|put]_page(). All of the calls to
ext2_[get|put]_page() occur in single threads so it is perfectly safe and
preferable to use kmap_local_page().
From: Ira Weiny
The k[un]map() calls in ext2_[get|put]_page() are localized to a single
thread. kmap_local_page() is more efficient.
Replace the kmap/kunmap calls with kmap_local_page()/kunmap_local().
kunmap_local() requires the mapping address so return that address from
ext2_get_page() to be
On 3/27/2021 1:20 AM, Rob Herring wrote:
The nvidia,tegra210-ahub binding is missing schema for child nodes. This
results in warnings if 'additionalProperties: false' is set (or when the
tools implement 'unevaluatedProperties' support). Add the child nodes
and reference their schema if one exi
This commit includes pinctrl driver for mt8195.
Signed-off-by: Zhiyong Tao
---
drivers/pinctrl/mediatek/Kconfig | 6 +
drivers/pinctrl/mediatek/Makefile| 1 +
drivers/pinctrl/mediatek/pinctrl-mt8195.c| 828
include/dt-bindings/pinctrl/mt8195-pinfu
The commit adds mt8195 compatible node in binding document.
Signed-off-by: Zhiyong Tao
---
.../bindings/pinctrl/pinctrl-mt8195.yaml | 152 ++
1 file changed, 152 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml
diff --git a/Do
This commit adds pinctrl device node for mt8195
Signed-off-by: Zhiyong Tao
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 068fe24efd
This patch provides the advanced drive raw data setting version
for I2C used pins on MT8195.
Signed-off-by: Zhiyong Tao
---
drivers/pinctrl/mediatek/pinctrl-mt8195.c | 22 +++
.../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 14
.../pinctrl/mediatek/pinctrl-mtk-co
This patch adds pinctrl file for mt8195.
Signed-off-by: Zhiyong Tao
---
drivers/pinctrl/mediatek/pinctrl-mtk-mt8195.h | 1669 +
1 file changed, 1669 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8195.h
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-
This patch provides rsel setting on MT8195.
Signed-off-by: Zhiyong Tao
---
drivers/pinctrl/mediatek/pinctrl-mt8195.c | 22 +++
.../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 14
.../pinctrl/mediatek/pinctrl-mtk-common-v2.h | 10 +
drivers/pinctrl/mediat
This series includes 6 patches:
1.add pinctrl file on mt8195.
2.add pinctrl binding document on mt8195.
3.add pinctrl device node on mt8195.
4.add pinctrl driver on MT8195.
5.add pinctrl drive for I2C related pins on MT8195.
6.add pinctrl rsel setting on MT8195.
Zhiyong Tao (6):
dt-bindings: pin
On Fri, Mar 26, 2021 at 04:37:49PM -0400, Lyude Paul wrote:
> As pointed out by the documentation for drm_dp_aux_register(),
> drm_dp_aux_init() should be used in situations where the AUX channel for a
> display driver can potentially be registered before it's respective DRM
> driver. This is the c
On Fri, Mar 26, 2021 at 01:50:03PM -0600, Rob Herring wrote:
> The nvidia,tegra210-ahub binding is missing schema for child nodes. This
> results in warnings if 'additionalProperties: false' is set (or when the
> tools implement 'unevaluatedProperties' support). Add the child nodes
> and reference
On Sun, Mar 28, 2021 at 06:59:38PM -0700, Brad Larson wrote:
> New drivers should include instead
> of legacy .
>
> Signed-off-by: Brad Larson
> ---
> drivers/gpio/gpio-elba-spics.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpio/gpio-elba-spics.c b/driv
On 2021/3/29 14:36, Gao Xiang wrote:
Hi Chao,
On Mon, Mar 29, 2021 at 02:26:05PM +0800, Chao Yu wrote:
On 2021/3/29 9:23, Gao Xiang wrote:
From: Gao Xiang
Add a bitmap for available compression algorithms and a variable-sized
on-disk table for compression options in preparation for upcoming
Hi Alexandru,
FYI, the error/warning still remains.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: a5e13c6df0e41702d2b2c77c8ad41677ebb065b3
commit: be24c65e9fa2486bb8ec98d9f592bdcf04bedd88 iio: adc: adi-axi-adc: add
proper Kconfig dependencies
date:
On Sun, Mar 28, 2021 at 7:08 AM Julian Braha wrote:
>
> When AD9467 is enabled, and OF is disabled,
> Kbuild gives the following warning:
>
> WARNING: unmet direct dependencies detected for ADI_AXI_ADC
> Depends on [n]: IIO [=y] && HAS_IOMEM [=y] && OF [=n]
> Selected by [y]:
> - AD9467 [=y] &&
Hi Chao,
On Mon, Mar 29, 2021 at 02:26:05PM +0800, Chao Yu wrote:
> On 2021/3/29 9:23, Gao Xiang wrote:
> > From: Gao Xiang
> >
> > Add a bitmap for available compression algorithms and a variable-sized
> > on-disk table for compression options in preparation for upcoming big
> > pcluster and LZ
On Mon, Mar 29, 2021 at 02:29:10PM +0900, Hyunsoon Kim wrote:
> This patch allows programmer to avoid zero initialization on page
> allocation even when the kernel config "CONFIG_INIT_ON_ALLOC_DEFAULT"
> is enabled. The configuration is made to prevent uninitialized
> heap memory flaws, and Android
The DCC is a DMA engine designed to store register values either in
case of a system crash or in case of software triggers manually done
by the user.Using DCC hardware and the sysfs interface of the driver
the user can exploit various functionalities of DCC.The user can specify
the register address
Documentation for Data Capture and Compare(DCC) device tree bindings
in yaml format.
Signed-off-by: Souradeep Chowdhury
---
.../devicetree/bindings/arm/msm/qcom,dcc.yaml | 49 ++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/m
Add the DCC(Data Capture and Compare) device tree node entry along with
the addresses for register regions.
Signed-off-by: Souradeep Chowdhury
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi
b/arch/arm64/bo
Added the entries for all the files added as a part of driver support for
DCC(Data Capture and Compare).
Signed-off-by: Souradeep Chowdhury
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d92f85c..fb28218 100644
--- a/MAINTAINERS
+++ b/
DCC(Data Capture and Compare) is a DMA engine designed for debugging
purposes.In case of a system
crash or manual software triggers by the user the DCC hardware stores the value
at the register
addresses which can be used for debugging purposes.The DCC driver provides the
user with sysfs
interfa
The DCC is a DMA Engine designed to capture and store data
during system crash or software triggers.The DCC operates
based on user inputs via the sysfs interface.The user gives
addresses as inputs and these addresses are stored in the
form of linkedlists.In case of a system crash or a manual
softwa
For NUMA balancing, in hint page fault handler, the faulting page will
be migrated to the accessing node if necessary. During the migration,
TLB will be shot down on all CPUs that the process has run on
recently. Because in the hint page fault handler, the PTE will be
made accessible before the m
On 2021/3/29 9:23, Gao Xiang wrote:
From: Gao Xiang
Add a bitmap for available compression algorithms and a variable-sized
on-disk table for compression options in preparation for upcoming big
pcluster and LZMA algorithm, which follows the end of super block.
To parse the compression options,
On Wed, Mar 24, 2021 at 8:49 PM Takashi Iwai wrote:
>
> On Wed, 24 Mar 2021 13:03:14 +0100,
> Ikjoon Jang wrote:
> >
> > On Wed, Mar 24, 2021, 7:16 PM Joakim Tjernlund
> >
> > wrote:
> >
> > On Wed, 2021-03-24 at 18:51 +0800, Ikjoon Jang wrote:
> > > Logitech ConferenceCam Connect is a c
Hi Kirill,
url:
https://github.com/0day-ci/linux/commits/Kirill-Kapranov/rtc-abx80x-Enable-distributed-digital-calibration/20210329-053233
base: https://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux.git
rtc-next
config: i386-randconfig-m021-20210328 (attached as .config)
compiler
On Sat, Mar 27, 2021 at 03:17:59PM -0700, Tao Ren wrote:
> On Fri, Mar 26, 2021 at 01:05:26PM +0100, Christoph Hellwig wrote:
> > On Fri, Mar 26, 2021 at 12:03:03PM +, Robin Murphy wrote:
> > > This might happen to work out, but is far from correct. Just wait until
> > > you
> > > try it on a
On Mon, Mar 29, 2021 at 04:55:25PM +1100, Stephen Rothwell wrote:
> Hi all,
>
> After merging the staging tree, today's linux-next build (x86_64
> allmodconfig) failed like this:
>
> drivers/iio/adc/ti-ads131e08.c: In function 'ads131e08_read_reg':
> drivers/iio/adc/ti-ads131e08.c:180:5: error: '
Add myself as the maintainer of the i.MX8qxp DPU DRM driver.
Signed-off-by: Liu Ying
---
v8->v9:
* No change.
v7->v8:
* No change.
v6->v7:
* No change.
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
* No change.
v2->v3:
* No change.
v1->v2:
* No change.
MAINTAINERS | 9 +
1 fi
Artificially use 'plane' and 'old_plane_state' to avoid 'not used' warning.
The precedent has already been set by other macros in the same file.
Acked-by: Daniel Vetter
Signed-off-by: Liu Ying
---
v8->v9:
* No change.
v7->v8:
* No change.
v6->v7:
* No change.
v5->v6:
* Fix commit message typo
Hi,
This is the v9 series to introduce i.MX8qm/qxp Display Processing Unit(DPU)
DRM support.
DPU is comprised of a blit engine for 2D graphics, a display controller
and a command sequencer. Outside of DPU, optional prefetch engines can
fetch data from memory prior to some DPU fetchunits of blit
This patch adds bindings for i.MX8qxp/qm Display Processing Unit.
Reviewed-by: Rob Herring
Signed-off-by: Liu Ying
---
v8->v9:
* No change.
v7->v8:
* No change.
v6->v7:
* Add Rob's R-b tag back.
v5->v6:
* Use graph schema. So, drop Rob's R-b tag as review is needed.
v4->v5:
* No change.
v3-
This patch adds bindings for i.MX8qxp/qm Display Prefetch Resolve Gasket.
Reviewed-by: Rob Herring
Signed-off-by: Liu Ying
---
v8->v9:
* No change.
v7->v8:
* No change.
v6->v7:
* No change.
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
* Improve compatible property by using enum instead
This patch adds bindings for i.MX8qxp/qm Display Prefetch Resolve Channel.
Signed-off-by: Liu Ying
---
v8->v9:
* Reference 'interrupts-extended' schema instead of 'interrupts' to require
an additional interrupt(r_rtram_stall) because the reference manual does
mention it, though the driver doe
Add support for the SMBus-Alert protocol to the STM32F7 that has
dedicated control and status logic.
If SMBus-Alert is used, the SMBALERT# pin must be configured as alternate
function for I2C Alert.
Signed-off-by: Alain Volmat
Reviewed-by: Pierre-Yves MORDRET
---
v2: - rely on st,smbus-alert b
Based on the SMBus specification, SMBus Alert active state is low.
As often on SoC, the SMBus Alert pin is not only dedicated to this
feature and can also be used for another purpose (by configuring it
as alternate function for other functions via pinctrl).
"smbus" dt-binding has been introduced r
This serie adds support for SMBus Alert on the STM32F7.
A new binding st,smbus-alert is added in order to differenciate
with the existing smbus binding.
SMBA alert control and status logic must be enabled along with
SMBALERT# pin configured via pinctrl in the device tree. This is the
rational for
This array uses 1-based indexing so it corrupts memory one element
beyond of the array. Fix it by making the array one element larger.
Fixes: dacb12877d92 ("thunderbolt: Add support for on-board retimers")
Signed-off-by: Dan Carpenter
---
drivers/thunderbolt/retimer.c | 2 +-
1 file changed, 1
After the device_register() succeeds, then the correct way to clean up
is to call device_unregister(). The unregister calls both device_del()
and device_put(). Since this code was only device_del() it results in
a memory leak.
Fixes: dacb12877d92 ("thunderbolt: Add support for on-board retimers"
On Sat, Mar 27, 2021 at 10:33:34PM +, Colin King wrote:
> From: Colin Ian King
>
> The variable force is being initialized with a value that is
> never read and it is being updated later with a new value. The
> initialization is redundant and can be removed.
>
> Addresses-Coverity: ("Unused
On 3/28/21 2:12 AM, Rob Herring wrote:
>> +
>> + led-gpios:
>> +description: Array of one or more GPIOs pins used to control the LED.
>> +minItems: 1
>> +maxItems: 8 # Should be enough
>> +
>> + led-states:
>> +description: |
>> + The array list the supported states here whi
On 3/26/21 9:49 PM, Pavel Machek wrote:
>> +of_property_read_string(node, "default-state", &state);
>> +if (!strcmp(state, "on"))
>> +multi_gpio_led_set(&priv->cdev, priv->cdev.max_brightness);
>> +else
>> +multi_gpio_led_set(&priv->cdev, 0);
> No need for defaul
From: Hermes Zhang
Introduce a new multiple GPIOs LED driver. This LED will made of
multiple GPIOs (up to 8) and will map different brightness to different
GPIOs states which defined in dts file.
Signed-off-by: Hermes Zhang
---
Notes:
changes v3:
- Remove LEDS_SIMPLE menu
- Minro c
On Mon, Mar 29, 2021 at 02:55:07AM +0300, Dmitry Osipenko wrote:
> Drop unnecessary zero-checking of ABS_MT_TOUCH_MAJOR resolution since
> there is no difference between setting resolution to 0 vs not setting
> it at all. This change makes code cleaner a tad.
>
> Suggested-by: Dmitry Torokhov
> S
On Fri, Mar 26, 2021 at 01:18:36PM -0700, Song Liu wrote:
> On Fri, Mar 26, 2021 at 12:45 PM Colin King wrote:
> >
> > From: Colin Ian King
> >
> > The variable id is being assigned a value that is never
> > read, the assignment is redundant and can be removed.
> >
> > Addresses-Coverity: ("Unuse
Hi Andy,
Thanks for the review.
On 26-Mar-21 16:10, Andy Shevchenko wrote:
> [CAUTION: External Email]
>
> On Fri, Mar 26, 2021 at 03:53:34PM +0530, Goswami, Sanket wrote:
>> On 25-Mar-21 22:35, Andy Shevchenko wrote:
>>> On Mon, Mar 22, 2021 at 10:26:55PM +0530, Goswami, Sanket wrote:
On 0
Hi all,
After merging the staging tree, today's linux-next build (x86_64
allmodconfig) failed like this:
drivers/iio/adc/ti-ads131e08.c: In function 'ads131e08_read_reg':
drivers/iio/adc/ti-ads131e08.c:180:5: error: 'struct spi_transfer' has no
member named 'delay_usecs'
180 |.delay_usecs
On 07:29 Mon 29 Mar 2021, Christoph Hellwig wrote:
I really don't think these typo patchbomb are that useful. I'm all
for fixing typos when working with a subsystem, but I'm not sure these
patchbombs help anything.
I am sure you are holding the wrong end of the wand and grossly failing to
unde
Hi Pierre,
On 3/26/21 11:59 PM, Pierre-Louis Bossart wrote:
> cppcheck warning:
>
> sound/soc/ti/omap-mcbsp.c:379:11: style: The if condition is the same
> as the previous if condition [duplicateCondition]
>
> if (mcbsp->irq) {
> ^
> sound/soc/ti/omap-mcbsp.c:376:11: note: First condi
On 22:38 Sun 28 Mar 2021, Max Filippov wrote:
On Sun, Mar 28, 2021 at 10:37 PM Max Filippov wrote:
On Sun, Mar 28, 2021 at 10:18 PM Bhaskar Chowdhury
wrote:
>
> s/controlers/controllers/
>
> Signed-off-by: Bhaskar Chowdhury
> ---
> Documentation/xtensa/atomctl.rst | 2 +-
> 1 file changed,
On 3/26/21 11:59 PM, Pierre-Louis Bossart wrote:
> cppcheck warning:
>
> sound/soc/ti/omap-abe-twl6040.c:173:10: style: Variable 'ret' is
> assigned a value that is never used. [unreadVariable]
> int ret = 0;
> ^
Thanks,
Acked-by: Peter Ujfalusi
>
> Signed-off-by: Pierre-Louis Bos
For the same purpose, the leagcy intel_pmu_lbr_is_compatible() could be
renamed for reuse by more callers for the same purpose and remove the
comment about LBR use case incidentally.
Signed-off-by: Like Xu
---
arch/x86/kvm/cpuid.h | 5 +
arch/x86/kvm/vmx/pmu_intel.c | 12 +-
The CPUID features PDCM, DS and DTES64 are required for PEBS feature.
KVM would expose CPUID feature PDCM, DS and DTES64 to guest when PEBS
is supported in the KVM on the Ice Lake server platforms.
Originally-by: Andi Kleen
Co-developed-by: Kan Liang
Signed-off-by: Kan Liang
Co-developed-by: Lu
The information obtained from the interface perf_get_x86_pmu_capability()
doesn't change, so an exported "struct x86_pmu_capability" is introduced
for all guests in the KVM, and it's initialized before hardware_setup().
Signed-off-by: Like Xu
---
arch/x86/kvm/cpuid.c | 24 +++
It allows this inline function to be reused by more callers in
more files, such as pmu_intel.c.
Signed-off-by: Like Xu
---
arch/x86/kvm/pmu.c | 11 ---
arch/x86/kvm/pmu.h | 11 +++
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/
The guest PEBS will be disabled when some users try to perf KVM and
its user-space through the same PEBS facility OR when the host perf
doesn't schedule the guest PEBS counter in a one-to-one mapping manner
(neither of these are typical scenarios).
The PEBS records in the guest DS buffer is still
The bit 12 represents "Processor Event Based Sampling Unavailable (RO)" :
1 = PEBS is not supported.
0 = PEBS is supported.
A write to this PEBS_UNAVL available bit will bring #GP(0) when guest PEBS
is enabled. Some PEBS drivers in guest may care about this bit.
Signed-off-by: Lik
If IA32_PERF_CAPABILITIES.PEBS_BASELINE [bit 14] is set, the adaptive
PEBS is supported. The PEBS_DATA_CFG MSR and adaptive record enable
bits (IA32_PERFEVTSELx.Adaptive_Record and IA32_FIXED_CTR_CTRL.
FCx_Adaptive_Record) are also supported.
Adaptive PEBS provides software the capability to confi
The PEBS-PDIR facility on Ice Lake server is supported on IA31_FIXED0 only.
If the guest configures counter 32 and PEBS is enabled, the PEBS-PDIR
facility is supposed to be used, in which case KVM adjusts attr.precise_ip
to 3 and request host perf to assign the exactly requested counter or fail.
T
When CPUID.01H:EDX.DS[21] is set, the IA32_DS_AREA MSR exists and
points to the linear address of the first byte of the DS buffer
management area, which is used to manage the PEBS records.
When guest PEBS is enabled and the value is different from the
host, KVM will add the IA32_DS_AREA MSR to the
When a guest counter is configured as a PEBS counter through
IA32_PEBS_ENABLE, a guest PEBS event will be reprogrammed by
configuring a non-zero precision level in the perf_event_attr.
The guest PEBS overflow PMI bit would be set in the guest
GLOBAL_STATUS MSR when PEBS facility generates a PEBS
o
The mask value of fixed counter control register should be dynamic
adjusted with the number of fixed counters. This patch introduces a
variable that includes the reserved bits of fixed counter control
registers. This is needed for later Ice Lake fixed counter changes.
Co-developed-by: Luwei Kang
If IA32_PERF_CAPABILITIES.PEBS_BASELINE [bit 14] is set, the
IA32_PEBS_ENABLE MSR exists and all architecturally enumerated fixed
and general purpose counters have corresponding bits in IA32_PEBS_ENABLE
that enable generation of PEBS records. The general-purpose counter bits
start at bit IA32_PEBS_
On Intel platforms, software may uses IA32_MISC_ENABLE[7]
bit to detect whether the performance monitoring facility
is supported in the processor.
It's dependent on the PMU being enabled for the guest and
a write to this PMU available bit will be ignored.
Cc: Yao Yuan
Signed-off-by: Like Xu
---
The guest Precise Event Based Sampling (PEBS) feature can provide
an architectural state of the instruction executed after the guest
instruction that exactly caused the event. It needs new hardware
facility only available on Intel Ice Lake Server platforms. This
patch set enables the basic PEBS via
Splitting the logic for determining the guest values is unnecessarily
confusing, and potentially fragile. Perf should have full knowledge and
control of what values are loaded for the guest.
If we change .guest_get_msrs() to take a struct kvm_pmu pointer, then it
can generate the full set of guest
With PEBS virtualization, the guest PEBS records get delivered to the
guest DS, and the host pmi handler uses perf_guest_cbs->is_in_guest()
to distinguish whether the PMI comes from the guest code like Intel PT.
No matter how many guest PEBS counters are overflowed, only triggering
one fake event
The new hardware facility supporting guest PEBS is only available
on Intel Ice Lake Server platforms for now. KVM will check this field
through perf_get_x86_pmu_capability() instead of hard coding the cpu
models in the KVM code. If it is supported, the guest PBES capability
will be exposed to the g
On Sun, Mar 28, 2021 at 10:18 PM Bhaskar Chowdhury
wrote:
>
> s/controlers/controllers/
>
> Signed-off-by: Bhaskar Chowdhury
> ---
> Documentation/xtensa/atomctl.rst | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/xtensa/atomctl.rst
> b/Documentation/xtens
Hi all,
Today's linux-next merge of the staging tree got a conflict in:
drivers/iio/common/scmi_sensors/scmi_iio.c
between commit:
fc91d6b6f0ba ("iio/scmi: port driver to the new scmi_sensor_proto_ops
interface")
from the scmi tree and commit:
1b33dfa5d5f1 ("Merge remote-tracking branc
Hi folks,
The following shows the latest progress of EROFS big pcluster feature
for the upcoming 5.13, note that big pcluster also enables inplace
decompression to minimize extra page allocation and cache thrashing.
Kernel: Linux 5.10-rc5
Testsuite: erofs-openbenchmark
Testdata: enwik9 (1
This patch allows programmer to avoid zero initialization on page
allocation even when the kernel config "CONFIG_INIT_ON_ALLOC_DEFAULT"
is enabled. The configuration is made to prevent uninitialized
heap memory flaws, and Android has applied this for security and
deterministic execution times. Plea
On Mon, Mar 29, 2021 at 12:55:15PM +1100, Alistair Popple wrote:
> On Friday, 26 March 2021 4:15:36 PM AEDT Balbir Singh wrote:
> > On Fri, Mar 26, 2021 at 12:20:35PM +1100, Alistair Popple wrote:
> > > +static int __region_intersects(resource_size_t start, size_t size,
> > > +
On Sun, Mar 28, 2021 at 10:37 PM Max Filippov wrote:
>
> On Sun, Mar 28, 2021 at 10:18 PM Bhaskar Chowdhury
> wrote:
> >
> > s/controlers/controllers/
> >
> > Signed-off-by: Bhaskar Chowdhury
> > ---
> > Documentation/xtensa/atomctl.rst | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
There are code paths that rely on zero_pfn to be fully initialized
before core_initcall. For example, wq_sysfs_init() is a core_initcall
function that eventually results in a call to kernel_execve, which
causes a page fault with a subsequent mmput. If zero_pfn is not
initialized by then it may not
Broadcast device is switched to oneshot mode in
hrtimer_switch_to_hres() -> tick_broadcast_switch_to_oneshot().
After high resolution timers are enabled, new installed
broadcast device has no chance to switch mode.
This issue happens in below situation:
In order to make broadcast clock source driv
I really don't think these typo patchbomb are that useful. I'm all
for fixing typos when working with a subsystem, but I'm not sure these
patchbombs help anything.
On Mon, Mar 29, 2021 at 05:22:56AM +0530, Bhaskar Chowdhury wrote:
> This patch series fixes some trivial and rudimentary spellings i
There are code paths that rely on zero_pfn to be fully initialized
before core_initcall. For example, wq_sysfs_init() is a core_initcall
function that eventually results in a call to kernel_execve, which
causes a page fault with a subsequent mmput. If zero_pfn is not
initialized by then it may not
On some platforms, the root port for Intel XMM7360 WWAN supports D3cold.
When the root port is put to D3cold by system suspend or runtime
suspend, attempt to systems resume or runtime resume will freeze the
laptop for a while, then it automatically shuts down.
The root cause is unclear for now, as
s/assymetry/asymmetry/
Signed-off-by: Bhaskar Chowdhury
---
Documentation/scheduler/sched-nice-design.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/scheduler/sched-nice-design.rst
b/Documentation/scheduler/sched-nice-design.rst
index 0571f1b47e64..3511d86
s/enhancments/enhancements/
Signed-off-by: Bhaskar Chowdhury
---
Documentation/openrisc/openrisc_port.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/openrisc/openrisc_port.rst
b/Documentation/openrisc/openrisc_port.rst
index 657ac4af7be6..b3c6c5e258b0 1006
s/resonable/reasonable/
Signed-off-by: Bhaskar Chowdhury
---
Documentation/riscv/pmu.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/riscv/pmu.rst b/Documentation/riscv/pmu.rst
index acb216b99c26..fde31b6aa861 100644
--- a/Documentation/riscv/pmu.rst
+++ b/D
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