t; TASK_SIZE to FIXADDR_START. We also move FIXADDR_TOP, FIXADDR_SIZE,
> and FIXADDR_START defines to asm/pgtable.h so that we can avoid
> cyclic
> header includes.
>
> Signed-off-by: Anup Patel
This fixes the RV32 issue.
Tested-by: Alistair Francis
Alistair
> ---
On Thu, 2019-08-15 at 13:29 -0700, Paul Walmsley wrote:
> On Thu, 15 Aug 2019, David Abdurachmanov wrote:
>
> > Yes, I do see those in Fedora/RISCV build farm every morning, but
> > with
> > riscv64 and 5.2.0-rc7 kernel.
>
> [...]
>
> > fedora-riscv-4 login: [178876.406122] Unable to handle
On Thu, 2019-08-15 at 12:07 -0700, David Abdurachmanov wrote:
> On Thu, Aug 15, 2019 at 11:57 AM Alistair Francis
> wrote:
> > On Wed, 2019-07-10 at 17:05 -0700, Paul Walmsley wrote:
> > > On Fri, 7 Jun 2019, Anup Patel wrote:
> > >
> > > > Currently, th
On Wed, 2019-07-10 at 17:05 -0700, Paul Walmsley wrote:
> On Fri, 7 Jun 2019, Anup Patel wrote:
>
> > Currently, the setup_vm() does initial page table setup in one-shot
> > very early before enabling MMU. Due to this, the setup_vm() has to
> > map
> > all possible kernel virtual addresses since
Update the defconfig:
- Add CONFIG_HW_RANDOM=y and CONFIG_HW_RANDOM_VIRTIO=y to enable
VirtIORNG when running on QEMU
Signed-off-by: Alistair Francis
---
arch/riscv/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs
Update the rv32_defconfig:
- Add 'CONFIG_DEVTMPFS_MOUNT=y' to match the RISC-V defconfig
- Add CONFIG_HW_RANDOM=y and CONFIG_HW_RANDOM_VIRTIO=y to enable
VirtIORNG when running on QEMU
Signed-off-by: Alistair Francis
---
arch/riscv/configs/rv32_defconfig | 3 +++
1 file changed, 3
On Tue, Aug 13, 2019 at 12:41 PM Arnd Bergmann wrote:
>
> On Tue, Aug 13, 2019 at 9:01 PM Alistair Francis wrote:
> > On Mon, Aug 12, 2019 at 2:49 AM Arnd Bergmann wrote:
>
> > > > diff --git a/include/linux/syscalls.h b/include/linux/syscalls.h
> > > >
On Mon, Aug 12, 2019 at 2:49 AM Arnd Bergmann wrote:
>
> On Sat, Aug 10, 2019 at 3:11 AM Alistair Francis
> wrote:
> >
> > Update the #defines around sys_fstat64() and sys_fstatat64() to match
> > the #defines around the __NR3264_fstatat and __NR3264_fstat definiti
On Sun, Aug 11, 2019 at 5:00 PM Andy Lutomirski wrote:
>
> On Fri, Aug 9, 2019 at 6:11 PM Alistair Francis
> wrote:
> >
> > Update the #defines around sys_fstat64() and sys_fstatat64() to match
> > the #defines around the __NR3264_fstatat and __NR3264_fstat definiti
Update the #defines around sys_fstat64() and sys_fstatat64() to match
the #defines around the __NR3264_fstatat and __NR3264_fstat definitions
in include/uapi/asm-generic/unistd.h. This avoids compiler failures if
one is defined.
Signed-off-by: Alistair Francis
---
include/linux/syscalls.h | 2
Re-run savedefconfig to cleanup the defconfig.
Signed-off-by: Alistair Francis
---
arch/arm64/configs/defconfig | 24 ++--
1 file changed, 6 insertions(+), 18 deletions(-)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 0e58ef02880c
Enable the sound drivers for Allwinner devices.
Signed-off-by: Alistair Francis
---
arch/arm64/configs/defconfig | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index b17ed20e1754..3dc12c3b9bf8 100644
--- a/arch/arm64/configs
On Thu, Jul 4, 2019 at 2:19 AM Arnd Bergmann wrote:
>
> On Thu, Jul 4, 2019 at 9:20 AM Andreas Schwab wrote:
> >
> > On Jul 03 2019, Alistair Francis wrote:
> >
> > > On Wed, Jul 3, 2019 at 12:08 AM Andreas Schwab wrote:
> > >>
&
On Thu, Jul 11, 2019 at 4:01 AM Robin Murphy wrote:
>
> Hi Alistair,
>
> On 10/07/2019 23:27, Alistair Francis wrote:
> > On Thu, Feb 28, 2019 at 2:42 PM Robin Murphy wrote:
> >>
> >> On 2019-02-28 10:33 pm, Alistair Fran
On Thu, Feb 28, 2019 at 2:42 PM Robin Murphy wrote:
>
> On 2019-02-28 10:33 pm, Alistair Francis wrote:
> > This reverts commit 6778be4e520959659b27a441c06a84c9cb009085.
> >
> > Reverting the commit fixes these error messages and an non-functioning
> > USB bus whe
On Thu, Jul 4, 2019 at 1:34 AM Arnd Bergmann wrote:
>
> On Thu, Jul 4, 2019 at 12:18 AM Alistair Francis wrote:
> > On Wed, Jul 3, 2019 at 12:47 PM Arnd Bergmann wrote:
> > > On Wed, Jul 3, 2019 at 8:45 PM Alistair Francis
> > > wrote:
> > >
On Wed, Jul 3, 2019 at 12:47 PM Arnd Bergmann wrote:
>
> On Wed, Jul 3, 2019 at 8:45 PM Alistair Francis wrote:
> >
> > On Wed, Jul 3, 2019 at 1:41 AM Arnd Bergmann wrote:
> > >
> > > On Wed, Jul 3, 2019 at 2:21 AM Alistair Francis
> > > wr
On Wed, Jul 3, 2019 at 1:41 AM Arnd Bergmann wrote:
>
> On Wed, Jul 3, 2019 at 2:21 AM Alistair Francis
> wrote:
> >
> > The glibc implementation of siginfo_t results in an allignment of 8 bytes
> > for the union _sifields on RV32. The kernel has an allignment of 4
On Wed, Jul 3, 2019 at 12:08 AM Andreas Schwab wrote:
>
> On Jul 02 2019, Alistair Francis wrote:
>
> > In the RISC-V 32-bit glibc port [1] the siginfo_t struct in the kernel
> > doesn't line up with the struct in glibc. In glibc world the _sifields
> > union is 8 byte
-by: Alistair Francis
---
include/uapi/asm-generic/siginfo.h | 32 --
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/include/uapi/asm-generic/siginfo.h
b/include/uapi/asm-generic/siginfo.h
index cb3d6c267181..09b0a1abac14 100644
--- a/include/uapi/asm-generic
to the struct to avoid allignment
mismatches.
Signed-off-by: Alistair Francis
---
arch/riscv/include/uapi/asm/siginfo.h | 32 +++
1 file changed, 32 insertions(+)
create mode 100644 arch/riscv/include/uapi/asm/siginfo.h
diff --git a/arch/riscv/include/uapi/asm/siginfo.h
b/arch
/commits/alistair/rv32.next
Alistair Francis (2):
uapi/asm-generic: Allow defining a custom __SIGINFO struct
riscv/include/uapi: Define a custom __SIGINFO struct for RV32
arch/riscv/include/uapi/asm/siginfo.h | 32 +++
include/uapi/asm-generic/siginfo.h| 32
-by: Alistair Francis
---
include/uapi/asm-generic/siginfo.h | 32 --
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/include/uapi/asm-generic/siginfo.h
b/include/uapi/asm-generic/siginfo.h
index cb3d6c267181..09b0a1abac14 100644
--- a/include/uapi/asm-generic
being lost in the waitid syscall.
This doesn't seem to be a great fix, but it is somewhat similar to what
x32 does (which has 64-bit time_t like RV32) and I can't figure out why
the two allignments are different.
1: https://github.com/alistair23/glibc/commits/alistair/rv32.next
Alistair Francis (2
to the struct to avoid allignment
mismatches.
Signed-off-by: Alistair Francis
---
arch/riscv/include/uapi/asm/siginfo.h | 32 +++
1 file changed, 32 insertions(+)
create mode 100644 arch/riscv/include/uapi/asm/siginfo.h
diff --git a/arch/riscv/include/uapi/asm/siginfo.h
b/arch
On Mon, 2019-06-17 at 20:26 -0700, Paul Walmsley wrote:
> On Mon, 17 Jun 2019, Alistair Francis wrote:
>
> > > The legacy M-mode U-boot handles the phy reset already, and I’ve
> > > been
> > > able to load upstream S-mode uboot as a payload via TFTP, and
>
On Mon, 2019-06-17 at 09:14 -0500, Troy Benjegerdes wrote:
> > On Jun 17, 2019, at 6:34 AM, Paul Walmsley <
> > paul.walms...@sifive.com> wrote:
> >
> > On Mon, 17 Jun 2019, Andreas Schwab wrote:
> >
> > > On Jun 17 2019, Paul Walmsley wrote:
> > >
> > > > On Mon, 17 Jun 2019, Andreas Schwab
On Mon, 2019-03-25 at 19:22 -0700, Palmer Dabbelt wrote:
> On Mon, 25 Mar 2019 00:01:45 PDT (-0700), a...@brainfault.org wrote:
> > On Mon, Mar 25, 2019 at 12:18 PM Christoph Hellwig <
> > h...@infradead.org> wrote:
> > > On Mon, Mar 25, 2019 at 01:25:50PM +0800, Alan Kao wrote:
> > > > Hi Anup,
>
On Fri, Mar 22, 2019 at 6:27 AM Christoph Hellwig wrote:
>
> On Wed, Mar 20, 2019 at 05:04:58PM -0700, Alistair Francis wrote:
> > > Well, it starts at 0x00, but the first one is reserved. If you think
> > > that is too confusing I'd rather throw in a comment explainin
On Wed, Mar 20, 2019 at 4:49 PM Christoph Hellwig wrote:
>
> On Wed, Mar 20, 2019 at 10:39:52PM +, Alistair Francis wrote:
> > According to the FU540 and E31 manuals the PLIC source priority
> > address starts at an offset of 0x04 and not 0x00. To aviod confusion
>
According to the FU540 and E31 manuals the PLIC source priority
address starts at an offset of 0x04 and not 0x00. To aviod confusion
update the address and source offset to match the documentation. This
causes no difference in functionality.
Signed-off-by: Alistair Francis
---
drivers/irqchip
On Thu, Feb 28, 2019 at 2:39 PM Paul Walmsley wrote:
>
> Hello Alistair,
>
> On Thu, 28 Feb 2019, Alistair Francis wrote:
>
> > This reverts commit 6778be4e520959659b27a441c06a84c9cb009085.
> >
> > Reverting the commit fixes these error messages and an non-funct
:03:00.0: startup error -19
xhci_hcd :03:00.0: USB bus 2 deregistered
xhci_hcd :03:00.0: WARNING: Host System Error
xhci_hcd :03:00.0: remove, state 1
Signed-off-by: Alistair Francis
---
I'm not sure if this is the correct fix, it's possible something else is
wrong, but I
On Thu, Feb 21, 2019 at 9:37 PM kra...@redhat.com wrote:
>
> On Thu, Feb 21, 2019 at 10:44:06AM -0800, Alistair Francis wrote:
> > On Thu, Feb 21, 2019 at 3:52 AM kra...@redhat.com wrote:
> > >
> > > On Thu, Feb 21, 2019 at 12:33:03AM +, Alistair Francis wrot
On Thu, Feb 21, 2019 at 3:52 AM kra...@redhat.com wrote:
>
> On Thu, Feb 21, 2019 at 12:33:03AM +, Alistair Francis wrote:
> > When running RISC-V QEMU with the Bochs device attached via PCIe the
> > probe of the Bochs device fails with:
> > [drm:bochs_hw_i
() is called before
bochs_load().
Signed-off-by: Alistair Francis
Reported-by: David Abdurachmanov
---
drivers/gpu/drm/bochs/bochs_drv.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/bochs/bochs_drv.c
b/drivers/gpu/drm/bochs/bochs_drv.c
index f3dd66ae990a..aa35007262cd 100644
On Thu, Feb 7, 2019 at 3:04 PM David Abdurachmanov
wrote:
>
> On Thu, Feb 7, 2019 at 11:56 PM Alistair Francis
> wrote:
> >
> > To fix systemd/sysVinit crashes enable __ARCH_WANT_STAT64.
> >
> > systemd failed to start with this error for 32-bit RISC-V:
> >
]---
sysVinit had a similar problem as well. By enabling __ARCH_WANT_STAT64
for 32-bit RISC-V the problem disapears and 32-bit RISC-V is able to
boot.
Signed-off-by: Alistair Francis
---
This was tested with this fork of glibc to enable 32-bit RISC-V support:
https://github.com/riscv/riscv-glibc
On Tue, 2019-01-15 at 07:26 -0800, Christoph Hellwig wrote:
> On Sat, Jan 12, 2019 at 12:41:26AM +0000, Alistair Francis wrote:
> > Enable generic PCIe by default in the RISC-V defconfig, this allows
> > us
> > to use QEMU's PCIe support out of the box.
> >
> >
Enable generic PCIe by default in the RISC-V defconfig, this allows us
to use QEMU's PCIe support out of the box.
Signed-off-by: Alistair Francis
---
arch/riscv/configs/defconfig | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv
On Sat, 2019-01-12 at 00:03 +, Alistair Francis wrote:
> Enable generic PCIe by default in the RISC-V defconfig, this allows
> us
> to use QEMU's PCIe support out of the box.
>
> Signed-off-by: Alistair Francis
> ---
> arch/riscv/configs/defconfig | 5 +++--
> 1 fi
Enable generic PCIe by default in the RISC-V defconfig, this allows us
to use QEMU's PCIe support out of the box.
Signed-off-by: Alistair Francis
---
arch/riscv/configs/defconfig | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv
Enable generic PCIe by default in the RISC-V defconfig, this allows us
to use QEMU's PCIe support out of the box.
Signed-off-by: Alistair Francis
---
arch/riscv/configs/defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
On Fri, 2018-12-21 at 14:34 -0800, Paul Walmsley wrote:
>
> On Fri, 21 Dec 2018, Alistair Francis wrote:
>
> > On Fri, 2018-12-21 at 11:27 -0800, Paul Walmsley wrote:
> > > On Fri, 21 Dec 2018, Alistair Francis wrote:
> > >
> > > > When the
On Fri, 2018-12-21 at 11:27 -0800, Paul Walmsley wrote:
> On Fri, 21 Dec 2018, Alistair Francis wrote:
>
> > When the MicroSemi driver does eventually go upstream this will
> > probably have to be discussed though as either the config or device
> > tree will need to be e
Enable generic PCIe by default in the RISC-V defconfig, this allows us
to use QEMU's PCIe support out of the box.
Signed-off-by: Alistair Francis
---
v2:
- Keep the Xilinx PCIE enabled
arch/riscv/configs/defconfig | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/riscv/configs
On Fri, 2018-12-21 at 11:13 -0800, Paul Walmsley wrote:
> Hello Alistair,
>
> On Fri, 21 Dec 2018, Alistair Francis wrote:
>
> > Enable generic PCIe by default in the RISC-V defconfig, this allows
> > us
> > to use QEMU's PCIe support out of the box. Also remove t
Enable generic PCIe by default in the RISC-V defconfig, this allows us
to use QEMU's PCIe support out of the box. Also remove the Xilinx PCIe
support by default as this is rarely used and conflicts with the more
commonly used (out of tree) MicroSemi PCIe root complex.
Signed-off-by: Alistair
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