.
Antoine
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Hi Sebastian,
On 13/03/2014 10:51, Sebastian Hesselbarth wrote:
On 03/12/2014 11:35 AM, Alexandre Belloni wrote:
On 12/03/2014 at 12:06:02 +0100, Antoine Ténart wrote :
This serie adds the initial support for the Marvell BG2-Q DMP (part
of the
Berlin family). SoC has nodes for cpu, l2 cache
Adds initial support for the Marvell Armada 1500 pro (BG2Q) SoC (Berlin family).
The SoC has nodes for cpu, l2 cache controller, interrupt controllers, local
timer, apb timers and uarts for now.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
Signed-off-by: Alexandre Belloni
Adds basic informations about the Armada 1500 Pro in the Berlin family of the
Marvell ARM SoC documentation and the Armada 1500 Pro SoC compatible in the
related device tree documentation.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
Documentation/arm/Marvell/README
Adds initial support for the Marvell BG2-Q DMP. The board has 2GB of
memory, an uart activated and what's initially supported by the Marvell
Armada 1500 pro dtsi.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/boot/dts/Makefile | 3 ++-
arch/arm
- moved documentation changes into a single patch
- fixed documentation typo
Antoine Ténart (3):
ARM: dts: berlin2q: add the Marvell Armada 1500 pro
ARM: berlin2q: add the Marvell Armada 1500 pro in the documentation
ARM: dts: berlin2q: add the Marvell BG2-Q DMP device tree
Sebastian,
On 14/03/2014 10:31, Sebastian Hesselbarth wrote:
On 03/13/2014 03:06 PM, Antoine Ténart wrote:
+clocks {
+#address-cells = 0;
+#size-cells = 0;
+
+smclk: sysmgr-clock {
+compatible = fixed-clock;
+#clock-cells = 0
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
Documentation/arm/Marvell/README | 5 +
Documentation/devicetree/bindings/arm/marvell,berlin.txt | 1 +
2 files changed, 6 insertions(+)
diff --git a/Documentation/arm/Marvell/README b/Documentation
Adds initial support for the Marvell Armada 1500 pro (BG2Q) SoC (Berlin family).
The SoC has nodes for cpu, l2 cache controller, interrupt controllers, local
timer, apb timers and uarts for now.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
Signed-off-by: Alexandre Belloni
size
- added more information in commit logs
- shorted nodes by address
- fixed clocks cells config
- renamed the Marvell BG2-Q DMP device tree
- moved documentation changes into a single patch
- fixed documentation typo
Antoine Ténart (3):
ARM: dts
Adds initial support for the Marvell BG2-Q DMP. The board has 2GB of
memory, an uart activated and what's initially supported by the Marvell
Armada 1500 pro dtsi.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/boot/dts/Makefile | 3 ++-
arch/arm
name it as twdclk to avoid confusion? On Berlin, sysclk is
another
clk rather than the clk for twd.
Sure, I'll change the name and send a v4.
Antoine
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Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Adds initial support for the Marvell BG2-Q DMP. The board has 2GB of
memory, an uart activated and what's initially supported by the Marvell
Armada 1500 pro dtsi.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/boot/dts/Makefile | 3 ++-
arch/arm
Adds initial support for the Marvell Armada 1500 pro (BG2Q) SoC (Berlin family).
The SoC has nodes for cpu, l2 cache controller, interrupt controllers, local
timer, apb timers and uarts for now.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
Signed-off-by: Alexandre Belloni
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
Documentation/arm/Marvell/README | 5 +
Documentation/devicetree/bindings/arm/marvell,berlin.txt | 1 +
2 files changed, 6 insertions(+)
diff --git a/Documentation/arm/Marvell/README b/Documentation
in commit logs
- shorted nodes by address
- fixed clocks cells config
- renamed the Marvell BG2-Q DMP device tree
- moved documentation changes into a single patch
- fixed documentation typo
Antoine Ténart (3):
ARM: dts: berlin2q: add the Marvell Armada 1500 pro
This serie adds the initial support for the Marvell BG2-Q DMP (part of the
Berlin family). SoC has nodes for cpu, l2 cache controller, interrupt
controllers, local timer, apb timers and uarts for now.
Homepage: http://www.marvell.com/digital-entertainment/armada-1500-pro/
Antoine Ténart (2
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/boot/dts/Makefile | 3 ++-
arch/arm/boot/dts/berlin2q-dmp.dts | 32
2 files changed, 34 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/berlin2q-dmp.dts
diff
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
Signed-off-by: Alexandre Belloni alexandre.bell...@free-electrons.com
---
Documentation/arm/Marvell/README | 5 +
.../devicetree/bindings/arm/marvell,berlin.txt | 1 +
arch/arm/boot/dts/berlin2q.dtsi
On 12/03/2014 12:20, Arnd Bergmann wrote:
On Wednesday 12 March 2014 12:06:04 Antoine Ténart wrote:
+
+ soc {
+ apb@fc {
+ uart0: uart@9000 {
+ status = okay
sebastian.hesselba...@gmail.com
Acked-by: Antoine Ténart antoine.ten...@free-electrons.com
Also tested on the BG2Q,
Tested-by: Antoine Ténart antoine.ten...@free-electrons.com
---
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Ian Campbell
.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Acked-by: Antoine Ténart antoine.ten...@free-electrons.com
Also tested on the BG2Q,
Tested-by: Antoine Ténart antoine.ten...@free-electrons.com
---
Cc: Russell King li...@arm.linux.org.uk
Cc: Antoine Tenart antoine.ten...@free
Enable the 2 available USB PHY and USB nodes on the Marvell Berlin BG2Q
DMP.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/berlin2q-marvell
The Marvell Berlin SoCs now has a reset controller. Add the needed
configuration.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/mach-berlin/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-berlin/Kconfig b/arch/arm/mach-berlin/Kconfig
Adds nodes describing the Marvell Berlin BG2Q USB PHY and USB. The BG2Q
SoC has 3 USB host controller, compatible with ChipIdea.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/boot/dts/berlin2q.dtsi | 51 +
1 file changed, 51
only on the BG2Q and are
compatible with USB ChipIdea. We here add a glue to use the available
common functions for this kind of controllers. A USB PHY driver is also
added to control the PHY.
Antoine Ténart (9):
reset: add the Berlin reset controller driver
ARM: Berlin: select the reset
The Marvell Berlin USB controllers are compatible with ChipIdea. Add a
driver using the ChipIdea common functions to support them.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
drivers/usb/chipidea/Makefile | 1 +
drivers/usb/chipidea/ci_hdrc_berlin.c | 108
Document the Marvell Berlin USB driver bindings.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
.../devicetree/bindings/usb/ci-hdrc-berlin.txt | 18 ++
1 file changed, 18 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/ci-hdrc
Add a reset controller for Marvell Berlin SoCs which is used by the
USB PHYs drivers (for now).
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
drivers/reset/Makefile | 1 +
drivers/reset/reset-berlin.c | 113 +++
2 files
Document the bindings of the Marvell Berlin USB PHY driver.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
.../devicetree/bindings/usb/berlin-usbphy.txt | 18 ++
1 file changed, 18 insertions(+)
create mode 100644 Documentation/devicetree/bindings
The chip controller node now also describes the Marvell Berlin reset
controller. Add the required 'reset-cells' property.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/boot/dts/berlin2.dtsi | 1 +
arch/arm/boot/dts/berlin2cd.dtsi | 1 +
arch/arm/boot/dts
Add the driver driving the Marvell Berlin USB PHY. This allows to
initialize the PHY and to use it from the USB driver later.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
drivers/usb/phy/Kconfig | 9 ++
drivers/usb/phy/Makefile | 1 +
drivers/usb/phy
On Thu, Jun 05, 2014 at 06:39:07PM +0200, Philipp Zabel wrote:
Am Donnerstag, den 05.06.2014, 17:48 +0200 schrieb Antoine Ténart:
The chip controller node now also describes the Marvell Berlin reset
controller. Add the required 'reset-cells' property.
Signed-off-by: Antoine Ténart
.
The reg property is shared between drivers using the common chip
controller node. I do not know how many registers are actually used
to reset.
We then could hardcode the size, with the registers actually used here?
Thanks for the review!
Antoine
--
Antoine Ténart, Free Electrons
Embedded Linux
Hi,
On Fri, Jun 06, 2014 at 12:09:06PM +0530, Vivek Gautam wrote:
On Thu, Jun 5, 2014 at 9:18 PM, Antoine Ténart
antoine.ten...@free-electrons.com wrote:
Add the driver driving the Marvell Berlin USB PHY. This allows to
initialize the PHY and to use it from the USB driver later.
Just out
Sebastian,
On Fri, Jun 06, 2014 at 12:54:06PM +0200, Sebastian Hesselbarth wrote:
On 06/05/2014 05:48 PM, Antoine Ténart wrote:
+
+#include linux/gpio.h
+#include linux/io.h
+#include linux/module.h
+#include linux/of_gpio.h
+#include linux/usb/phy.h
+#include linux/platform_device.h
Sebastian,
On Fri, Jun 06, 2014 at 12:55:54PM +0200, Sebastian Hesselbarth wrote:
On 06/05/2014 05:48 PM, Antoine Ténart wrote:
+
+static const struct of_device_id ci_hdrc_berlin_of_match[] = {
+{ .compatible = marvell,berlin-usb },
Looking at the driver, I can see no Berlin-specific
Hi all,
On Mon, May 26, 2014 at 04:51:41PM +0200, Antoine Ténart wrote:
This series adds the support for Berlin SoC AHCI controller. The
controller allows to use the SATA host interface and, for example, the
eSATA port on the BG2Q.
The series adds a PHY driver to control the two SATA ports
The BG2Q has an AHCI SATA controller with an eSATA interface. Enable it.
Only enable the first port, the BG2Q DMP does not support the second one.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 8
1 file changed, 8
The libahci now allows to use multiple PHYs and to represent each port
as a sub-node. Add these bindings to the documentation.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
.../devicetree/bindings/ata/ahci-platform.txt | 38 +-
1 file changed, 37
The BG2Q has an AHCI SATA controller. Add the corresponding nodes
(AHCI, PHY) into its device tree.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/boot/dts/berlin2q.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot
-node. This as the advantage of allowing a per port
configuration. Because some ports may be accessible but disabled in the
device tree, the default port_map is computed automatically when using
this.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
drivers/ata/Kconfig
The Marvell Berlin AHCI has all his specific in the PHY driver. It then
only need to use the libahci functions to work properly.
Add its compatible into the libahci_platform driver.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
drivers/ata/ahci_platform.c | 1 +
1 file
and configure registers in the
AHCI driver
- removed BG2 / BG2CD nodes
Antoine Ténart (7):
phy: add a driver for the Berlin SATA PHY
Documentation: bindings: add the Berlin SATA PHY
ata: libahci: allow to use multiple PHYs
ata: ahci_platform: add the Marvell Berlin AHCI
registers in the SATA range, the PHY seems to be integrated
and no information tells us the contrary. For these reasons, make the
driver a SATA PHY driver.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
drivers/phy/Kconfig | 5 +
drivers/phy/Makefile | 1
The Berlin SATA PHY drives the PHY related to the SATA interface. Add
the corresponding documentation.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
Documentation/devicetree/bindings/phy/berlin-sata-phy.txt | 14 ++
1 file changed, 14 insertions(+)
create mode
On Tue, May 20, 2014 at 11:11:17AM +0200, Sebastian Hesselbarth wrote:
On 05/20/2014 11:04 AM, Antoine Ténart wrote:
+#define HOST_VSA_ADDR 0x0
+#define HOST_VSA_DATA 0x4
+#define PORT_VSR_ADDR 0x78
+#define PORT_VSR_DATA 0x7c
Above two lines
On Tue, May 20, 2014 at 11:18:11AM +0200, Sebastian Hesselbarth wrote:
On 05/20/2014 11:04 AM, Antoine Ténart wrote:
The Marvell Berlin AHCI has all his specific in the PHY driver. It then
only need to use the libahci functions to work properly.
If it is that generic, ..
Add its
On Tue, May 20, 2014 at 03:49:42PM +0200, Andrew Lunn wrote:
On Tue, May 20, 2014 at 02:34:20PM +0200, Bartlomiej Zolnierkiewicz wrote:
On Tuesday, May 20, 2014 11:04:29 AM Antoine Ténart wrote:
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 4906c27fa3bd..b31b1986fda4
Hi,
On Tue, May 20, 2014 at 02:34:20PM +0200, Bartlomiej Zolnierkiewicz wrote:
On Tuesday, May 20, 2014 11:04:29 AM Antoine Ténart wrote:
+
+static struct phy_berlin_desc desc[] = {
+ { .val = POWER_DOWN_PHY0 },
+ { .val = POWER_DOWN_PHY1 },
Only .val entry of struct
.
This was actually fixed by:
b51fbf9fb0c3 phy-core: Don't allow building phy-core as a module
Antoine
--
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Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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the body
On Tue, May 20, 2014 at 04:06:52PM +0200, Antoine Ténart wrote:
Hi,
On Tue, May 20, 2014 at 02:34:20PM +0200, Bartlomiej Zolnierkiewicz wrote:
On Tuesday, May 20, 2014 11:04:29 AM Antoine Ténart wrote:
+
+static struct phy_berlin_desc desc[] = {
+ { .val = POWER_DOWN_PHY0
Linus,
On Fri, May 16, 2014 at 03:35:48PM +0200, Linus Walleij wrote:
On Mon, May 5, 2014 at 7:27 AM, Antoine Ténart
antoine.ten...@free-electrons.com wrote:
Add the documentation related to the Berlin pin-controller driver and
explain how to configure this group based controller
avoid using the pen lock mechanism.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/mach-berlin/Kconfig | 3 ++
arch/arm/mach-berlin/Makefile | 3 +-
arch/arm/mach-berlin/headsmp.S | 30 +
arch/arm/mach-berlin/platsmp.c | 99
The SMP support for Marvell Berlin SoCs introduce a new enable-method.
Document it.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm
Add required nodes and properties into the Berlin BG2Q device tree to
take advantage of the newly introduced SMP support. Add the scu and
cpu-ctrl nodes along with the CPUs enable-method property.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/boot/dts/berlin2q.dtsi
lock mechanism.
Antoine Ténart (5):
ARM: berlin: add SMP support
Documentation: bindings: document the Marvell Berlin enable-method
Documentation: bindings: add the Berlin CPU control doc
ARM: dts: berlin: add SMP related nodes and properties for BG2
ARM: dts: berlin: add SMP related
Document the CPU control compatible, needed for the SMP support on
Marvell Berlin SoCs.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
Documentation/devicetree/bindings/arm/marvell,berlin.txt | 16
1 file changed, 16 insertions(+)
diff --git a/Documentation
Add required nodes and properties into the Berlin BG2 device tree to
take advantage of the newly introduced SMP support. Add the scu and
cpu-ctrl nodes along with the CPUs enable-method property.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/boot/dts/berlin2.dtsi
On Mon, Jun 02, 2014 at 10:29:13AM +0100, Russell King - ARM Linux wrote:
On Mon, Jun 02, 2014 at 11:21:02AM +0200, Antoine Ténart wrote:
diff --git a/arch/arm/mach-berlin/Kconfig b/arch/arm/mach-berlin/Kconfig
index d3c5f14dc142..e3733692f67a 100644
--- a/arch/arm/mach-berlin/Kconfig
Hi Andrew,
On Mon, Jun 02, 2014 at 11:35:32AM +0200, Andrew Lunn wrote:
On Mon, Jun 02, 2014 at 11:21:01AM +0200, Antoine Ténart wrote:
This series adds the SMP support for Marvell Berlin BG2 and BG2Q.
This implementation takes advantage of the reset exception register and
the software
Hi Andrew,
On Mon, Jun 02, 2014 at 11:47:15AM +0200, Andrew Lunn wrote:
On Mon, Jun 02, 2014 at 11:21:02AM +0200, Antoine Ténart wrote:
+
+static inline void berlin_reset_cpu(unsigned int cpu)
+{
+ u32 val;
+
+ val = readl(cpu_ctrl + CPU_RESET);
+ val |= BIT(cpu_logical_map
On Mon, Jun 02, 2014 at 12:03:32PM +0200, Andrew Lunn wrote:
On Mon, Jun 02, 2014 at 12:00:48PM +0200, Antoine Ténart wrote:
Hi Andrew,
On Mon, Jun 02, 2014 at 11:47:15AM +0200, Andrew Lunn wrote:
On Mon, Jun 02, 2014 at 11:21:02AM +0200, Antoine Ténart wrote:
+
+static inline
The ahci_platform driver is a generic driver using the libahci_platform
functions. Add a generic compatible to avoid having an endless list of
compatibles with no differences for the same driver.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
drivers/ata/ahci_platform.c | 2
-node. This as the advantage of allowing a per port
configuration. Because some ports may be accessible but disabled in the
device tree, the default port_map is computed automatically when using
this.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
drivers/ata/ahci.h
nodes
Antoine Ténart (7):
phy: add a driver for the Berlin SATA PHY
Documentation: bindings: add the Berlin SATA PHY
ata: libahci: allow to use multiple PHYs
ata: ahci_platform: add a generic AHCI compatible
Documentation: bindings: document the sub-nodes AHCI bindings
ARM: berlin: add
The libahci now allows to use multiple PHYs and to represent each port
as a sub-node. Add these bindings to the documentation.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
.../devicetree/bindings/ata/ahci-platform.txt | 38 +-
1 file changed, 37
The BG2Q has an AHCI SATA controller with an eSATA interface. Enable it.
Only enable the first port, the BG2Q DMP does not support the second one.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 8
1 file changed, 8
The BG2Q has an AHCI SATA controller. Add the corresponding nodes
(AHCI, PHY) into its device tree.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/boot/dts/berlin2q.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot
registers in the SATA range, the PHY seems to be integrated
and no information tells us the contrary. For these reasons, make the
driver a SATA PHY driver.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
drivers/phy/Kconfig | 7 ++
drivers/phy/Makefile | 1
The Berlin SATA PHY drives the PHY related to the SATA interface. Add
the corresponding documentation.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
Documentation/devicetree/bindings/phy/berlin-sata-phy.txt | 14 ++
1 file changed, 14 insertions(+)
create mode
On Tue, May 27, 2014 at 03:29:17PM +0900, Jingoo Han wrote:
Use devm_ioremap_resource() because devm_request_and_ioremap() is
obsoleted by devm_ioremap_resource().
Signed-off-by: Jingoo Han jg1@samsung.com
Acked-by: Antoine Ténart antoine.ten...@free-electrons.com
Thanks!
Antoine
The BG2Q has an AHCI SATA controller with an eSATA interface. Enable it.
Also use the SATA PHY 0, the BG2Q DMP does not has the SATA PHY 1.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 10 ++
1 file changed, 10
Antoine Ténart (6):
phy: add a driver for the Berlin SATA PHY
Documentation: bindings: add the Berlin SATA PHY
ata: ahci: add AHCI support for the Berlin BG2Q
Documentation: bindings: add the berlin-ahci compatible to the ahci
platform
ARM: berlin: add the AHCI node for the BG2Q
The BG2Q has an AHCI SATA controller. Add the corresponding nodes
(AHCI, SATA PHY) in its device tree.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/boot/dts/berlin2q.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts
The berlin-ahci driver allows Berlin SoCs to support their AHCI SATA controller.
Add the corresponding device tree bindings documentation.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
Documentation/devicetree/bindings/ata/ahci-berlin.txt | 18 ++
1 file
Add support for the Berlin BG2Q AHCI SATA controller allowing to
interface with devices like external hard drives.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
drivers/ata/Kconfig | 10 +++
drivers/ata/Makefile | 1 +
drivers/ata/ahci_berlin.c | 202
The Berlin SoC has a two SATA ports. Add a PHY driver to handle them.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
drivers/phy/Kconfig | 5 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-berlin-sata.c | 179
The Berlin SATA PHY drives the PHY related to the SATA interface and
allows to power up/down each PHY independently. Add the corresponding
documentation.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
Documentation/devicetree/bindings/phy/berlin-sata-phy.txt | 15
The phys array is of size EXYNOS_MIPI_PHYS_NUM. Trying to access the
index EXYNOS_MIPI_PHYS_NUM should return an error.
Fixes: 069d2e26e9d6 phy: Add driver for Exynos MIPI CSIS/DSIM DPHYs
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
drivers/phy/phy-exynos-mipi-video.c | 2
Hi Andrew,
On Mon, May 12, 2014 at 04:12:21PM +0200, Andrew Lunn wrote:
On Mon, May 12, 2014 at 11:16:54AM +0200, Antoine Ténart wrote:
[…]
I've no idea is this is a good or bad idea, but could you put all the
above code in the phy driver? It does seem to be mostly phy
related. Then teach
Hello,
On Mon, May 12, 2014 at 06:16:46PM +0530, Kishon Vijay Abraham I wrote:
On Monday 12 May 2014 02:46 PM, Antoine Ténart wrote:
[…]
+struct phy_desc {
to be consistent, lets name it phy_berlin_desc.
+ struct phy *phy;
+ u32 val;
+ unsignedindex
On Mon, May 12, 2014 at 11:16:52AM +0200, Antoine Ténart wrote:
[…]
+static int phy_berlin_sata_probe(struct platform_device *pdev)
+{
+ struct phy *phy;
+ struct phy_provider *phy_provider;
+ struct priv *priv;
+ struct resource *res;
+ int i;
+
+ priv
and configure registers in the
AHCI driver
- removed BG2 / BG2CD nodes
Antoine Ténart (6):
phy: add a driver for the Berlin SATA PHY
Documentation: bindings: add the Berlin SATA PHY
ata: ahci: add AHCI support for the Berlin BG2Q
Documentation: bindings: add the berlin-ahci
The BG2Q has an AHCI SATA controller. Add the corresponding nodes
(AHCI, SATA PHYs) in its device tree.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/boot/dts/berlin2q.dtsi | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot
The BG2Q has an AHCI SATA controller with an eSATA interface. Enable it.
Also use the SATA PHY 0, the BG2Q DMP does not has the SATA PHY 1.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 10 ++
1 file changed, 10
Add support for the Berlin BG2Q AHCI SATA controller allowing to
interface with devices like external hard drives.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
drivers/ata/Kconfig | 10 +++
drivers/ata/Makefile | 1 +
drivers/ata/ahci_berlin.c | 202
The Berlin SATA PHY drives the PHY related to the SATA interface and
allows to power up/down each PHY independently. Add the corresponding
documentation.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
.../devicetree/bindings/phy/berlin-sata-phy.txt| 34
The Berlin SoC has a two SATA ports. Add a PHY driver to handle them.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
drivers/phy/Kconfig | 5 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-berlin-sata.c | 180
The berlin-ahci driver allows Berlin SoCs to support their AHCI SATA controller.
Add the compatible to the device tree bindings documentation.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
Documentation/devicetree/bindings/ata/ahci-berlin.txt | 18 ++
1 file
Hi,
On Wed, May 14, 2014 at 03:43:03PM +0530, Kishon Vijay Abraham I wrote:
Hi,
On Wednesday 14 May 2014 03:18 PM, Antoine Ténart wrote:
[…]
+#define to_berlin_sata_phy_priv(desc) \
+ container_of((desc), struct phy_berlin_priv, phys[(desc)-index])
+
+struct phy_berlin_desc
Arnd,
On Wed, May 14, 2014 at 03:02:34PM +0200, Arnd Bergmann wrote:
On Wednesday 14 May 2014 11:48:57 Antoine Ténart wrote:
+static int phy_berlin_sata_power_on(struct phy *phy)
+{
+ struct phy_berlin_desc *desc = phy_get_drvdata(phy);
+ struct phy_berlin_priv *priv
On Wed, May 14, 2014 at 05:31:24PM +0200, Arnd Bergmann wrote:
On Wednesday 14 May 2014 16:50:02 Antoine Ténart wrote:
On Wed, May 14, 2014 at 03:02:34PM +0200, Arnd Bergmann wrote:
On Wednesday 14 May 2014 11:48:57 Antoine Ténart wrote:
+static int phy_berlin_sata_power_on(struct phy
registers in the SATA range, the PHY seems to be integrated
and no information tells us the contrary. For these reasons, make the
driver a SATA PHY driver.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
drivers/phy/Kconfig | 7 ++
drivers/phy/Makefile | 1
The BG2Q has an AHCI SATA controller with an eSATA interface. Enable it.
Only enable the first port, the BG2Q DMP does not support the second one.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 8
1 file changed, 8
The libahci now allows to use multiple PHYs and to represent each port
as a sub-node. Add these bindings to the documentation.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
.../devicetree/bindings/ata/ahci-platform.txt | 37 ++
1 file changed, 37
The ahci_platform driver is a generic driver using the libahci_platform
functions. Add a generic compatible to avoid having an endless list of
compatibles with no differences for the same driver.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
drivers/ata/ahci_platform.c | 2
The BG2Q has an AHCI SATA controller. Add the corresponding nodes
(AHCI, PHY) into its device tree.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/boot/dts/berlin2q.dtsi | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot
:)
- wrote a function to select and configure registers in the
AHCI driver
- removed BG2 / BG2CD nodes
Antoine Ténart (7):
phy: add a driver for the Berlin SATA PHY
Documentation: bindings: add the Berlin SATA PHY
ata: libahci: allow to use multiple PHYs
ata: ahci_platform: add
-node. This as the advantage of allowing a per port
configuration. Because some ports may be accessible but disabled in the
device tree, the default port_map is computed automatically when using
this.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
drivers/ata/ahci.h
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