)
> /* Number of entries in the page table */
> -#define PTRS_PER_PTE(PAGE_SIZE / sizeof(pte_t))
> +#ifdef __PAGETABLE_PMD_FOLDED
> +#define PTRS_PER_PTE (1 << (PGDIR_SHIFT - PAGE_SHIFT))
> +#else
> +#define PTRS_PER_PTE (1 << (PMD_SHIFT - PAGE_SHIFT))
> +#endif
>
> /* Number of PGD entries that a user-mode program can use */
> #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
> --
> 1.9.1
>
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
egral part of kernel development and this should not be a
reason to defer critical changes as long as changes are tested on existing HW.
Linux kernel is all about "organic development". We start with a reasonable
implementation of any thing and perfect it incrementally over time. That's
> -Original Message-
> From: Gary Guo
> Sent: Thursday, April 25, 2019 8:19 AM
> To: Anup Patel ; Palmer Dabbelt
>
> Cc: Anup Patel ; Albert Ou
> ; Atish Patra ; Christoph
> Hellwig ; Paul Walmsley ;
> Mike Rapoport ; linux-ri...@lists.infradead.org; linu
> -Original Message-
> > From: Anup Patel
> > Sent: Thursday, April 25, 2019 03:04
> > To: Palmer Dabbelt
> > Cc: Anup Patel ; Albert Ou ;
> > Gary Guo ; Atish Patra ; Christoph
> > Hellwig ; Paul Walmsley ;
> > Mike Rapoport ; linux-ri...@lis
On Wed, Apr 24, 2019 at 8:31 PM Christoph Hellwig wrote:
>
> On Wed, Apr 24, 2019 at 12:15:45PM +0530, Anup Patel wrote:
> > We need these defines for programming HIDELEG CSR in KVM kernel module
> > so it will be used at multiple places.
> >
> > >
> &g
.
Signed-off-by: Anup Patel
Reviewed-by: Christoph Hellwig
---
arch/riscv/include/asm/csr.h | 32 ++--
arch/riscv/include/asm/irqflags.h| 10 -
arch/riscv/include/asm/mmu_context.h | 7 +-
arch/riscv/kernel/entry.S| 22
The spacing between macro name and value is not consistent in
asm/csr.h. This patch beautifies asm/csr.h by using tabs to align
macro values instead of spaces.
Signed-off-by: Anup Patel
Reviewed-by: Christoph Hellwig
---
arch/riscv/include/asm/csr.h | 76 ++--
1
elated SCAUSE defines
in asm/encoding.h
Anup Patel (3):
RISC-V: Use tabs to align macro values in asm/csr.h
RISC-V: Add interrupt related SCAUSE defines in asm/csr.h
RISC-V: Access CSRs using CSR numbers
arch/riscv/include/asm/csr.h | 127 +--
arch/riscv/i
This patch adds SCAUSE interrupt flag and SCAUSE interrupt related
defines to asm/csr.h. We also use these defines in kernel/irq.c and
express SIE/SIP flags in-terms of SCAUSE interrupt causes.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/csr.h | 25 +
arch/riscv
On Thu, Apr 25, 2019 at 11:28 AM Christoph Hellwig wrote:
>
> > +#ifdef CONFIG_64BIT
> > +#define SCAUSE_IRQ_FLAG _AC(0x8000, UL)
> > +#else
> > +#define SCAUSE_IRQ_FLAG _AC(0x8000, UL)
> > +#endif
>
> Please keep the existing defintion that doesn't need a
The spacing between macro name and value is not consistent in
asm/csr.h. This patch beautifies asm/csr.h by using tabs to align
macro values instead of spaces.
Signed-off-by: Anup Patel
Reviewed-by: Christoph Hellwig
---
arch/riscv/include/asm/csr.h | 76 ++--
1
nce v1:
- Squash PATCH2 into cpatch3
- Added new PATCH2 to add interrupt related SCAUSE defines
in asm/encoding.h
Anup Patel (3):
RISC-V: Use tabs to align macro values in asm/csr.h
RISC-V: Add interrupt related SCAUSE defines in asm/csr.h
RISC-V: Access CSRs using CSR numbers
arch/riscv/i
This patch adds SCAUSE interrupt flag and SCAUSE interrupt related
defines to asm/csr.h. We also use these defines in kernel/irq.c and
express SIE/SIP flags in-terms of SCAUSE interrupt causes.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/csr.h | 21 +
arch/riscv
.
Signed-off-by: Anup Patel
Reviewed-by: Christoph Hellwig
---
arch/riscv/include/asm/csr.h | 32 ++--
arch/riscv/include/asm/irqflags.h| 10 -
arch/riscv/include/asm/mmu_context.h | 7 +-
arch/riscv/kernel/entry.S| 22
On Thu, Apr 25, 2019 at 1:31 PM Christoph Hellwig wrote:
>
> On Thu, Apr 25, 2019 at 12:46:52PM +0530, Anup Patel wrote:
> > On Thu, Apr 25, 2019 at 11:28 AM Christoph Hellwig
> > wrote:
> > >
> > > > +#ifdef CONFIG_64BIT
> > > > +#define SCAU
The spacing between macro name and value is not consistent in
asm/csr.h. This patch beautifies asm/csr.h by using tabs to align
macro values instead of spaces.
Signed-off-by: Anup Patel
Reviewed-by: Christoph Hellwig
---
arch/riscv/include/asm/csr.h | 76 ++--
1
This patch adds SCAUSE interrupt flag and SCAUSE interrupt related
defines to asm/csr.h. We also use these defines in kernel/irq.c and
express SIE/SIP flags in-terms of SCAUSE interrupt causes.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/csr.h | 21 +
arch/riscv
which beautifies asm/csr.h by using tabs to
align macro values
Changes since v1:
- Squash PATCH2 into cpatch3
- Added new PATCH2 to add interrupt related SCAUSE defines
in asm/encoding.h
Anup Patel (3):
RISC-V: Use tabs to align macro values in asm/csr.h
RISC-V: Add interrupt related SCAUSE d
.
Signed-off-by: Anup Patel
Reviewed-by: Christoph Hellwig
---
arch/riscv/include/asm/csr.h | 32 ++--
arch/riscv/include/asm/irqflags.h| 10 -
arch/riscv/include/asm/mmu_context.h | 7 +-
arch/riscv/kernel/entry.S| 22
V SBI console driver")
Cc: sta...@vger.kernel.org
Signed-off-by: Anup Patel
---
drivers/tty/hvc/hvc_riscv_sbi.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/tty/hvc/hvc_riscv_sbi.c b/drivers/tty/hvc/hvc_riscv_sbi.c
index 75155bde2b88..31f53fa77e4a 100644
--- a/drivers/tty/hvc/hvc
On Fri, Apr 26, 2019 at 10:11 AM Atish Patra wrote:
>
> On 4/25/19 6:35 AM, Anup Patel wrote:
> > The Linux kernel will auto-disables all boot consoles whenever it
> > gets a preferred real console.
> >
> > Currently on RISC-V systems, if we have a real console whic
On Fri, Apr 26, 2019 at 11:51 AM Christoph Hellwig wrote:
>
> On Thu, Apr 25, 2019 at 09:41:21PM -0700, Atish Patra wrote:
> > Do we even need HVC_SBI console to be enabled by default? Disabling
> > CONFIG_HVC_RISCV_SBI seems to be fine while running in QEMU.
> >
> > If we don't need it, I suggest
From: Anup Patel
This patchset primarily extends initial page table setup using fixmap
to boot Linux RISC-V kernel (64bit and 32bit) from any 4KB aligned address.
We also add 32bit defconfig to allow people to try 32bit Linux RISC-V
kernel as well.
The patchset is tested on SiFive Unleashed
addressing.
Fixes: 6f1e9e946f0b ("RISC-V: Move setup_vm() to mm/init.c")
Signed-off-by: Anup Patel
---
arch/riscv/kernel/head.S | 1 +
arch/riscv/mm/init.c | 71 ++--
2 files changed, 47 insertions(+), 25 deletions(-)
diff --git a/arch/riscv/ker
-place, the booting constraint for RISCV32 and RISCV64
kernel is much more relaxed and we can now boot kernel very close to
RAM start thereby minimizng memory wastage.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/fixmap.h | 5 +
arch/riscv/include/asm/pgtable-64.h | 5 +
arch/riscv
This patch adds rv32_defconfig for 32bit systems. The only
difference between rv32_defconfig and defconfig is that
rv32_defconfig has CONFIG_ARCH_RV32I=y.
Signed-off-by: Anup Patel
---
arch/riscv/configs/rv32_defconfig | 84 +++
1 file changed, 84 insertions
On Thu, Mar 14, 2019 at 12:01 AM Mike Rapoport wrote:
>
> On Tue, Mar 12, 2019 at 10:08:22PM +, Anup Patel wrote:
> > Currently, we have to boot RISCV64 kernel from a 2MB aligned physical
> > address and RISCV32 kernel from a 4MB aligned physical address. This
> &g
On Thu, Mar 14, 2019 at 12:23 PM Mike Rapoport wrote:
>
> On Thu, Mar 14, 2019 at 02:36:01AM +0530, Anup Patel wrote:
> > On Thu, Mar 14, 2019 at 12:01 AM Mike Rapoport wrote:
> > >
> > > On Tue, Mar 12, 2019 at 10:08:22PM +, Anup Patel wrote:
> > &g
On Fri, Mar 15, 2019 at 9:28 PM Mike Rapoport wrote:
>
> On Thu, Mar 14, 2019 at 11:28:32PM +0530, Anup Patel wrote:
> > On Thu, Mar 14, 2019 at 12:23 PM Mike Rapoport wrote:
> > >
> > > On Thu, Mar 14, 2019 at 02:36:01AM +0530, Anup Patel wrote:
> > >
On Fri, Mar 15, 2019 at 9:28 PM Mike Rapoport wrote:
>
> On Thu, Mar 14, 2019 at 11:28:32PM +0530, Anup Patel wrote:
> > On Thu, Mar 14, 2019 at 12:23 PM Mike Rapoport wrote:
> > >
> > > On Thu, Mar 14, 2019 at 02:36:01AM +0530, Anup Patel wrote:
> > >
ot;RISC-V: Move setup_vm() to mm/init.c")
Suggested-by: Christoph Hellwig
Suggested-by: Mike Rapoport
Signed-off-by: Anup Patel
Reviewed-by: Mike Rapoport
Reviewed-by: Christoph Hellwig
---
v4: Use "#error" for setup_vm() compiled without cmodel=medany
v3: Don't use CF
and ASIDs provided by QEMU. Unfortunately, ASID bits
of SATP CSR are not implemented on SiFive Unleashed board so we don't
see any change in performance.
Signed-off-by: Anup Patel
---
This patch is based on Linux-5.1-rc2 and TLB flush cleanup patches v4
from Gary Guo. It can be also fou
On Wed, Mar 27, 2019 at 4:57 PM Gary Guo wrote:
>
> Hi Anup,
>
> This won't work in an actual hardware with ASID support. There're more
Can you elaborate why?
This implementation is based on Linux ARM64 ASID allocator which is
tested for large number of CPUs on real HW.
> interactions with TLB
On Wed, Mar 27, 2019 at 7:12 PM Gary Guo wrote:
>
> I would also like to mention that your code assumes 64-bit atomics
> support which we don't have on 32-bit systems. Using 32-bit to track
> ASID generations isn't sufficient and will cause overflows. That's why I
> have asid_generation_overflow t
On Wed, Mar 27, 2019 at 7:08 PM Gary Guo wrote:
>
> On 27/03/2019 11:42, Anup Patel wrote:
> > On Wed, Mar 27, 2019 at 4:57 PM Gary Guo wrote:
> >>
> >> Hi Anup,
> >>
> >> This won't work in an actual hardware with ASID support. There
On Wed, Mar 27, 2019 at 7:39 PM Gary Guo wrote:
>
> I think my code already get all the caveats cases covered. The only
> thing my code is missing is handling the case when ASID is not
> supported. Maybe it is better to work based on that instead?
Well, I have also spend enough time hardening thi
, did you also fix that issue? It's somewhere in my
> email queue...
That was a patch I submitted to fix overlapping FIXMAP and VMALLOC
regions.
This patch does not consider FIXMAP region.
I suggest we introduce asm/memory.h where we have all critical defines
related to virtual me
TLBs provided by QEMU. Unfortunately, ASID bits of SATP CSR
are not implemented on SiFive Unleashed board so we don't see any change
in performance.
Signed-off-by: Gary Guo
Signed-off-by: Anup Patel
---
Changes since v1:
- We adapt good aspects from Gary Guo's ASID allocator implementa
On Thu, Mar 28, 2019 at 1:25 PM Mike Rapoport wrote:
>
> On Wed, Mar 27, 2019 at 12:54:41AM -0700, Christoph Hellwig wrote:
> > On Mon, Mar 25, 2019 at 09:46:59PM +0530, Anup Patel wrote:
> > > > Why do you even care about kernel mappings for non-existant ram.
> >
gned version of va_pa_offset such that all of the physical
> address space will be mapped.
>
> Signed-off-by: Logan Gunthorpe
> Cc: Palmer Dabbelt
> Cc: Albert Ou
> Cc: Anup Patel
> Cc: Atish Patra
> Cc: Paul Walmsley
> Cc: Zong Li
> Cc: Mike Rapoport
> ---
>
On Thu, Mar 28, 2019 at 3:22 PM Anup Patel wrote:
>
> On Thu, Mar 28, 2019 at 1:25 PM Mike Rapoport wrote:
> >
> > On Wed, Mar 27, 2019 at 12:54:41AM -0700, Christoph Hellwig wrote:
> > > On Mon, Mar 25, 2019 at 09:46:59PM +0530, Anup Patel wrote:
> > > &
fixes above issue by reserving unusable memory region in
setup_bootmem().
Signed-off-by: Anup Patel
---
arch/riscv/mm/init.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index 5fd8c922e1c2..6b063f20a9d0 100644
--- a/arch/riscv/mm/init.c
On Tue, Apr 2, 2019 at 2:05 PM Mike Rapoport wrote:
>
> On Tue, Apr 02, 2019 at 06:02:38AM +, Anup Patel wrote:
> > The Maximum Physical Memory 2GiB option for 64bit systems is currently
> > broken because kernel hangs at boot-time when this option is enabled
> > and t
fixes above issue by removing unusable memory region in
setup_bootmem().
Signed-off-by: Anup Patel
---
Changes since v1:
- Use memblock_remove() instead of memblock_reserve()
---
arch/riscv/mm/init.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm
On Tue, Apr 2, 2019 at 2:05 PM Mike Rapoport wrote:
>
> On Tue, Apr 02, 2019 at 06:02:38AM +, Anup Patel wrote:
> > The Maximum Physical Memory 2GiB option for 64bit systems is currently
> > broken because kernel hangs at boot-time when this option is enabled
> > and t
> -Original Message-
> From: Guo Ren
> Sent: Tuesday, April 9, 2019 8:33 AM
> To: Anup Patel
> Cc: Palmer Dabbelt ; Albert Ou
> ; linux-kernel@vger.kernel.org; Mike Rapoport
> ; Christoph Hellwig ; Atish Patra
> ; Gary Guo ; Paul Walmsley
> ; linux-ri...@li
On Tue, Apr 9, 2019 at 10:17 PM Palmer Dabbelt wrote:
>
> On Tue, 12 Mar 2019 15:08:16 PDT (-0700), Anup Patel wrote:
> > The setup_vm() must access kernel symbols in a position independent way
> > because it will be called from head.S with MMU off.
> >
> > If we com
On Tue, Apr 9, 2019 at 10:14 PM Palmer Dabbelt wrote:
>
> On Tue, 12 Mar 2019 15:08:12 PDT (-0700), Anup Patel wrote:
> > This patch adds rv32_defconfig for 32bit systems. The only
> > difference between rv32_defconfig and defconfig is that
> > rv32_defconfig has CONFIG_
On Wed, Feb 3, 2021 at 7:58 AM Palmer Dabbelt wrote:
>
> On Thu, 21 Jan 2021 05:50:16 PST (-0800), Anup Patel wrote:
> > Currently, we do local TLB flush on every MM switch. This is very harsh on
> > performance because we are forcing page table walks after every MM switch.
rd so we don't see any change in performance. On real HW
having all ASID bits implemented, the performance gains will be much
more due improved sharing of TLB among different processes.
Signed-off-by: Anup Patel
Reviewed-by: Palmer Dabbelt
---
Changes since v4:
- Rebased on Linux-5.11-
The CPU hotplug support has been tested on QEMU, Spike, and SiFive
Unleashed so let's enable it by default in RV32 and RV64 defconfigs.
Signed-off-by: Anup Patel
---
arch/riscv/configs/defconfig | 1 +
arch/riscv/configs/rv32_defconfig | 1 +
2 files changed, 2 insertions(+)
diff --
Hi Palmer,
On Fri, Feb 19, 2021 at 12:45 PM Palmer Dabbelt
wrote:
>
> On Mon, 08 Feb 2021 21:46:20 PST (-0800), Anup Patel wrote:
> > The CPU hotplug support has been tested on QEMU, Spike, and SiFive
> > Unleashed so let's enable it by default in RV32 and RV64 defconfigs
Hi Alex,
On Fri, Feb 26, 2021 at 6:46 PM Alex Ghiti wrote:
>
> Hi Anup,
>
> Le 2/21/21 à 4:37 AM, Anup Patel a écrit :
> > We force select CPU_PM and provide asm/cpuidle.h so that we can
> > use CPU IDLE drivers for Linux RISC-V kernel.
> >
> > Signed-off-by:
RQCHIP drivers.
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
---
arch/riscv/include/asm/irq.h | 1 -
arch/riscv/include/asm/smp.h | 3 +++
arch/riscv/kernel/irq.c | 16 ++--
arch/riscv/kernel/smp.c | 11 ++
ve do_IRQ() function
- Rebased upon Atish's SMP patches
Anup Patel (6):
RISC-V: self-contained IPI handling routine
RISC-V: Rename and move plic_find_hart_id() to arch directory
irqchip: RISC-V per-HART local interrupt controller driver
clocksource/drivers/timer-riscv: Use per-CPU
Instead of directly calling RISC-V timer interrupt handler from
RISC-V local interrupt conntroller driver, this patch implements
RISC-V timer interrupt as a per-CPU interrupt using per-CPU APIs
of Linux IRQ subsystem.
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
---
arch/riscv/include
Dabbelt
Signed-off-by: Palmer Dabbelt
Signed-off-by: Anup Patel
Acked-by: Palmer Dabbelt
---
arch/riscv/Kconfig| 1 +
arch/riscv/include/asm/irq.h | 2 -
arch/riscv/kernel/irq.c | 33 +--
arch/riscv/kernel/traps.c | 2 -
drivers/irqchip/Kconfig
The RISC-V per-HART local interrupt controller driver is mandatory
for all RISC-V system (with/without MMU) hence we force select it
for CONFIG_RISCV (just like RISCV_TIMER).
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
---
arch/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff
The only thing do_IRQ() does is call handle_arch_irq function
pointer. We can very well call handle_arch_irq function pointer
directly from assembly and remove do_IRQ() function hence this
patch.
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
---
arch/riscv/kernel/entry.S | 4 +++-
arch
The plic_find_hart_id() can be useful to other interrupt controller
drivers (such as RISC-V local interrupt driver) so we rename this
function to riscv_of_parent_hartid() and place it in arch directory
along with riscv_of_processor_hartid().
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
On Sat, May 30, 2020 at 5:31 PM Marc Zyngier wrote:
>
> On 2020-05-30 11:07, Anup Patel wrote:
> > The RISC-V per-HART local interrupt controller manages software
> > interrupts, timer interrupts, external interrupts (which are routed
> > via the platform level interrupt c
On Sat, May 30, 2020 at 5:11 PM Marc Zyngier wrote:
>
> On 2020-05-30 11:07, Anup Patel wrote:
> > Instead of directly calling RISC-V timer interrupt handler from
> > RISC-V local interrupt conntroller driver, this patch implements
> > RISC-V timer interrupt as a per-CPU
: add STRICT_KERNEL_RWX support")
Cc: sta...@vger.kernel.org
Signed-off-by: Anup Patel
---
arch/riscv/mm/init.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index 736de6c8739f..e0f8ccab8a41 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv
On Sun, May 31, 2020 at 3:03 PM Marc Zyngier wrote:
>
> On 2020-05-31 06:36, Anup Patel wrote:
> > On Sat, May 30, 2020 at 5:31 PM Marc Zyngier wrote:
>
> [...]
>
> >> > plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD);
> >>
> >>
On Sun, May 31, 2020 at 4:23 PM Marc Zyngier wrote:
>
> On 2020-05-31 11:06, Anup Patel wrote:
> > On Sun, May 31, 2020 at 3:03 PM Marc Zyngier wrote:
> >>
> >> On 2020-05-31 06:36, Anup Patel wrote:
> >> > On Sat, M
On Sun, May 31, 2020 at 3:28 PM Anup Patel wrote:
>
> The head text section (i.e. _start, secondary_start_sbi, etc) and the
> init section fall under same page table level-1 mapping.
>
> Currently, the runtime CPU hotplug is broken because we are marking
> init section as non-e
: add STRICT_KERNEL_RWX support")
Cc: sta...@vger.kernel.org
Signed-off-by: Anup Patel
---
Changes since v1:
- Updated free_initmem() is same as generic free_initmem() defined in
init/main.c so we completely remove free_initmem() from arch/riscv
---
arch/riscv/mm/init.c | 11 ---
1 fi
On Mon, Jun 1, 2020 at 1:11 PM Marc Zyngier wrote:
>
> On 2020-06-01 05:09, Anup Patel wrote:
> > On Sun, May 31, 2020 at 4:23 PM Marc Zyngier wrote:
> >>
> >> On 2020-05-31 11:06, Anup Patel wrote:
>
> [...]
>
> > Also, the PLIC spec is now owned by
-off-by: Palmer Dabbelt
Signed-off-by: Anup Patel
Acked-by: Palmer Dabbelt
---
arch/riscv/Kconfig| 1 +
arch/riscv/include/asm/irq.h | 2 -
arch/riscv/kernel/irq.c | 33 +--
arch/riscv/kernel/traps.c | 2 -
drivers/irqchip/Kconfig | 13
Instead of directly calling RISC-V timer interrupt handler from
RISC-V local interrupt conntroller driver, this patch implements
RISC-V timer interrupt as a per-CPU interrupt using per-CPU APIs
of Linux IRQ subsystem.
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
---
arch/riscv/include
The only thing do_IRQ() does is call handle_arch_irq function
pointer. We can very well call handle_arch_irq function pointer
directly from assembly and remove do_IRQ() function hence this
patch.
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
---
arch/riscv/kernel/entry.S | 4 +++-
arch
The RISC-V per-HART local interrupt controller driver is mandatory
for all RISC-V system (with/without MMU) hence we force select it
for CONFIG_RISCV (just like RISCV_TIMER).
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
---
arch/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff
RQCHIP drivers.
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
---
arch/riscv/include/asm/irq.h | 1 -
arch/riscv/include/asm/smp.h | 3 +++
arch/riscv/kernel/irq.c | 16 ++--
arch/riscv/kernel/smp.c | 11 ++
The plic_find_hart_id() can be useful to other interrupt controller
drivers (such as RISC-V local interrupt driver) so we rename this
function to riscv_of_parent_hartid() and place it in arch directory
along with riscv_of_processor_hartid().
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
ined IPI handling routine
- Removed patch for GENERIC_IRQ kconfig options
- Added patch to remove do_IRQ() function
- Rebased upon Atish's SMP patches
Anup Patel (6):
RISC-V: self-contained IPI handling routine
RISC-V: Rename and move plic_find_hart_id() to arch directory
irqchip: RISC-V per-H
On Tue, May 19, 2020 at 7:21 PM Daniel Lezcano
wrote:
>
> On 19/05/2020 14:39, Kefeng Wang wrote:
> >
> > On 2020/5/19 4:23, Daniel Lezcano wrote:
> >> Hi Kefeng,
> >>
> >> On 18/05/2020 17:40, Kefeng Wang wrote:
> >>> On 2020/5/18 22:09, Daniel Lezcano wrote:
> On 13/05/2020 23:14, Palmer Da
arate patch for self-contained IPI handling routine
- Removed patch for GENERIC_IRQ kconfig options
- Added patch to remove do_IRQ() function
- Rebased upon Atish's SMP patches
Anup Patel (6):
RISC-V: self-contained IPI handling routine
RISC-V: Rename and move plic_find_hart_id() to arch di
c.txt
Signed-off-by: Palmer Dabbelt
Signed-off-by: Anup Patel
---
arch/riscv/Kconfig | 1 +
arch/riscv/include/asm/irq.h | 2 -
arch/riscv/kernel/irq.c| 33 +-
arch/riscv/kernel/traps.c | 2 -
drivers/irqchip/Kc
RQCHIP drivers.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/irq.h | 1 -
arch/riscv/include/asm/smp.h | 3 +++
arch/riscv/kernel/irq.c | 16 ++--
arch/riscv/kernel/smp.c | 11 +--
4 files changed, 22 insertions(+), 9 deletions(-)
diff --git a/arch/riscv/
Instead of directly calling RISC-V timer interrupt handler from
RISC-V local interrupt conntroller driver, this patch implements
RISC-V timer interrupt as a per-CPU interrupt using per-CPU APIs
of Linux IRQ subsystem.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/irq.h | 2
The plic_find_hart_id() can be useful to other interrupt controller
drivers (such as RISC-V local interrupt driver) so we rename this
function to riscv_of_parent_hartid() and place it in arch directory
along with riscv_of_processor_hartid().
Signed-off-by: Anup Patel
---
arch/riscv/include/asm
The RISC-V per-HART local interrupt controller driver is mandatory
for all RISC-V system (with/without MMU) hence we force select it
for CONFIG_RISCV (just like RISCV_TIMER).
Signed-off-by: Anup Patel
---
arch/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/Kconfig
The only thing do_IRQ() does is call handle_arch_irq function
pointer. We can very well call handle_arch_irq function pointer
directly from assembly and remove do_IRQ() function hence this
patch.
Signed-off-by: Anup Patel
---
arch/riscv/kernel/entry.S | 4 +++-
arch/riscv/kernel/irq.c | 6
i.e. NoMMU)
Anup Patel (5):
RISC-V: Add mechanism to provide custom IPI operations
RISC-V: Remove CLINT related code
clocksource/drivers/timer-riscv: Remove MMIO related stuff
clocksource/drivers: Add CLINT timer driver
dt-bindings: timer: Add CLINT bindings
.../bindings/timer/sifive
compare
register for clockevent device.
This patch removes MMIO related stuff from RISC-V timer driver
so that we can have a separate CLINT timer driver.
Signed-off-by: Anup Patel
---
arch/riscv/Kconfig| 2 +-
arch/riscv/include/asm/timex.h| 28
The TIME CSR and SBI calls are not available in RISC-V M-mode so we
add CLINT driver for Linux RISC-V M-mode (i.e. RISC-V NoMMU kernel).
Signed-off-by: Anup Patel
---
drivers/clocksource/Kconfig | 10 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-clint.c | 226
We will be having separate CLINT timer driver which will also
provide CLINT based IPI operations so let's remove CLINT related
code from arch/riscv directory.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/clint.h | 39 --
arch/riscv/kernel/Makefile
We add mechanism to set custom IPI operations so that CLINT driver
from drivers directory can provide custom IPI operations.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/smp.h | 11
arch/riscv/kernel/smp.c | 52
arch/riscv/kernel
We add DT bindings documentation for CLINT device.
Signed-off-by: Anup Patel
---
.../bindings/timer/sifive,clint.txt | 33 +++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt
diff --git a/Documentation
On Tue, Aug 11, 2020 at 12:07 PM Qiu Wenbo wrote:
>
> Exception vector is missing on nommu platform and it is a big issue.
> This patch is tested in Sipeed MAIX Bit Dev Board.
>
> Fixes: 79b1feba5455 ("RISC-V: Setup exception vector early")
> Signed-off-by: Qiu Wenbo
> ---
> arch/riscv/kernel/sm
On Wed, Aug 12, 2020 at 12:16 AM Atish Patra wrote:
>
> On Tue, Aug 11, 2020 at 1:41 AM Anup Patel wrote:
> >
> > On Tue, Aug 11, 2020 at 12:07 PM Qiu Wenbo wrote:
> > >
> > > Exception vector is missing on nommu platform and it is a big issue.
> > >
On Wed, Aug 5, 2020 at 7:17 AM Palmer Dabbelt wrote:
>
> On Fri, 24 Jul 2020 00:18:18 PDT (-0700), Anup Patel wrote:
> > The current RISC-V timer driver is convoluted and implements two
> > distinct timers:
> > 1. S-mode timer: This is for Linux RISC-V S-mode with MMU. Th
to the resource tree")
>
> Signed-off-by: Atish Patra
Looks good to me.
Reviewed-by: Anup Patel
> ---
> arch/riscv/kernel/setup.c | 24 +---
> 1 file changed, 13 insertions(+), 11 deletions(-)
>
> diff --git a/arch/riscv/kernel/setup.c b/arch/ris
ff-by: Atish Patra
Looks good to me.
Reviewed-by: Anup Patel
> ---
> arch/riscv/include/asm/cache.h | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
> index 9b58b104559e..c9c669ea2fe6 100644
> --- a
_pa_symbol(&_start);
> + phys_addr_t max_mapped_addr = __pa(PHYS_ADDR_MAX);
Using PHYS_ADDR_MAX as the max virtual address does not look right.
Better use __pa(~(ulong)0) here. Otherwise looks good to me.
Reviewed-by: Anup Patel
> u64 i;
>
> /* Find the memory region c
simply not true for current kernel. In future, a 2GB split support can be
> added to allow 2GB physical address space.
>
> Signed-off-by: Atish Patra
Just for information, Alex's also has a patch to simplify this. Refer,
"[RFC PATCH 05/12] riscv: Simplify MAXPHYSMEM config"
Hi Palmer,
On Thu, Jan 7, 2021 at 2:57 PM Atish Patra wrote:
>
> This series fixes various issues observed in latest kernel on RV32.
> The first two patches fixes an resource tree introduced in 5.11-rc1
> while the last two fixes the case where 2GB physical memory is used
> on RV32.
>
> There are
On Tue, Dec 22, 2020 at 2:08 AM Vitaly Wool wrote:
>
> Introduce XIP (eXecute In Place) support for RISC-V platforms.
> It allows code to be executed directly from non-volatile storage
> directly addressable by the CPU, such as QSPI NOR flash which can
> be found on many RISC-V platforms. This mak
On Tue, Dec 22, 2020 at 3:55 PM Vitaly Wool wrote:
>
> Hi Anup,
>
> On Tue, Dec 22, 2020 at 6:16 AM Anup Patel wrote:
> >
> > On Tue, Dec 22, 2020 at 2:08 AM Vitaly Wool
> > wrote:
> > >
> > > Introduce XIP (eXecute In Place) support for RISC-
Hi,
On Tue, Jan 19, 2021 at 1:40 PM Geert Uytterhoeven wrote:
>
> Let the LiteX SoC Controller register a restart handler, which resets
> the LiteX SoC by writing 1 to CSR_CTRL_RESET_ADDR.
>
> Signed-off-by: Geert Uytterhoeven
We have SBI System Reset Extension (SRST) in upcoming
SBI v0.3 spec.
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