On 12/22/2014 2:15 PM, Borislav Petkov wrote:
On Mon, Dec 22, 2014 at 02:10:09PM -0600, Aravind Gopalakrishnan wrote:
When a MCE happens that is to be logged onto bank 4 of AMD multi-node
processors, they are reported only to corresponding node base core of
the cpu on which the error occurred
. We can make this extern as and when need arises.
While at it, reverse the return condition in amd_get_topology
and save an indent level.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/processor.h | 1 +
arch/x86/kernel/cpu/amd.c| 78
For Fam10h onwards, bank4 MCE are reported only to the node base
cores. This patch modifies the do_inject code path to take care
of this.
Refer D18F3x44[NbMcaToMstCpuEn] on BKDGs of Fam10h and later for
clarifications on the reporting of MC4 errors only to NBC MSRs.
Signed-off-by: Aravind
handling.
Aravind Gopalakrishnan (3):
x86,amd: Refactor amd cpu topology functions for multi-node processors
x86, mce: Handle AMD MCE on bank4 on NBC for multi-node processors
edac, mce_amd_inj: Inject errors only on NBC for bank 4 errors
arch/x86/include/asm/processor.h | 1 +
arch/x86
mechanism
later on the correct cpu on which error happened.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/kernel/cpu/mcheck/mce.c | 167 +++
1 file changed, 153 insertions(+), 14 deletions(-)
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86
mechanism
later on the correct cpu on which error happened.
Signed-off-by: Aravind Gopalakrishnan aravind.gopalakrish...@amd.com
---
arch/x86/kernel/cpu/mcheck/mce.c | 167 +++
1 file changed, 153 insertions(+), 14 deletions(-)
diff --git a/arch/x86/kernel/cpu
For Fam10h onwards, bank4 MCE are reported only to the node base
cores. This patch modifies the do_inject code path to take care
of this.
Refer D18F3x44[NbMcaToMstCpuEn] on BKDGs of Fam10h and later for
clarifications on the reporting of MC4 errors only to NBC MSRs.
Signed-off-by: Aravind
. We can make this extern as and when need arises.
While at it, reverse the return condition in amd_get_topology
and save an indent level.
Signed-off-by: Aravind Gopalakrishnan aravind.gopalakrish...@amd.com
---
arch/x86/include/asm/processor.h | 1 +
arch/x86/kernel/cpu/amd.c| 78
handling.
Aravind Gopalakrishnan (3):
x86,amd: Refactor amd cpu topology functions for multi-node processors
x86, mce: Handle AMD MCE on bank4 on NBC for multi-node processors
edac, mce_amd_inj: Inject errors only on NBC for bank 4 errors
arch/x86/include/asm/processor.h | 1 +
arch/x86
On 12/22/2014 2:15 PM, Borislav Petkov wrote:
On Mon, Dec 22, 2014 at 02:10:09PM -0600, Aravind Gopalakrishnan wrote:
When a MCE happens that is to be logged onto bank 4 of AMD multi-node
processors, they are reported only to corresponding node base core of
the cpu on which the error occurred
Commit-ID: 904cb3677f3adcd3d837be0a0d0b14251ba8d6f7
Gitweb: http://git.kernel.org/tip/904cb3677f3adcd3d837be0a0d0b14251ba8d6f7
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 10 Nov 2014 14:24:26 -0600
Committer: Ingo Molnar
CommitDate: Wed, 12 Nov 2014 15:12:32 +0100
perf/x86/amd/ibs
Commit-ID: 904cb3677f3adcd3d837be0a0d0b14251ba8d6f7
Gitweb: http://git.kernel.org/tip/904cb3677f3adcd3d837be0a0d0b14251ba8d6f7
Author: Aravind Gopalakrishnan aravind.gopalakrish...@amd.com
AuthorDate: Mon, 10 Nov 2014 14:24:26 -0600
Committer: Ingo Molnar mi...@kernel.org
CommitDate: Wed
On 11/10/2014 4:17 PM, Borislav Petkov wrote:
On Mon, Nov 10, 2014 at 04:06:00PM -0600, Aravind Gopalakrishnan wrote:
+ MCESEV(
+ DEFERRED, "Deferred error",
+ NOSER,
MASK(MCI_STATUS_UC|MCI_STATUS_DEFERRED|MCI_STATUS_POISON, MCI_STATU
On 11/7/2014 7:40 PM, Chen Yucong wrote:
Until now, the mce_severity mechanism can only identify the severity
of UCNA error as MCE_KEEP_SEVERITY. Meanwhile, it is not able to filter
out DEFERRED error for ADM platform.
This patch aims to extend the mce_severity mechanism for handling
: Len Brown
Cc: Fenghua Yu
Signed-off-by: Aravind Gopalakrishnan
---
Changes in V2 (per Boris suggestion)
- Remove unused MSR listing
arch/x86/include/asm/perf_event.h| 3 +++
arch/x86/include/uapi/asm/msr-index.h| 1 +
arch/x86/kernel/cpu/perf_event_amd_ibs.c | 15
On 11/10/2014 10:03 AM, Borislav Petkov wrote:
On Mon, Nov 10, 2014 at 10:00:59AM -0600, Aravind Gopalakrishnan wrote:
No, There aren't any bits in MSR_AMD64_IBS_FETCH_EXTD_CTL that we need to
configure right now.
So, have included it here mainly to keep the MSR listing consistent
On 11/8/2014 3:03 AM, Borislav Petkov wrote:
On Thu, Nov 06, 2014 at 10:57:40AM -0600, Aravind Gopalakrishnan wrote:
On 11/6/2014 10:34 AM, Borislav Petkov wrote:
On Thu, Nov 06, 2014 at 10:26:22AM -0600, Aravind Gopalakrishnan wrote:
diff --git a/arch/x86/include/uapi/asm/msr-index.h
b/arch
On 11/8/2014 3:03 AM, Borislav Petkov wrote:
On Thu, Nov 06, 2014 at 10:57:40AM -0600, Aravind Gopalakrishnan wrote:
On 11/6/2014 10:34 AM, Borislav Petkov wrote:
On Thu, Nov 06, 2014 at 10:26:22AM -0600, Aravind Gopalakrishnan wrote:
diff --git a/arch/x86/include/uapi/asm/msr-index.h
b/arch
On 11/10/2014 10:03 AM, Borislav Petkov wrote:
On Mon, Nov 10, 2014 at 10:00:59AM -0600, Aravind Gopalakrishnan wrote:
No, There aren't any bits in MSR_AMD64_IBS_FETCH_EXTD_CTL that we need to
configure right now.
So, have included it here mainly to keep the MSR listing consistent
...@suse.de
Cc: Jan Kiszka jan.kis...@siemens.com
Cc: Len Brown len.br...@intel.com
Cc: Fenghua Yu fenghua...@intel.com
Signed-off-by: Aravind Gopalakrishnan aravind.gopalakrish...@amd.com
---
Changes in V2 (per Boris suggestion)
- Remove unused MSR listing
arch/x86/include/asm/perf_event.h
On 11/7/2014 7:40 PM, Chen Yucong wrote:
Until now, the mce_severity mechanism can only identify the severity
of UCNA error as MCE_KEEP_SEVERITY. Meanwhile, it is not able to filter
out DEFERRED error for ADM platform.
This patch aims to extend the mce_severity mechanism for handling
On 11/10/2014 4:17 PM, Borislav Petkov wrote:
On Mon, Nov 10, 2014 at 04:06:00PM -0600, Aravind Gopalakrishnan wrote:
+ MCESEV(
+ DEFERRED, Deferred error,
+ NOSER,
MASK(MCI_STATUS_UC|MCI_STATUS_DEFERRED|MCI_STATUS_POISON, MCI_STATUS_DEFERRED
On 11/6/2014 10:34 AM, Borislav Petkov wrote:
On Thu, Nov 06, 2014 at 10:26:22AM -0600, Aravind Gopalakrishnan wrote:
diff --git a/arch/x86/include/uapi/asm/msr-index.h
b/arch/x86/include/uapi/asm/msr-index.h
index e21331c..ba7b609 100644
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch
: Len Brown
Cc: Fenghua Yu
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/perf_event.h| 3 +++
arch/x86/include/uapi/asm/msr-index.h| 2 ++
arch/x86/kernel/cpu/perf_event_amd_ibs.c | 15 +++
3 files changed, 20 insertions(+)
diff --git a/arch/x86/include
...@suse.de
Cc: Jan Kiszka jan.kis...@siemens.com
Cc: Len Brown len.br...@intel.com
Cc: Fenghua Yu fenghua...@intel.com
Signed-off-by: Aravind Gopalakrishnan aravind.gopalakrish...@amd.com
---
arch/x86/include/asm/perf_event.h| 3 +++
arch/x86/include/uapi/asm/msr-index.h| 2 ++
arch
On 11/6/2014 10:34 AM, Borislav Petkov wrote:
On Thu, Nov 06, 2014 at 10:26:22AM -0600, Aravind Gopalakrishnan wrote:
diff --git a/arch/x86/include/uapi/asm/msr-index.h
b/arch/x86/include/uapi/asm/msr-index.h
index e21331c..ba7b609 100644
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch
F3 device ID is wrongly included in fam15h_power_id_table
for F16h M30h. It should be F4 device ID. Fix this.
Signed-off-by: Aravind Gopalakrishnan
---
drivers/hwmon/fam15h_power.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/hwmon/fam15h_power.c b/drivers/hwmon
From: Aravind Gopalakrishnan
Extended error code meanings are tabulated for other banks.
Extending that tradition for MC6 in this patch.
Signed-off-by: Aravind Gopalakrishnan
---
drivers/edac/mce_amd.c | 41 +++--
1 file changed, 11 insertions(+), 30
From: Aravind Gopalakrishnan aravind.gopalakrish...@amd.com
Extended error code meanings are tabulated for other banks.
Extending that tradition for MC6 in this patch.
Signed-off-by: Aravind Gopalakrishnan aravind.gopalakrish...@amd.com
---
drivers/edac/mce_amd.c | 41
F3 device ID is wrongly included in fam15h_power_id_table
for F16h M30h. It should be F4 device ID. Fix this.
Signed-off-by: Aravind Gopalakrishnan aravind.gopalakrish...@amd.com
---
drivers/hwmon/fam15h_power.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/hwmon
On 11/3/2014 11:05 AM, Aravind Gopalakrishnan wrote:
There are three ways that have been used to report machine check event.
And they are MCE, CMCI/Threshold Interrupt, and POLL. On the Intel
platform, CMCI/Threshold Interrupt and POLL share the same event handler
- machine_check_poll
On 11/3/2014 11:05 AM, Aravind Gopalakrishnan wrote:
There are three ways that have been used to report machine check event.
And they are MCE, CMCI/Threshold Interrupt, and POLL. On the Intel
platform, CMCI/Threshold Interrupt and POLL share the same event handler
- machine_check_poll
On 10/29/2014 10:59 AM, Aravind Gopalakrishnan wrote:
On 10/22/2014 4:30 AM, Borislav Petkov wrote:
Hi Aravind,
question: what's the story with MC?_MISC[IntP], is that bit still there?
Because I don't see it in my BKDGs here.
Yep, It exists.
Maybe you are referring to Fam15h M0h BKDG? I
On 10/30/2014 7:45 AM, Borislav Petkov wrote:
On Wed, Oct 29, 2014 at 04:18:03PM -0500, Aravind Gopalakrishnan wrote:
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index bbd6514..1092ddd 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -692,9
On 10/30/2014 7:45 AM, Borislav Petkov wrote:
On Wed, Oct 29, 2014 at 04:18:03PM -0500, Aravind Gopalakrishnan wrote:
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index bbd6514..1092ddd 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -692,9
On 10/29/2014 10:59 AM, Aravind Gopalakrishnan wrote:
On 10/22/2014 4:30 AM, Borislav Petkov wrote:
Hi Aravind,
question: what's the story with MC?_MISC[IntP], is that bit still there?
Because I don't see it in my BKDGs here.
Yep, It exists.
Maybe you are referring to Fam15h M0h BKDG? I
he patch by injecting 'ECC' type errors using mce_amd_inj
and error decoding works fine.
Signed-off-by: Aravind Gopalakrishnan
---
Changes in V3
- Re-work per-family low_op for determine_memory_type() as
switch-case
- Rebase work on top of latest tip.git
Changes in V2
- Cache dram_type in a
On 10/22/2014 4:30 AM, Borislav Petkov wrote:
Hi Aravind,
question: what's the story with MC?_MISC[IntP], is that bit still there?
Because I don't see it in my BKDGs here.
Yep, It exists.
Maybe you are referring to Fam15h M0h BKDG? I think the bit was
introduced only from F15h M30h onwards.
On 10/10/2014 12:49 PM, Borislav Petkov wrote:
On Mon, Oct 06, 2014 at 07:04:40PM -0500, Aravind Gopalakrishnan wrote:
This patch adds support for ECC error decoding for F15h M60h processor.
Aside from the usual changes, the patch adds support for some new features
in the processor:
- DDR4
On 10/10/2014 12:49 PM, Borislav Petkov wrote:
On Mon, Oct 06, 2014 at 07:04:40PM -0500, Aravind Gopalakrishnan wrote:
This patch adds support for ECC error decoding for F15h M60h processor.
Aside from the usual changes, the patch adds support for some new features
in the processor:
- DDR4
On 10/22/2014 4:30 AM, Borislav Petkov wrote:
Hi Aravind,
question: what's the story with MC?_MISC[IntP], is that bit still there?
Because I don't see it in my BKDGs here.
Yep, It exists.
Maybe you are referring to Fam15h M0h BKDG? I think the bit was
introduced only from F15h M30h onwards.
by injecting 'ECC' type errors using mce_amd_inj
and error decoding works fine.
Signed-off-by: Aravind Gopalakrishnan aravind.gopalakrish...@amd.com
---
Changes in V3
- Re-work per-family low_op for determine_memory_type() as
switch-case
- Rebase work on top of latest tip.git
Changes in V2
- Cache
On 10/9/2014 12:35 PM, Borislav Petkov wrote:
On Thu, Oct 09, 2014 at 11:53:39AM -0500, Aravind Gopalakrishnan wrote:
How do you mean "last error"?
The interrupt is only fired upon overflow..
And? Think about it, what is causing the overflow? A CE, right?
There was e
On Thu, Oct 09, 2014 at 12:57:50AM +0200, Borislav Petkov wrote:
> On Wed, Oct 08, 2014 at 04:52:06PM -0500, Aravind Gopalakrishnan wrote:
> > I am not understanding why m.bank is assigned this value..
>
> That's a very good question, see below for some history.
>
>
On Thu, Oct 09, 2014 at 12:57:50AM +0200, Borislav Petkov wrote:
On Wed, Oct 08, 2014 at 04:52:06PM -0500, Aravind Gopalakrishnan wrote:
I am not understanding why m.bank is assigned this value..
That's a very good question, see below for some history.
It only causes incorrect
On 10/9/2014 12:35 PM, Borislav Petkov wrote:
On Thu, Oct 09, 2014 at 11:53:39AM -0500, Aravind Gopalakrishnan wrote:
How do you mean last error?
The interrupt is only fired upon overflow..
And? Think about it, what is causing the overflow? A CE, right?
There was even a call
Ok, this return is still bugging me - we're logging the error which
caused the counter overflow but we go and explicitly clear _STATUS so
that machine_check_poll doesn't pick up the same error again.
Even though, machine_check_poll is intended to log the thresholding
error.
Which actually
Ok, this return is still bugging me - we're logging the error which
caused the counter overflow but we go and explicitly clear _STATUS so
that machine_check_poll doesn't pick up the same error again.
Even though, machine_check_poll is intended to log the thresholding
error.
Which actually
ing 'ECC' type errors using mce_amd_inj
and error decoding works fine.
Signed-off-by: Aravind Gopalakrishnan
---
Changes in V2
- Cache dram_type in amd64_pvt structure (per Boris suggestion)
- Introduce per-family low_ops for determine_memory_type() to reduce
number of if-else statements
' type errors using mce_amd_inj
and error decoding works fine.
Signed-off-by: Aravind Gopalakrishnan aravind.gopalakrish...@amd.com
---
Changes in V2
- Cache dram_type in amd64_pvt structure (per Boris suggestion)
- Introduce per-family low_ops for determine_memory_type() to reduce
number
On 10/1/2014 10:45 AM, Borislav Petkov wrote:
On Wed, Oct 01, 2014 at 10:32:58AM -0500, Aravind Gopalakrishnan wrote:
+ if (dcsm & 0x3) {
+ /* LRDIMMs */
+ edac_dbg(1, " DIMM type: LRDIMM %dx rank
On 10/1/2014 10:45 AM, Borislav Petkov wrote:
On Wed, Oct 01, 2014 at 10:32:58AM -0500, Aravind Gopalakrishnan wrote:
+ if (dcsm 0x3) {
+ /* LRDIMMs */
+ edac_dbg(1, DIMM type: LRDIMM %dx rank
multiply
On 10/2/2014 9:52 AM, Borislav Petkov wrote:
On Wed, Oct 01, 2014 at 02:44:21PM -0500, Aravind Gopalakrishnan wrote:
The more I think about this, I'm finding it's hard to do this cleanly.
I initially thought I'd just cache this in pvt->dram_type the first time I'm
doing this.
But, the pvt-&
On 10/2/2014 9:52 AM, Borislav Petkov wrote:
On Wed, Oct 01, 2014 at 02:44:21PM -0500, Aravind Gopalakrishnan wrote:
The more I think about this, I'm finding it's hard to do this cleanly.
I initially thought I'd just cache this in pvt-dram_type the first time I'm
doing this.
But, the pvt-ops
On 10/1/2014 6:32 AM, Borislav Petkov wrote:
On Thu, Sep 18, 2014 at 02:57:10PM -0500, Aravind Gopalakrishnan wrote:
This patch adds support for ECC error decoding for F15h M60h processor.
Aside from the usual changes, the patch adds support for some new features
in the processor:
- DDR4
On 10/1/2014 10:45 AM, Borislav Petkov wrote:
On Wed, Oct 01, 2014 at 10:32:58AM -0500, Aravind Gopalakrishnan wrote:
+ if (dcsm & 0x3) {
+ /* LRDIMMs */
+ edac_dbg(1, " DIMM type: LRDIMM %dx rank
On 10/1/2014 6:32 AM, Borislav Petkov wrote:
On Thu, Sep 18, 2014 at 02:57:10PM -0500, Aravind Gopalakrishnan wrote:
This patch adds support for ECC error decoding for F15h M60h processor.
Aside from the usual changes, the patch adds support for some new features
in the processor:
- DDR4
On 10/1/2014 6:32 AM, Borislav Petkov wrote:
On Thu, Sep 18, 2014 at 02:57:10PM -0500, Aravind Gopalakrishnan wrote:
This patch adds support for ECC error decoding for F15h M60h processor.
Aside from the usual changes, the patch adds support for some new features
in the processor:
- DDR4
On 10/1/2014 10:45 AM, Borislav Petkov wrote:
On Wed, Oct 01, 2014 at 10:32:58AM -0500, Aravind Gopalakrishnan wrote:
+ if (dcsm 0x3) {
+ /* LRDIMMs */
+ edac_dbg(1, DIMM type: LRDIMM %dx rank
multiply
On 10/1/2014 6:32 AM, Borislav Petkov wrote:
On Thu, Sep 18, 2014 at 02:57:10PM -0500, Aravind Gopalakrishnan wrote:
This patch adds support for ECC error decoding for F15h M60h processor.
Aside from the usual changes, the patch adds support for some new features
in the processor:
- DDR4
On 9/26/2014 9:29 AM, Borislav Petkov wrote:
On Fri, Sep 26, 2014 at 10:02:01PM +0800, Jiang Liu wrote:
We plan to restructure x86 interrupt code based on hierarchy irqdomain,
that is to build irqdomains for CPU vector, interrupt remapping unit,
IOAPIC, MSI and HPET etc and organize those
On 9/26/2014 9:29 AM, Borislav Petkov wrote:
On Fri, Sep 26, 2014 at 10:02:01PM +0800, Jiang Liu wrote:
We plan to restructure x86 interrupt code based on hierarchy irqdomain,
that is to build irqdomains for CPU vector, interrupt remapping unit,
IOAPIC, MSI and HPET etc and organize those
On 9/22/2014 9:33 AM, Aravind Gopalakrishnan wrote:
This is a big fat RFC. It takes quite a few liberties with the
multi-core topology level that I'm not completely comfortable
with.
It has only been tested lightly.
Full dmesg for a Cluster-on-Die system with this set applied
On 9/22/2014 9:33 AM, Aravind Gopalakrishnan wrote:
This is a big fat RFC. It takes quite a few liberties with the
multi-core topology level that I'm not completely comfortable
with.
It has only been tested lightly.
Full dmesg for a Cluster-on-Die system with this set applied
Add F3 and F4 PCI device IDs to amd_nb_misc_ids[] and
amd_nb_link_ids[] respectively. We need this to cache the
Northbridges.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/kernel/amd_nb.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel
cleanup:
- amd64_pci_table[] is condensed by using PCI_VDEVICE macro.
Testing details:
Tested the patch by injecting 'ECC' type errors using mce_amd_inj
and error decoding works fine.
Signed-off-by: Aravind Gopalakrishnan
---
drivers/edac/amd64_edac
F15hM60h adds support for DDR4 and DDR3 LRDIMMS. Adding them here.
Signed-off-by: Aravind Gopalakrishnan
---
drivers/edac/edac_mc.c | 3 +++
include/linux/edac.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c
index 9f134823..71fd9fb
Add F3, F4 device IDs to be used in amd_nb.c and amd64_edac.c
Signed-off-by: Aravind Gopalakrishnan
---
include/linux/pci_ids.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index aa0d390..6a2a72a 100644
--- a/include/linux/pci_ids.h
Northbridges
for later use in amd64_edac
- Patch 3: F15hM60h adds support for DDR4 and DDR3 LRDIMMS. Adding them here.
- Patch 4: Adds bulk of the code necessary to support F15hM60h.
Also introduces a change to dbam_to_cs mapper functions.
Aravind Gopalakrishnan (4):
pci_ids
Northbridges
for later use in amd64_edac
- Patch 3: F15hM60h adds support for DDR4 and DDR3 LRDIMMS. Adding them here.
- Patch 4: Adds bulk of the code necessary to support F15hM60h.
Also introduces a change to dbam_to_cs mapper functions.
Aravind Gopalakrishnan (4
Add F3, F4 device IDs to be used in amd_nb.c and amd64_edac.c
Signed-off-by: Aravind Gopalakrishnan aravind.gopalakrish...@amd.com
---
include/linux/pci_ids.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index aa0d390..6a2a72a 100644
F15hM60h adds support for DDR4 and DDR3 LRDIMMS. Adding them here.
Signed-off-by: Aravind Gopalakrishnan aravind.gopalakrish...@amd.com
---
drivers/edac/edac_mc.c | 3 +++
include/linux/edac.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/drivers/edac/edac_mc.c b/drivers/edac
Add F3 and F4 PCI device IDs to amd_nb_misc_ids[] and
amd_nb_link_ids[] respectively. We need this to cache the
Northbridges.
Signed-off-by: Aravind Gopalakrishnan aravind.gopalakrish...@amd.com
---
arch/x86/kernel/amd_nb.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/kernel
:
- amd64_pci_table[] is condensed by using PCI_VDEVICE macro.
Testing details:
Tested the patch by injecting 'ECC' type errors using mce_amd_inj
and error decoding works fine.
Signed-off-by: Aravind Gopalakrishnan aravind.gopalakrish...@amd.com
---
drivers/edac/amd64_edac.c | 226
Fam16h,M30h(Mullins) and Fam15hM30h(Kaveri) processors can
report 'power_crit' value. So, adding their respective device ids.
Signed-off-by: Aravind Gopalakrishnan
---
drivers/hwmon/fam15h_power.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/hwmon/fam15h_power.c b/drivers/hwmon
dev_attr_power1_input.attr for comparison rather than
string comparison.
- Fix minor style issue.
[Patch 2/2] is functionality extension.
- Add PCI IDs for Fam16h,M30h(Mullins) and Fam15hM30h(Kaveri)
to report power1_crit values
Aravind Gopalakrishnan (2):
hwmon, fam15h_power: Make actual power reporting
power1_input should only be reported for Fam15h, Models 00h-0fh
So, introduce a is_visible function to take care of this.
As suggested by Guenter here:
http://marc.info/?l=linux-kernel=141038145616437=2
Suggested-by: Guenter Roeck
Signed-off-by: Aravind Gopalakrishnan
---
drivers/hwmon
On 9/16/2014 10:52 AM, Guenter Roeck wrote:
On Tue, Sep 16, 2014 at 10:38:38AM -0500, Aravind Gopalakrishnan wrote:
power1_input should only be reported for Fam15h, Models 00h-0fh
So, introduce a is_visible function to take care of this.
As suggested by Guenter here:
http://marc.info/?l=linux
power1_input should only be reported for Fam15h, Models 00h-0fh
So, introduce a is_visible function to take care of this.
As suggested by Guenter here:
http://marc.info/?l=linux-kernel=141038145616437=2
Suggested-by: Guenter Roeck
Signed-off-by: Aravind Gopalakrishnan
---
drivers/hwmon
.
- Add PCI IDs for Fam16h,M30h(Mullins) and Fam15hM30h(Kaveri)
to report power1_crit values
Aravind Gopalakrishnan (2):
hwmon, fam15h_power: Make actual power reporting conditional
hwmon, fam15h_power: Add support for two more processors
drivers/hwmon/fam15h_power.c | 21
Fam16h,M30h(Mullins) and Fam15hM30h(Kaveri) processors can
report 'power_crit' value. So, adding their respective device ids.
Signed-off-by: Aravind Gopalakrishnan
---
drivers/hwmon/fam15h_power.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/hwmon/fam15h_power.c b/drivers/hwmon
power1_input should only be reported for Fam15h, Models 00h-0fh
So, introduce a is_visible function to take care of this.
As suggested by Guenter here:
http://marc.info/?l=linux-kernelm=141038145616437w=2
Suggested-by: Guenter Roeck li...@roeck-us.net
Signed-off-by: Aravind Gopalakrishnan
Fam16h,M30h(Mullins) and Fam15hM30h(Kaveri) processors can
report 'power_crit' value. So, adding their respective device ids.
Signed-off-by: Aravind Gopalakrishnan aravind.gopalakrish...@amd.com
---
drivers/hwmon/fam15h_power.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/hwmon
.
- Add PCI IDs for Fam16h,M30h(Mullins) and Fam15hM30h(Kaveri)
to report power1_crit values
Aravind Gopalakrishnan (2):
hwmon, fam15h_power: Make actual power reporting conditional
hwmon, fam15h_power: Add support for two more processors
drivers/hwmon/fam15h_power.c | 21
On 9/16/2014 10:52 AM, Guenter Roeck wrote:
On Tue, Sep 16, 2014 at 10:38:38AM -0500, Aravind Gopalakrishnan wrote:
power1_input should only be reported for Fam15h, Models 00h-0fh
So, introduce a is_visible function to take care of this.
As suggested by Guenter here:
http://marc.info/?l=linux
power1_input should only be reported for Fam15h, Models 00h-0fh
So, introduce a is_visible function to take care of this.
As suggested by Guenter here:
http://marc.info/?l=linux-kernelm=141038145616437w=2
Suggested-by: Guenter Roeck li...@roeck-us.net
Signed-off-by: Aravind Gopalakrishnan
dev_attr_power1_input.attr for comparison rather than
string comparison.
- Fix minor style issue.
[Patch 2/2] is functionality extension.
- Add PCI IDs for Fam16h,M30h(Mullins) and Fam15hM30h(Kaveri)
to report power1_crit values
Aravind Gopalakrishnan (2):
hwmon, fam15h_power: Make actual power reporting
Fam16h,M30h(Mullins) and Fam15hM30h(Kaveri) processors can
report 'power_crit' value. So, adding their respective device ids.
Signed-off-by: Aravind Gopalakrishnan aravind.gopalakrish...@amd.com
---
drivers/hwmon/fam15h_power.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/hwmon
From: Aravind Gopalakrishnan
Rationale behind this change:
- F2x1xx addresses were stopped from being mapped explicitly to DCT1
from F15h (OR) onwards. They use _dct[0:1] mechanism to access the
registers. So we should move away from using address ranges to select
DCT
On 9/15/2014 10:08 AM, Borislav Petkov wrote:
amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, >online_spare);
- amd64_read_dct_pci_cfg(pvt, DCLR0, >dclr0);
- amd64_read_dct_pci_cfg(pvt, DCHR0, >dchr0);
-
- if (!dct_ganging_enabled(pvt)) {
-
On 9/15/2014 7:09 AM, Borislav Petkov wrote:
On Tue, Sep 09, 2014 at 02:52:26PM -0500, Aravind Gopalakrishnan wrote:
Rationale behind this change:
- F2x1xx addresses were stopped from being mapped explicitly to DCT1
from F15h (OR) onwards. They use _dct[0:1] mechanism to access
On 9/15/2014 7:09 AM, Borislav Petkov wrote:
On Tue, Sep 09, 2014 at 02:52:26PM -0500, Aravind Gopalakrishnan wrote:
Rationale behind this change:
- F2x1xx addresses were stopped from being mapped explicitly to DCT1
from F15h (OR) onwards. They use _dct[0:1] mechanism to access
On 9/15/2014 10:08 AM, Borislav Petkov wrote:
amd64_read_pci_cfg(pvt-F3, F10_ONLINE_SPARE, pvt-online_spare);
- amd64_read_dct_pci_cfg(pvt, DCLR0, pvt-dclr0);
- amd64_read_dct_pci_cfg(pvt, DCHR0, pvt-dchr0);
-
- if (!dct_ganging_enabled(pvt)) {
-
From: Aravind Gopalakrishnan aravind.gopalakrish...@amd.com
Rationale behind this change:
- F2x1xx addresses were stopped from being mapped explicitly to DCT1
from F15h (OR) onwards. They use _dct[0:1] mechanism to access the
registers. So we should move away from using address ranges
On 9/10/2014 3:37 PM, Guenter Roeck wrote:
On Wed, Sep 10, 2014 at 03:01:36PM -0500, Aravind Gopalakrishnan wrote:
On 9/10/2014 12:53 PM, Guenter Roeck wrote:
On Wed, Sep 10, 2014 at 12:02:08PM -0500, Aravind Gopalakrishnan wrote:
Fam16h,M30h(Mullins) and Fam15hM30h(Kaveri) processors can
On 9/10/2014 12:53 PM, Guenter Roeck wrote:
On Wed, Sep 10, 2014 at 12:02:08PM -0500, Aravind Gopalakrishnan wrote:
Fam16h,M30h(Mullins) and Fam15hM30h(Kaveri) processors can
report 'power_crit' value. So, adding their respective device ids.
Also, according to BKDGs, the 'TdpRunAvgAccCap
error if we are on any other family/model.
Impact on lm-sensors is minimal. On such families, instead of reporting
Current power value as '0', we now have:
power1: N/A
Signed-off-by: Aravind Gopalakrishnan
---
drivers/hwmon/fam15h_power.c | 6 ++
1 file changed, 6 insertions
error if we are on any other family/model.
Impact on lm-sensors is minimal. On such families, instead of reporting
Current power value as '0', we now have:
power1: N/A
Signed-off-by: Aravind Gopalakrishnan aravind.gopalakrish...@amd.com
---
drivers/hwmon/fam15h_power.c | 6 ++
1
On 9/10/2014 12:53 PM, Guenter Roeck wrote:
On Wed, Sep 10, 2014 at 12:02:08PM -0500, Aravind Gopalakrishnan wrote:
Fam16h,M30h(Mullins) and Fam15hM30h(Kaveri) processors can
report 'power_crit' value. So, adding their respective device ids.
Also, according to BKDGs, the 'TdpRunAvgAccCap
On 9/10/2014 3:37 PM, Guenter Roeck wrote:
On Wed, Sep 10, 2014 at 03:01:36PM -0500, Aravind Gopalakrishnan wrote:
On 9/10/2014 12:53 PM, Guenter Roeck wrote:
On Wed, Sep 10, 2014 at 12:02:08PM -0500, Aravind Gopalakrishnan wrote:
Fam16h,M30h(Mullins) and Fam15hM30h(Kaveri) processors can
401 - 500 of 642 matches
Mail list logo
