On 09/22/12 11:10, Nicolas Pitre wrote:
On Fri, 21 Sep 2012, Cyril Chemparathy wrote:
The original phys_to_virt/virt_to_phys patching implementation relied on early
patching prior to MMU initialization. On PAE systems running out of 4G
address space, this would have entailed an additional
On 09/24/12 09:38, Russell King - ARM Linux wrote:
On Fri, Sep 21, 2012 at 11:56:07AM -0400, Cyril Chemparathy wrote:
From: Vitaly Andrianov vita...@ti.com
This patch fixes the initrd setup code to use phys_addr_t instead of assuming
32-bit addressing. Without this we cannot boot on systems
Hi Dave,
Thanks for the detailed review...
On 9/24/2012 8:06 AM, Dave Martin wrote:
On Fri, Sep 21, 2012 at 11:55:59AM -0400, Cyril Chemparathy wrote:
The original phys_to_virt/virt_to_phys patching implementation relied on early
patching prior to MMU initialization. On PAE systems running
On 02/04/2013 12:02 PM, Felipe Balbi wrote:
Hi,
On Mon, Feb 04, 2013 at 08:54:17PM +0300, Sergei Shtylyov wrote:
On Mon, Feb 04, 2013 at 08:36:38PM +0300, Sergei Shtylyov wrote:
opted out of it. From the top of my head we have CPPI 3.x, CPPI 4.1,
Inventra DMA, OMAP sDMA and ux500 DMA engines
On 02/04/2013 04:11 PM, Linus Walleij wrote:
On Mon, Feb 4, 2013 at 9:33 PM, Mark Brown
broo...@opensource.wolfsonmicro.com wrote:
On Mon, Feb 04, 2013 at 09:29:46PM +0100, Linus Walleij wrote:
On Mon, Feb 4, 2013 at 8:22 PM, Cyril Chemparathy cy...@ti.com wrote:
Based on our experience
On 02/04/2013 03:29 PM, Linus Walleij wrote:
On Mon, Feb 4, 2013 at 8:22 PM, Cyril Chemparathy cy...@ti.com wrote:
Based on our experience with fitting multiple subsystems on top of this
DMA-Engine driver, I must say that the DMA-Engine interface has proven
to be a less than ideal fit
On 02/05/2013 07:38 AM, Russell King - ARM Linux wrote:
On Mon, Feb 04, 2013 at 09:47:38PM +, Arnd Bergmann wrote:
On Monday 04 February 2013, Linus Walleij wrote:
So I think the above concerns are moot. The callback we can
set on cookies is entirely optional, and it's even implemented by
On 02/05/2013 07:41 AM, Russell King - ARM Linux wrote:
On Mon, Feb 04, 2013 at 04:54:45PM -0500, Cyril Chemparathy wrote:
You're assuming that cookies complete in order. That is not necessarily
true.
Under what circumstances is that not true?
Notably when hardware can prioritize certain
On 02/05/2013 01:29 PM, Linus Walleij wrote:
On Tue, Feb 5, 2013 at 5:47 PM, Mark Brown
broo...@opensource.wolfsonmicro.com wrote:
On Tue, Feb 05, 2013 at 05:21:48PM +0100, Linus Walleij wrote:
For IRQ mode, use the completion callback to push each cookie
to NAPI, and thus let the IRQ drive
This patch adds an architecture defined override for ARCH_LOW_ADDRESS_LIMIT.
On PAE systems, the absence of this override causes bootmem to incorrectly
limit itself to 32-bit addressable physical memory.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
This patch redefines the early boot time use of the R4 register to steal a few
low order bits (ARCH_PGD_SHIFT bits) on LPAE systems. This allows for up to
38-bit physical addresses.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
---
arch/arm/include
This patch modifies the switch_mm() processor functions to use phys_addr_t.
On LPAE systems, we now honor the upper 32-bits of the physical address that
is being passed in, and program these into TTBR as expected.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita
This patch moves the TTBR1 offset calculation and the T1SZ calculation out
of the TTB setup assembly code. This should not affect functionality in
any way, but improves code readability as well as readability of subsequent
patches in this series.
Signed-off-by: Cyril Chemparathy cy...@ti.com
for membank overlap with
[12/13] ARM: mm: clean up membank size limit checks
(v4) unchanged from v3
(v3) unchanged from v2
(v2) unchanged from v1
[13/13] ARM: fix type of PHYS_PFN_OFFSET to unsigned long
(v4) introduced here
Cyril Chemparathy (10):
ARM: LPAE: use signed arithmetic
be mapped in
a monotonically increasing fashion if there are multiple banks of memory,
i.e., x y must = pa(x) pa(y).
Signed-off-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
Acked-by: Nicolas Pitre n...@linaro.org
---
arch/arm/mm/mmu.c | 22
thing.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
Reviewed-by: Nicolas Pitre n...@linaro.org
Reviewed-by: Catalin Marinas catalin.mari...@arm.com
---
arch/arm/include/asm/page.h |2 +-
arch/arm/include/asm/pgtable-3level.h |6
.
Signed-off-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Cyril Chemparathy cy...@ti.com
Acked-by: Nicolas Pitre n...@linaro.org
---
arch/arm/mm/init.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index ad722f1..1c5151a 100644
'long
unsigned int', but argument 2 has type 'phys_addr_t' [-Wformat]
This patch fixes this warning by pinning down the PFN type to unsigned long.
Signed-off-by: Cyril Chemparathy cy...@ti.com
---
arch/arm/include/asm/memory.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
), which applied similar changes
elsewhere in the ARM memory management code.
Signed-off-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Cyril Chemparathy cy...@ti.com
Acked-by: Nicolas Pitre n...@linaro.org
Acked-by: Catalin Marinas catalin.mari...@arm.com
---
arch/arm/mm/mmu.c |3 ++-
1 file
by the !highmem condition.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
Acked-by: Nicolas Pitre n...@linaro.org
---
arch/arm/mm/mmu.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm
-by: Cyril Chemparathy cy...@ti.com
Acked-by: Nicolas Pitre n...@linaro.org
Acked-by: Catalin Marinas catalin.mari...@arm.com
---
arch/arm/mm/init.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 1c5151a..87ee0ec 100644
-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
Acked-by: Nicolas Pitre n...@linaro.org
Reviewed-by: Catalin Marinas catalin.mari...@arm.com
---
arch/arm/include/asm/proc-fns.h | 22 +-
arch/arm/mm/context.c |9 ++---
2 files
) by
checking bank-start against the physical address corresponding to vmalloc_min
instead.
In the process, this patch also cleans up parts of the highmem sanity check
code by removing what has now become a redundant check for banks that entirely
overlap with the vmalloc range.
Signed-off-by: Cyril
Hi Nico,
On 01/31/2013 11:00 PM, Nicolas Pitre wrote:
On Thu, 31 Jan 2013, Cyril Chemparathy wrote:
This series is a repost of the LPAE related changes in preparation for the
introduction of the Keystone sub-architecture. The original series has now
been split, and this particular series
On 02/01/2013 10:14 AM, Russell King - ARM Linux wrote:
On Fri, Feb 01, 2013 at 10:10:37AM -0500, Cyril Chemparathy wrote:
With this, I ran simple network and filesystem performance tests to
compare the code-patching vs. non-code-patching variants. These tests
didn't yield any significant
On 02/01/2013 12:33 PM, Subash Patel wrote:
Hi Nicolas,
On Thursday 31 January 2013 07:35 PM, Nicolas Pitre wrote:
On Fri, 1 Feb 2013, Hui Wang wrote:
Cyril Chemparathy wrote:
From: Vitaly Andrianov vita...@ti.com
This patch fixes the alloc_init_pud() function to use phys_addr_t
instead
On 8/12/2012 12:36 AM, Nicolas Pitre wrote:
On Fri, 10 Aug 2012, Cyril Chemparathy wrote:
On Keystone platforms, physical memory is entirely outside the 32-bit
addressible range. Therefore, the (bank-start ULONG_MAX) check below marks
the entire system memory as highmem, and this causes
thing.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
Reviewed-by: Nicolas Pitre n...@linaro.org
---
arch/arm/include/asm/page.h |2 +-
arch/arm/include/asm/pgtable-3level.h |6 +++---
2 files changed, 4 insertions(+), 4 deletions
This patch redefines the early boot time use of the R4 register to steal a few
low order bits (ARCH_PGD_SHIFT bits) on LPAE systems. This allows for up to
38-bit physical addresses.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
---
arch/arm/include
.
Signed-off-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Cyril Chemparathy cy...@ti.com
Acked-by: Nicolas Pitre n...@linaro.org
---
arch/arm/mm/init.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 9aec41f..19ba70b 100644
) by
checking bank-start against the physical address corresponding to vmalloc_min
instead.
In the process, this patch also cleans up parts of the highmem sanity check
code by removing what has now become a redundant check for banks that entirely
overlap with the vmalloc range.
Signed-off-by: Cyril
(17/22) ARM: mm: clean up membank size limit checks
(v3) unchanged from v2
(v2) unchanged from v1
Cyril Chemparathy (14):
ARM: add mechanism for late code patching
ARM: add self test for runtime patch mechanism
ARM: use late patch framework for phys-virt patching
ARM: LPAE: use
This patch adds an architecture defined override for ARCH_LOW_ADDRESS_LIMIT.
On PAE systems, the absence of this override causes bootmem to incorrectly
limit itself to 32-bit addressable physical memory.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
Acked-by: Nicolas Pitre n...@linaro.org
---
arch/arm/include/asm/proc-fns.h | 24 +++-
arch/arm/mm/context.c |9 ++---
2 files changed, 21 insertions(+), 12 deletions(-)
diff --git
computations on the upper 32-bits would be discarded anyway.
Signed-off-by: Cyril Chemparathy cy...@ti.com
---
arch/arm/include/asm/memory.h | 38 --
arch/arm/kernel/head.S|4
arch/arm/kernel/setup.c |2 +-
3 files changed, 41 insertions
), which applied similar changes
elsewhere in the ARM memory management code.
Signed-off-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Cyril Chemparathy cy...@ti.com
Acked-by: Nicolas Pitre n...@linaro.org
---
arch/arm/mm/mmu.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
This patch fixes up the types used when converting back and forth between
physical and virtual addresses.
Signed-off-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Cyril Chemparathy cy...@ti.com
Reviewed-by: Nicolas Pitre n...@linaro.org
---
arch/arm/include/asm/memory.h | 26
by the !highmem condition.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
---
arch/arm/mm/mmu.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index e631f73..794457a 100644
-by: Cyril Chemparathy cy...@ti.com
Acked-by: Nicolas Pitre n...@linaro.org
---
arch/arm/mm/init.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 19ba70b..bae9d05 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
This patch modifies the switch_mm() processor functions to use phys_addr_t.
On LPAE systems, we now honor the upper 32-bits of the physical address that
is being passed in, and program these into TTBR as expected.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita
' modifier has been found to ICE certain versions of GCC, and
therefore we resort to stringified symbols here.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Reviewed-by: Nicolas Pitre n...@linaro.org
---
arch/arm/Kconfig |3 +
arch/arm/include/asm/module.h|7
This patch replaces the original physical offset patching implementation
with one that uses the newly added patching framework.
Signed-off-by: Cyril Chemparathy cy...@ti.com
---
arch/arm/Kconfig |1 +
arch/arm/include/asm/memory.h | 26 +++
arch/arm/kernel/armksyms.c
This patch moves the TTBR1 offset calculation and the T1SZ calculation out
of the TTB setup assembly code. This should not affect functionality in
any way, but improves code readability as well as readability of subsequent
patches in this series.
Signed-off-by: Cyril Chemparathy cy...@ti.com
This patch adds basic sanity tests to ensure that the instruction patching
results in valid instruction encodings. This is done by verifying the output
of the patch process against a vector of assembler generated instructions at
init time.
Signed-off-by: Cyril Chemparathy cy...@ti.com
---
arch
be mapped in
a monotonically increasing fashion if there are multiple banks of memory,
i.e., x y must = pa(x) pa(y).
Signed-off-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
Acked-by: Nicolas Pitre n...@linaro.org
---
arch/arm/mm/mmu.c | 22
On 9/21/2012 1:40 PM, Nicolas Pitre wrote:
On Tue, 11 Sep 2012, Cyril Chemparathy wrote:
This patch adds basic sanity tests to ensure that the instruction patching
results in valid instruction encodings. This is done by verifying the output
of the patch process against a vector of assembler
On 9/21/2012 2:09 PM, Nicolas Pitre wrote:
On Tue, 11 Sep 2012, Cyril Chemparathy wrote:
The original phys_to_virt/virt_to_phys patching implementation relied on early
patching prior to MMU initialization. On PAE systems running out of 4G
address space, this would have entailed an additional
On 9/21/2012 2:42 PM, Nicolas Pitre wrote:
On Tue, 11 Sep 2012, Cyril Chemparathy wrote:
This patch cleans up the highmem sanity check code by simplifying the range
checks with a pre-calculated size_limit. This patch should otherwise have no
functional impact on behavior.
This patch also
.
Signed-off-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Cyril Chemparathy cy...@ti.com
Acked-by: Nicolas Pitre n...@linaro.org
---
arch/arm/mm/init.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index ad722f1..1c5151a 100644
This patch fixes up the types used when converting back and forth between
physical and virtual addresses.
Signed-off-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Cyril Chemparathy cy...@ti.com
Reviewed-by: Nicolas Pitre n...@linaro.org
---
arch/arm/include/asm/memory.h | 26
-by: Cyril Chemparathy cy...@ti.com
Acked-by: Nicolas Pitre n...@linaro.org
---
arch/arm/mm/init.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 1c5151a..87ee0ec 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
This patch adds basic sanity tests to ensure that the instruction patching
results in valid instruction encodings. This is done by verifying the output
of the patch process against a vector of assembler generated instructions at
init time.
Signed-off-by: Cyril Chemparathy cy...@ti.com
---
arch
), which applied similar changes
elsewhere in the ARM memory management code.
Signed-off-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Cyril Chemparathy cy...@ti.com
Acked-by: Nicolas Pitre n...@linaro.org
---
arch/arm/mm/mmu.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
checks
(16/22) ARM: mm: cleanup checks for membank overlap with vmalloc area
(17/22) ARM: mm: clean up membank size limit checks
(v3) unchanged from v2
(v2) unchanged from v1
Cyril Chemparathy (14):
ARM: add mechanism for late code patching
ARM: add self test for runtime patch mechanism
' modifier has been found to ICE certain versions of GCC, and
therefore we resort to stringified symbols here.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Reviewed-by: Nicolas Pitre n...@linaro.org
---
arch/arm/Kconfig |3 +
arch/arm/include/asm/module.h|7
This patch replaces the original physical offset patching implementation
with one that uses the newly added patching framework.
Signed-off-by: Cyril Chemparathy cy...@ti.com
---
arch/arm/Kconfig |1 +
arch/arm/include/asm/memory.h | 26 +++
arch/arm/kernel/armksyms.c
-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
Acked-by: Nicolas Pitre n...@linaro.org
---
arch/arm/include/asm/proc-fns.h | 24 +++-
arch/arm/mm/context.c |9 ++---
2 files changed, 21 insertions(+), 12 deletions(-)
diff --git
) by
checking bank-start against the physical address corresponding to vmalloc_min
instead.
In the process, this patch also cleans up parts of the highmem sanity check
code by removing what has now become a redundant check for banks that entirely
overlap with the vmalloc range.
Signed-off-by: Cyril
be mapped in
a monotonically increasing fashion if there are multiple banks of memory,
i.e., x y must = pa(x) pa(y).
Signed-off-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
Acked-by: Nicolas Pitre n...@linaro.org
---
arch/arm/mm/mmu.c | 22
This patch redefines the early boot time use of the R4 register to steal a few
low order bits (ARCH_PGD_SHIFT bits) on LPAE systems. This allows for up to
38-bit physical addresses.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
---
arch/arm/include
computations on the upper 32-bits would be discarded anyway.
Signed-off-by: Cyril Chemparathy cy...@ti.com
---
arch/arm/include/asm/memory.h | 38 --
arch/arm/kernel/head.S|4
arch/arm/kernel/setup.c |2 +-
3 files changed, 41 insertions
This patch modifies the switch_mm() processor functions to use phys_addr_t.
On LPAE systems, we now honor the upper 32-bits of the physical address that
is being passed in, and program these into TTBR as expected.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita
This patch moves the TTBR1 offset calculation and the T1SZ calculation out
of the TTB setup assembly code. This should not affect functionality in
any way, but improves code readability as well as readability of subsequent
patches in this series.
Signed-off-by: Cyril Chemparathy cy...@ti.com
This patch adds an architecture defined override for ARCH_LOW_ADDRESS_LIMIT.
On PAE systems, the absence of this override causes bootmem to incorrectly
limit itself to 32-bit addressable physical memory.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
thing.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
Reviewed-by: Nicolas Pitre n...@linaro.org
---
arch/arm/include/asm/page.h |2 +-
arch/arm/include/asm/pgtable-3level.h |6 +++---
2 files changed, 4 insertions(+), 4 deletions
by the !highmem condition.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
---
arch/arm/mm/mmu.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 6c35483..50d9df5 100644
'long
unsigned int', but argument 2 has type 'phys_addr_t' [-Wformat]
This patch fixes this warning by pinning down the PFN type to unsigned long.
Signed-off-by: Cyril Chemparathy cy...@ti.com
---
arch/arm/include/asm/memory.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
is to promote the initialization of offset into do_alignment().
Signed-off-by: Cyril Chemparathy cy...@ti.com
---
arch/arm/mm/alignment.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 9107231..d15877c 100644
--- a/arch/arm
This patch fixes the /dev/mem driver to use phys_addr_t for physical
addresses. This is required on PAE systems, especially those that run
entirely out of 4G physical memory space.
---
arch/arm/include/asm/io.h |2 +-
arch/arm/mm/mmap.c |2 +-
arch/ia64/include/asm/io.h |2
On some PAE architectures, the entire range of physical memory could reside
outside the 32-bit limit. These systems need the ability to specify the
initrd location using 64-bit numbers.
This patch globally modifies the early_init_dt_setup_initrd_arch() function to
use 64-bit numbers instead of
guidance towards a better solution to this
problem.
Signed-off-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Cyril Chemparathy cy...@ti.com
---
include/linux/bootmem.h | 30
mm/bootmem.c| 59 ---
2 files changed
On 9/12/2012 12:16 PM, Geert Uytterhoeven wrote:
On Wed, Sep 12, 2012 at 6:05 PM, Cyril Chemparathy cy...@ti.com wrote:
On some PAE architectures, the entire range of physical memory could reside
outside the 32-bit limit. These systems need the ability to specify the
initrd location using 64
This patch fixes the /dev/mem driver to use phys_addr_t for physical
addresses. This is required on PAE systems, especially those that run
entirely out of 4G physical memory space.
Signed-off-by: Cyril Chemparathy cy...@ti.com
---
arch/arm/include/asm/io.h |2 +-
arch/arm/mm/mmap.c
This patch adds a check for the presence of the channel controller when
trying to allocate a slot. Without this fix, the kernel panics with a NULL
pointer dereference when the dma-engine drivers are probed.
Signed-off-by: Cyril Chemparathy cy...@ti.com
---
arch/arm/mach-davinci/dma.c |3
Greg,
On 9/12/2012 2:15 PM, Greg KH wrote:
On Wed, Sep 12, 2012 at 02:05:58PM -0400, Cyril Chemparathy wrote:
This patch fixes the /dev/mem driver to use phys_addr_t for physical
addresses. This is required on PAE systems, especially those that run
entirely out of 4G physical memory space
On 9/12/2012 4:23 PM, Rob Herring wrote:
On 09/12/2012 11:05 AM, Cyril Chemparathy wrote:
On some PAE architectures, the entire range of physical memory could reside
outside the 32-bit limit. These systems need the ability to specify the
initrd location using 64-bit numbers.
This patch
Hi Tejun,
On 9/12/2012 4:39 PM, Tejun Heo wrote:
Hello,
On Wed, Sep 12, 2012 at 12:06:48PM -0400, Cyril Chemparathy wrote:
static void * __init alloc_bootmem_core(unsigned long size,
unsigned long align
Hi Tejun,
On 9/12/2012 8:34 PM, Tejun Heo wrote:
Hello,
On Wed, Sep 12, 2012 at 08:08:30PM -0400, Cyril Chemparathy wrote:
So, a function which takes phys_addr_t for goal and limit but returns
void * doesn't make much sense unless the function creates directly
addressable mapping somewhere
This patch fixes an apparent bug in the running weighted average calculation
used in the RED algorithm.
Going by the described formula:
qavg = qavg*(1-W) + backlog*W
= qavg = qavg + (backlog - qavg) * W
... with W converted to a pre-calculated shift, this then becomes:
Hi Catalin,
On 7/24/2012 6:05 AM, Catalin Marinas wrote:
On Tue, Jul 24, 2012 at 02:09:04AM +0100, Cyril Chemparathy wrote:
This patch applies to PAGE_MASK, PMD_MASK, and PGDIR_MASK, where forcing
unsigned long math truncates the mask at the 32-bits. This clearly does bad
things on PAE
Hi Nicolas,
On 8/4/2012 1:38 AM, Nicolas Pitre wrote:
[...]
extern unsigned __patch_table_begin, __patch_table_end;
You could use exttern void __patch_table_begin so those symbols don't
get any type that could be misused by mistake, while you still can take
their addresses.
Looks like
On 08/08/12 01:56, Nicolas Pitre wrote:
On Tue, 7 Aug 2012, Cyril Chemparathy wrote:
[...]
u32 arm_check[] = {
0xe2810041, 0xe2810082, 0xe2810f41, 0xe2810f82, 0xe2810e41,
0xe2810e82, 0xe2810d41, 0xe2810d82, 0xe2810c41, 0xe2810c82,
0xe2810b41, 0xe2810b82, 0xe2810a41
Hi Russell,
On 8/6/2012 7:14 AM, Russell King - ARM Linux wrote:
On Tue, Jul 31, 2012 at 07:04:39PM -0400, Cyril Chemparathy wrote:
This patch fixes up the types used when converting back and forth between
physical and virtual addresses.
Signed-off-by: Vitaly Andrianov vita...@ti.com
Signed
This patch redefines the early boot time use of the R4 register to steal a few
low order bits (ARCH_PGD_SHIFT bits) on LPAE systems. This allows for up to
38-bit physical addresses.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
---
arch/arm/include
by the !highmem condition.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
---
arch/arm/mm/mmu.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 3d685c6..662684b 100644
This patch adds an architecture defined override for ARCH_LOW_ADDRESS_LIMIT.
On PAE systems, the absence of this override causes bootmem to incorrectly
limit itself to 32-bit addressable physical memory.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
This patch modifies the switch_mm() processor functions to use phys_addr_t.
On LPAE systems, we now honor the upper 32-bits of the physical address that
is being passed in, and program these into TTBR as expected.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita
physical memory addressing capabilities via LPAE.
Signed-off-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Cyril Chemparathy cy...@ti.com
Reviewed-by: Arnd Bergmann a...@arndb.de
---
arch/arm/Kconfig | 18 +
arch/arm/Makefile
computations on the upper 32-bits would be discarded anyway.
Signed-off-by: Cyril Chemparathy cy...@ti.com
---
arch/arm/include/asm/memory.h | 22 ++
arch/arm/kernel/head.S|4
arch/arm/kernel/setup.c |2 +-
3 files changed, 23 insertions(+), 5 deletions
a machine descriptor
hook that allows the PHYS_OFFSET to be overridden in a machine specific
fashion.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
---
arch/arm/include/asm/mach/arch.h |1 +
arch/arm/kernel/setup.c |3 ++
arch/arm/mm/mmu.c
be mapped in
a monotonically increasing fashion if there are multiple banks of memory,
i.e., x y must = pa(x) pa(y).
Signed-off-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
---
arch/arm/mm/mmu.c | 22 ++
1 file changed, 10 insertions
' modifier has been found to ICE certain versions of GCC, and
therefore we resort to stringified symbols here.
Signed-off-by: Cyril Chemparathy cy...@ti.com
---
arch/arm/Kconfig |3 +
arch/arm/include/asm/module.h|7 ++
arch/arm/include/asm/runtime-patch.h | 175
This patch fixes up the types used when converting back and forth between
physical and virtual addresses.
Signed-off-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Cyril Chemparathy cy...@ti.com
---
arch/arm/include/asm/memory.h | 26 ++
1 file changed, 18
This patch moves the TTBR1 offset calculation and the T1SZ calculation out
of the TTB setup assembly code. This should not affect functionality in
any way, but improves code readability as well as readability of subsequent
patches in this series.
Signed-off-by: Cyril Chemparathy cy...@ti.com
), which applied similar changes
elsewhere in the ARM memory management code.
Signed-off-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Cyril Chemparathy cy...@ti.com
Acked-by: Nicolas Pitre n...@linaro.org
---
arch/arm/mm/mmu.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
This patch replaces the original physical offset patching implementation
with one that uses the newly added patching framework. In the process, we now
unconditionally initialize the __pv_phys_offset and __pv_offset globals in the
head.S code.
Signed-off-by: Cyril Chemparathy cy...@ti.com
This series is a follow on to the series posted earlier (archived at [1]).
Patches 01/22 .. 09/22 of this series have been pretty intensively reviewed;
thanks to all who helped. We've modified per feedback, and these should be in
reasonable shape.
Patches 10/22 .. 19/22 of this series have not
...@ti.com
Signed-off-by: Cyril Chemparathy cy...@ti.com
---
arch/arm/Kconfig |1 +
arch/arm/boot/dts/keystone-sim.dts |8 +++---
arch/arm/configs/keystone_defconfig |1 +
arch/arm/mach-keystone/include/mach/memory.h | 25
) by
checking bank-start against the physical address corresponding to vmalloc_min
instead.
In the process, this patch also cleans up parts of the highmem sanity check
code by removing what has now become a redundant check for banks that entirely
overlap with the vmalloc range.
Signed-off-by: Cyril
-by: Cyril Chemparathy cy...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
---
arch/arm/include/asm/proc-fns.h | 24 +++-
arch/arm/mm/context.c |9 ++---
2 files changed, 21 insertions(+), 12 deletions(-)
diff --git a/arch/arm/include/asm/proc-fns.h b/arch
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