Re: [PATCH] x86_64 RESTORE_CONTEXT missing '\n'

Andi Kleen wrote: On Wednesday 07 March 2007 21:45, Dave Jiang wrote: The RESTORE_CONTEXT macro is missing the '\n' at the end. It was removed in the previous patch that touched system.h. It causes compile failure if any inline asm is added after the macro. Discovered this when playing

[PATCH] MPSC serial driver tx locking

transmit lock provides a finer granular locking and protects registers being clobbered while printks are nested within UART writes. Signed-off-by: Dave Jiang [EMAIL PROTECTED] Signed-off-by: Mark A. Greer [EMAIL PROTECTED] --- drivers/serial/mpsc.c | 25 - 1 files changed, 24

[PATCH] x86_64 RESTORE_CONTEXT missing '\n'

The RESTORE_CONTEXT macro is missing the '\n' at the end. It was removed in the previous patch that touched system.h. It causes compile failure if any inline asm is added after the macro. Discovered this when playing with kgdb. Signed-off-by: Dave Jiang [EMAIL PROTECTED] --- include/asm

[PATCH] MAINTAINERS: update Intel C600 SAS driver maintainers

Cc: Lukasz Dorau lukasz.do...@intel.com Cc: Maciej Patelczyk maciej.patelc...@intel.com Signed-off-by: Dave Jiang dave.ji...@intel.com --- MAINTAINERS |7 --- 1 files changed, 4 insertions(+), 3 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index b17587d..162f602 100644

[PATCH v3] ioatdma: Adding support for 16 src PQ ops and super extended descriptors

to the op descriptor during operation. This is a new feature for ioatdma v3.3. Signed-off-by: Dave Jiang dave.ji...@intel.com Acked-by: Dan Williams d...@fb.com --- drivers/dma/ioat/dma.h | 17 ++ drivers/dma/ioat/dma_v2.h|2 drivers/dma/ioat/dma_v3.c| 394

[PATCH v3] async_tx: allow generic async_memcpy() not be effected by channel switch

to remove the ifdef for channel switching fixup. Signed-off-by: Dave Jiang dave.ji...@intel.com --- crypto/async_tx/async_memcpy.c | 76 +++ crypto/async_tx/async_raid6_recov.c |4 +- drivers/md/raid5.c | 15 --- include/linux

[PATCH v2 0/5] ioatdma: Intel S1200 support patches

raid6test working. --- Dave Jiang (5): ioatdma: Removing hw bug workaround for CB3.x .2 and earlier ioatdma: Adding support for 16 src PQ ops and super extended descriptors ioatdma: S1200 platforms ioatdma channel 2 and 3 falsely advertise RAID cap ioatdma: Adding write back

[PATCH v2 1/5] ioatdma: Removing hw bug workaround for CB3.x .2 and earlier

CB3.2 and earlier hardware has silicon bugs that are no longer needed with the new hardware. We don't have to use a NULL op to signal interrupt for RAID ops any longer. This code make sure the legacy workarounds only happen on legacy hardware. Signed-off-by: Dave Jiang dave.ji...@intel.com

[PATCH v2 2/5] ioatdma: Adding support for 16 src PQ ops and super extended descriptors

to the op descriptor during operation. This is a new feature for ioatdma v3.3. Signed-off-by: Dave Jiang dave.ji...@intel.com Acked-by: Dan Williams d...@fb.com --- drivers/dma/ioat/dma.h | 17 ++ drivers/dma/ioat/dma_v2.h|2 drivers/dma/ioat/dma_v3.c| 399

[PATCH v2 3/5] ioatdma: S1200 platforms ioatdma channel 2 and 3 falsely advertise RAID cap

This workaround checks for channel 23 and remove RAID cap. Signed-off-by: Dave Jiang dave.ji...@intel.com Acked-by: Dan Williams d...@fb.com --- drivers/dma/ioat/dma_v3.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c

[PATCH v2 4/5] ioatdma: Adding write back descriptor error status support for ioatdma 3.3

to report the errors up the stack. We are also going to mask those error interrupts and handle them when the chain has completed at the end. Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers/dma/ioat/dma.h |1 drivers/dma/ioat/dma_v3.c| 111

[PATCH v2 5/5] async_tx: allow generic async_memcpy() not be effected by channel switch

to remove the ifdef for channel switching fixup. Signed-off-by: Dave Jiang dave.ji...@intel.com --- crypto/async_tx/async_memcpy.c | 76 +++- drivers/md/raid5.c | 15 +--- include/linux/async_tx.h |5 +++ include/linux/dmaengine.h

Re: [PATCH 06/10] ioatdma: Removing PQ val disable for cb3.3

On 03/27/2013 11:48 AM, Dan Williams wrote: On Tue, Mar 26, 2013 at 3:43 PM, Dave Jiang dave.ji...@intel.com wrote: The PQ Val ops work on the newer hardware so we should actually provide support for it and remove the disabling bits. Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers

Re: [PATCH v2] ioat: remove chanerr mask setting for IOAT v3.x

. There is no need for this code. Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers/dma/ioat/dma_v3.c |7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c index f7f1dc6..fda3b8a1 100644 --- a/drivers/dma/ioat

[PATCH] ioatdma: Adding Haswell devid for ioatdma

Adding Haswell PCI device IDs for ioatdma and simplify the detection of certain Xeon CPUs that has alignment bugs so that modifications can be changed at a single place going forward. Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers/dma/ioat/dma_v3.c | 28

[PATCH 00/10] Add Intel Atom S1200 seris ioatdma support

implemention. The series is dependent on the haswell update patch sent prior. --- Dave Jiang (10): ioatdma: Adding PCI IDs for Intel Atom S1200 product family ioatdma devices ioatdma: Add 64bit chansts register read for ioat v3.3. ioatdma: channel reset scheme fixup on Intel

[PATCH 02/10] ioatdma: Add 64bit chansts register read for ioat v3.3.

The channel status register for v3.3 is now 64bit. Use readq if available on v3.3 platforms. Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers/dma/ioat/dma.h | 22 +- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/dma/ioat/dma.h b/drivers/dma

[PATCH 03/10] ioatdma: channel reset scheme fixup on Intel Atom S1200 platforms

generations. Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers/dma/ioat/dma.c|8 +- drivers/dma/ioat/dma.h| 10 ++ drivers/dma/ioat/dma_v3.c | 236 + 3 files changed, 171 insertions(+), 83 deletions(-) diff --git a/drivers/dma/ioat

[PATCH 04/10] ioatdma: Removing hw bug workaround for CB3.x .2 and earlier

CB3.2 and earlier hardware has silicon bugs that are no longer needed with the new hardware. We don't have to use a NULL op to signal interrupt for RAID ops any longer. This code make sure the legacy workarounds only happen on legacy hardware. Signed-off-by: Dave Jiang dave.ji...@intel.com

[PATCH 05/10] ioatdma: skip legacy reset bits since v3.3 plattform doesn't need it

Make it so only 3.2 and earlier platform need the PCI config register clearings since this implementation does not have the registers. Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers/dma/ioat/dma_v3.c | 34 +- 1 file changed, 21 insertions(+), 13

[PATCH 07/10] ioatdma: skip silicon bug workaround for pq_align for cb3.3

The alignment workaround is only necessary for cb3.2 or earlier platforms. Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers/dma/ioat/dma_v3.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c index

[PATCH 09/10] ioatdma: Adding write back descriptor error status support for ioatdma 3.3

to report the errors up the stack. We are also going to mask those error interrupts and handle them when the chain has completed at the end. Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers/dma/ioat/dma_v3.c| 87 -- drivers/dma/ioat/hw.h

[PATCH 10/10] ioatdma: S1200 platforms ioatdma channel 2 and 3 falsely advertise RAID cap

This workaround checks for channel 23 and remove RAID cap. Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers/dma/ioat/dma_v3.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c index 83d44f3..6f6d2ec 100644

[PATCH 06/10] ioatdma: Removing PQ val disable for cb3.3

The PQ Val ops work on the newer hardware so we should actually provide support for it and remove the disabling bits. Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers/dma/Kconfig |2 - drivers/dma/ioat/dma.h |1 drivers/dma/ioat/dma_v3.c| 134

[PATCH 08/10] ioatdma: Adding support for 16 src PQ ops and super extended descriptors

to the op descriptor during operation. This is a new feature for ioatdma v3.3. Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers/dma/ioat/dma.h | 18 ++ drivers/dma/ioat/dma_v2.h|2 drivers/dma/ioat/dma_v3.c| 394 -- drivers

[PATCH 01/10] ioatdma: Adding PCI IDs for Intel Atom S1200 product family ioatdma devices

These should be good for the IOAT DMA devices on the Intel Atom S1269, S1279, and S1289 platforms. We are also adding IOAT v3.3 definition for the new DMA engine. Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers/dma/ioat/hw.h |6 ++ drivers/dma/ioat/pci.c |6 ++ 2

Re: [PATCH 09/10] ioatdma: Adding write back descriptor error status support for ioatdma 3.3

On 03/26/2013 04:47 PM, Dan Williams wrote: On 3/26/13 3:43 PM, Dave Jiang dave.ji...@intel.com wrote: v3.3 provides support for write back descriptor error status. This allows reporting of errors in a descriptor field. In supporting this, certain errors such as P/Q validation errors

[PATCH] async_tx: allow generic async_memcpy() not be effected by channel switch

This adds a generic async_memcpy() for the DMA engines that cannot do channel switch. Previously it would exclude all DMA engines that don't have all equal capabilities for all ops with the DMA_ASYNC_TX check. Signed-off-by: Dave Jiang dave.ji...@intel.com --- crypto/async_tx/async_memcpy.c

[PATCH] ioatdma: make debug output more readable

Making OP field a hex instead of integer to make it more readable. Also add the dump out of the NEXT field. Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers/dma/ioat/dma.h|2 +- drivers/dma/ioat/dma_v3.c |3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git

Re: [PATCH] ioatdma: make debug output more readable

On 03/05/2013 03:20 PM, Dan Williams wrote: On 3/4/13 9:59 AM, Dave Jiang dave.ji...@intel.com wrote: Making OP field a hex instead of integer to make it more readable. Also add the dump out of the NEXT field. Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers/dma/ioat/dma.h

[PATCH v2] ioatdma: make debug output more readable

Making OP field a hex instead of integer to make it more readable. Also add the dump out of the NEXT field. Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers/dma/ioat/dma.h|2 +- drivers/dma/ioat/dma_v3.c |3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git

[PATCH] ioat: Add alignment workaround for IVB platforms

The PCI IDs for IvyBridge IOAT DMA needs to go into a header file since dma_v3.c looks them up for certain hardware workarounds. Need to add to the alignment workaround for IOAT 3.2 since it wasn't fixed in IVB. Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers/dma/ioat/dma_v3.c | 22

[PATCH] ioatdma: fix race between updating ioat-head and IOAT_COMPLETION_PENDING

. Signed-off-by: Dave Jiang dave.ji...@intel.com Reviewed-by: Dan Williams d...@fb.com --- drivers/dma/ioat/dma.h|1 drivers/dma/ioat/dma_v2.c | 113 + drivers/dma/ioat/dma_v3.c | 111 +--- 3 files changed

[PATCH] ioatdma: allow all channels to have irq coalescing support

Looks like only the RAID channels are allowed to have irq coalescing support in the existing code. Fixing that. The ioat3 cleanup code can handle memcpy ops anyways Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers/dma/ioat/dma_v3.c | 12 +++- 1 file changed, 3 insertions

Re: [PATCH 1/2] efi: Make 'efi_enabled' a function to query EFI facilities

Airlie airl...@linux.ie Cc: H. Peter Anvin h...@zytor.com Cc: Corentin Chary corenti...@iksaif.net Cc: Matthew Garrett mj...@srcf.ucam.org Cc: Dave Jiang dave.ji...@intel.com Cc: Olof Johansson o...@lixom.net Cc: Peter Jones pjo...@redhat.com Cc: Colin Ian King colin.k...@canonical.com Cc: Steve Langasek

x86_64 frame pointer via thread context

Hi, I've been playing around with extracting the frame pointer from rBP register and using that to perform backtracing on the x86_64 platform. With a non-threaded user application, I was able to do that successfully. However, when attempting to do that with multi-threaded app, this seems to

Re: x86_64 frame pointer via thread context

won't get it in rBP. It is possible that userspace or toolchain may be suspect, However, why is the value bad in kernel space when rBP from pt_regs is dumped? -- Dave -- Dave Jiang Software Engineer Phone: (480) 517-0372 MontaVista

Re: x86_64 frame pointer via thread context

Dave Jiang wrote: Jan Engelhardt wrote: Am I doing something wrong, or is this intended to be this way on x86_64, or is something incorrect in the kernel? This method works fine on i386. Thanks for any help! I just tested your program on SLES9 with updated kernel and RBP looks correct to me

Re: x86_64 frame pointer via thread context

Andi Kleen wrote: Dave Jiang [EMAIL PROTECTED] writes: Am I doing something wrong, or is this intended to be this way on x86_64, or is something incorrect in the kernel? This method works fine on i386. Thanks for any help! I just tested your program on SLES9 with updated kernel and RBP

Re: x86_64 frame pointer via thread context

Petr Vandrovec wrote: Dave Jiang wrote: Andi Kleen wrote: Dave Jiang [EMAIL PROTECTED] writes: Am I doing something wrong, or is this intended to be this way on x86_64, or is something incorrect in the kernel? This method works fine on i386. Thanks for any help! I just tested your

Re: x86_64 frame pointer via thread context

some of them from clobbering rbp? -- Dave -- Dave Jiang Software Engineer Phone: (480) 517-0372 MontaVista Software, Inc.Fax: (480) 517-0262 2141 E Broadway Rd, St 108 Web: www.mvista.com Tempe, AZ 85282 mailto:[EMAIL

[PATCH v2] ioat: Adding Ivy Bridge IOATDMA PCI device IDs

Signed-off-by: Dave Jiang dave.ji...@intel.com --- Sorry about the churn. I had to move the PCI dev IDs to the header file after realizing that dma_v3.c actually sometimes check the PCI IDs in order to work around certain silicon bugs. drivers/dma/ioat/hw.h | 11 +++ drivers/dma/ioat

[PATCH] ioat: Adding Ivy Bridge IOATDMA PCI device IDs

Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers/dma/ioat/pci.c | 22 ++ 1 files changed, 22 insertions(+), 0 deletions(-) diff --git a/drivers/dma/ioat/pci.c b/drivers/dma/ioat/pci.c index 5e3a40f..c057306 100644 --- a/drivers/dma/ioat/pci.c +++ b/drivers/dma

Re: [PATCH] ioat: remove chanerr mask setting for IOAT v3.x

On 11/26/2012 09:56 PM, Dan Williams wrote: On Fri, Nov 16, 2012 at 3:26 PM, Dave Jiang dave.ji...@intel.com wrote: The CHANERRMSK_INT register should be 0. The existing code set a value for a workaround to address a pre-silicon bug on the Intel 5520 IO hub that has been fixed when

[PATCH v2] ioat: remove chanerr mask setting for IOAT v3.x

The existing code set a value in the PCI_CHANERRMSK_INT register for a workaround to address a pre-silicon bug on the Intel 5520 IO hub that has been fixed when the hardware was released. There is no need for this code. Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers/dma/ioat/dma_v3

[PATCH] ioat: remove chanerr mask setting for IOAT v3.x

The CHANERRMSK_INT register should be 0. The existing code set a value for a workaround to address a pre-silicon bug on the Intel 5520 IO hub that has been fixed when the hardware was released. There is no need for this code. Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers/dma/ioat

Re: [PATCH 2/2] ioatdma: add DMA_PRIVATE capabilities flag

the dma_request_channel function call. Signed-off-by: Jon Mason jon.ma...@intel.com Acked-by: Dave Jiang dave.ji...@intel.com --- drivers/dma/ioat/dma_v3.c |1 + 1 file changed, 1 insertion(+) diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c index ca6ea9b..ac2aeef 100644 --- a/drivers

[PATCH] MAINTAINERS: add to ioatdma maintainer list

dan.j.willi...@intel.com -S: Maintained +M: Dave Jiang dave.ji...@intel.com +S: Supported F: drivers/dma/ioat* INTEL IOMMU (VT-d) -- 1.8.3.1 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo

Re: [PATCH] dmatest: masking tests for channel capabilities

like: (1 DMA_MEMCPY) And also in that case for user scripts you have bits that are here and there for the bitmask instead of something simple and sequential. -- Dave Jiang Application Engineer, Storage Divsion Intel Corp. dave.ji...@intel.com -- To unsubscribe from this list: send the line

Re: [PATCH] ioat: device control support

Acked-by: Dave Jiang dave.ji...@intel.com On 05/17/2013 10:53 AM, Jon Mason wrote: Add device control support for CBDMA v2 and v3 in the ioat driver. This allows DMA engine clients to call into the ioat driver and issue a DMA_TERMINATE_ALL. Signed-off-by: Jon Mason jon.ma...@intel.com

[PATCH] ntb: fix sysfs display of usd vs dsd

The sysfs display is opposite of the discovery printout and what the BIOS has configured. Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers/ntb/ntb_hw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ntb/ntb_hw.c b/drivers/ntb/ntb_hw.c index db0fe8a..ce6680a

[PATCH 0/6] NTB bug fixes and hardware workarounds

The following series contains various fixes and cleanup for NTB. It also adds the split BAR support on Haswell platform and a hardware errata workaround in order to allow interrupts to function during bi-directional traffic under stress. --- Dave Jiang (6): ntb: Add alignment check

[PATCH 1/6] ntb: Add alignment check to meet hardware requirement

with the appropriate CONFIG_CMA_ALIGNMENT and CONFIG_CMA_SIZE_MBYTES set. Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers/ntb/ntb_transport.c | 13 + 1 file changed, 13 insertions(+) diff --git a/drivers/ntb/ntb_transport.c b/drivers/ntb/ntb_transport.c index 611fef4

[PATCH 2/6] ntb: move platform detection to separate function

Move the platform detection function to separate functions to allow easier maintenence. Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers/ntb/ntb_hw.c | 56 ++ 1 file changed, 38 insertions(+), 18 deletions(-) diff --git a/drivers/ntb

[PATCH 6/6] ntb: workaround for high traffic hardware hang

. The scratch pads are now overloaded in order to allow the exchange of the information. This gets around using the doorbell and prevents the lockup with additional pcode changes in BIOS. Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers/ntb/ntb_hw.c| 177

[PATCH 5/6] ntb: Adding split BAR support for Haswell platforms

On the Haswell platform, a split BAR option to allow creation of 2 32bit BARs (4 and 5) from the 64bit BAR 4. Adding support for this new option. Signed-off-by: Dave Jiang dave.ji...@intel.com Signed-off-by: Jon Mason jdma...@gmail.com --- drivers/ntb/ntb_hw.c | 217

[PATCH 3/6] ntb: conslidate reading of PPD to move platform detection earlier

To simplify some of the platform detection code. Move the platform detection to a function to be called earlier. Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers/ntb/ntb_hw.c | 130 ++ 1 file changed, 100 insertions(+), 30 deletions

[PATCH 4/6] ntb: use errata flag set via DID to implement workaround

Instead of using a module parameter, we should detect the errata via PCI DID and then set an appropriate flag. This will be used for additional errata later on. Signed-off-by: Dave Jiang dave.ji...@intel.com --- drivers/ntb/ntb_hw.c | 47 ++- drivers

[PATCH] MAINTAINERS: Remove self as isci maintainer

Removing myself as a maintainer. Signed-off-by: Dave Jiang dave.ji...@intel.com --- MAINTAINERS |1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 93409ad..7e3d97a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4946,7 +4946,6 @@ K:\b(ABS|SYN)_MT_ INTEL

[PATCH] MAINTAINERS: adding mailing list for NTB

Adding a mailing list for PCI NTB Signed-off-by: Dave Jiang dave.ji...@intel.com --- MAINTAINERS |1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index f8e0afb..60440e1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6981,6 +6981,7 @@ F:drivers/power

Re: IOAT 4.0 driver not supported on Intel 5000 chipset

lowing commits. > > commit 85596a19478da5125f3471a0c474b3f05a78e390 > Author: Dave Jiang <dave.ji...@intel.com> > Date: Tue Aug 11 08:48:10 2015 -0700 > > dmaengine: ioatdma: remove ioat1 specific code > > Cleaning up of ioat1 specific code as it is no longer supported >

Re: [PATCH] fixup! mm, fs: reduce fault, page_mkwrite, and pfn_mkwrite to take only vmf

ite to take > only vmf") > Signed-off-by: Arnd Bergmann <a...@arndb.de> Thanks for catching these! Acked-by: Dave Jiang <dave.ji...@intel.com> > --- > drivers/gpu/drm/armada/armada_gem.c | 9 + > drivers/gpu/drm/etnaviv/etnaviv_drv.h | 2 +- > d

Re: linux-next 0112 tree breaks fs DAX

On 01/16/2017 03:45 AM, Stephen Rothwell wrote: > Hi Xiong, > > Just cc'ing Andrew. > > On Mon, 16 Jan 2017 17:29:16 +0800 Xiong Zhou wrote: >> >> On Fri, Jan 13, 2017 at 06:16:41PM +0800, Xiong Zhou wrote: >>> Hi, >>> >>> These cases "hang" when testing with -o dax mount

Re: linux-next 0112 tree breaks fs DAX

On 01/17/2017 09:05 AM, Dave Jiang wrote: > On 01/16/2017 03:45 AM, Stephen Rothwell wrote: >> Hi Xiong, >> >> Just cc'ing Andrew. >> >> On Mon, 16 Jan 2017 17:29:16 +0800 Xiong Zhou <xz...@redhat.com> wrote: >>> >>> On Fri, Ja

Re: linux-next 0112 tree breaks fs DAX

On 01/17/2017 11:13 AM, Dave Jiang wrote: > > > On 01/17/2017 09:05 AM, Dave Jiang wrote: >> On 01/16/2017 03:45 AM, Stephen Rothwell wrote: >>> Hi Xiong, >>> >>> Just cc'ing Andrew. >>> >>> On Mon, 16 Jan 2017 17:29:16 +0800 Xiong Z

Re: [PATCH] mm,x86: fix SMP x86 32bit build for native_pud_clear()

On 02/27/2017 12:29 PM, Boris Ostrovsky wrote: >> On 02/15/2017 12:31 PM, Dave Jiang wrote: >>> The fix introduced by e4decc90 to fix the UP case for 32bit x86, however >>> that broke the SMP case that was working previously. Add ifdef so the dummy >>> functi

Re: [PATCH] mm,fs,dax: mark dax_iomap_pmd_fault as const

On 02/27/2017 01:33 PM, Arnd Bergmann wrote: > The two alternative implementations of dax_iomap_fault have different > prototypes, and one of them is obviously wrong as seen from this build > warning: > > fs/dax.c: In function 'dax_iomap_fault': > fs/dax.c:1462:35: error: passing argument 2 of

Re: [PATCH] dmaengine: dmatest: Restore "memcpy" as default mode

On 09/15/2016 08:48 AM, Vinod Koul wrote: > On Wed, Sep 14, 2016 at 08:40:38PM +0300, Eugeniy Paltsev wrote: >> Commit 0d4cb44da6ca0e8 ("dmaengine: dmatest: Add support for >> scatter-gather DMA mode") changes default "dmatest" behavior by >> changing default mode from "memcpy" to

[PATCH] x86: fix kaslr and memmap collision

to avoid the region marked by memmap. Signed-off-by: Dave Jiang <dave.ji...@intel.com> --- arch/x86/boot/boot.h |2 ++ arch/x86/boot/compressed/kaslr.c | 45 ++ arch/x86/boot/string.c | 25 + 3 files chang

Re: [PATCH] x86: Add warning when memmap=nn!ss and CONFIG_RANDOMIZE_BASE enabled

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 On 11/18/2016 04:33 AM, Thomas Gleixner wrote: > On Thu, 17 Nov 2016, Dave Jiang wrote: >> CONFIG_RANDOMIZE_BASE can place the kernel anywhere. This causes >> a problem for when memmap=nn!ss is used. This information is not >&

Re: [PATCH] x86: Add warning when memmap=nn!ss and CONFIG_RANDOMIZE_BASE enabled

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 On 11/18/2016 10:07 AM, Dan Williams wrote: > On Fri, Nov 18, 2016 at 8:47 AM, Dave Jiang <dave.ji...@intel.com> > wrote: >> -BEGIN PGP SIGNED MESSAGE- Hash: SHA256 >> >> >> >> On 11/18/2016 0

[PATCH] x86: Add warning when memmap=nn!ss and CONFIG_RANDOMIZE_BASE enabled

is not reliable in the presence of CONFIG_RANDOMIZE_BASE. Signed-off-by: Dave Jiang <dave.ji...@intel.com> --- Documentation/kernel-parameters.txt |5 - arch/x86/kernel/e820.c |2 ++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/kernel-parameters.

[PATCH v2] x86: fix kaslr and memmap collision

. Signed-off-by: Dave Jiang <dave.ji...@intel.com> --- arch/x86/boot/boot.h |3 + arch/x86/boot/compressed/kaslr.c | 82 ++ arch/x86/boot/string.c | 38 ++ 3 files changed, 123 insertions(+) diff --git a/arch/x8

Re: [PATCH v2] x86: fix kaslr and memmap collision

On 11/29/2016 12:26 PM, Dave Jiang wrote: > CONFIG_RANDOMIZE_BASE relocates the kernel to a random base address. > However it does not take into account the memmap= parameter passed in from > the kernel cmdline. This results in the kernel sometimes being put in > the middle of the

Re: [PATCH v6] x86: fix kaslr and memmap collision

On 01/11/2017 05:00 AM, Thomas Gleixner wrote: > On Tue, 10 Jan 2017, Dave Jiang wrote: >> +unsigned long simple_strtoul(const char *cp, char **endp, unsigned int >> base); >> +long simple_strtol(const char *cp, char **endp, unsigned int base); > &g

[PATCH v6] x86: fix kaslr and memmap collision

. The nn@ss ranges will be skipped by the mem_avoid set since it indicates memory useable. Signed-off-by: Dave Jiang <dave.ji...@intel.com> --- arch/x86/boot/boot.h |3 + arch/x86/boot/compressed/kaslr.c | 132 ++ arch/x86/boot/st

[PATCH v7] x86: fix kaslr and memmap collision

. The nn@ss ranges will be skipped by the mem_avoid set since it indicates memory useable. Signed-off-by: Dave Jiang <dave.ji...@intel.com> Acked-by: Kees Cook <keesc...@chromium.org> Acked-by: Baoquan He <b...@redhat.com> --- arch/x86/boot/boot.h |1 arch/x

Re: [PATCH 1/1] dma: ioat: set error code on failures

inconsistent with the execution status. This patch > fixes the bug by assigning -ENOMEM to err on the error path. > > Signed-off-by: Pan Bian <bianpan2...@163.com> Acked-by: Dave Jiang <dave.ji...@intel.com> > --- > drivers/dma/ioat/init.c | 2 ++ > 1 file changed,

Re: [PATCH 2/2] dma: ioat: fix improper return value on failures

_mapping_error() fails. > > Signed-off-by: Pan Bian <bianpan2...@163.com> Acked-by: Dave Jiang <dave.ji...@intel.com> > --- > drivers/dma/ioat/init.c | 16 > 1 file changed, 12 insertions(+), 4 deletions(-) > > diff --git a/drivers/dma/ioat/init.c b/

[PATCH v5] x86: fix kaslr and memmap collision

. The nn@ss ranges will be skipped by the mem_avoid set since it indicates memory useable. Signed-off-by: Dave Jiang <dave.ji...@intel.com> --- v2: Addressing comments from Ingo. - Handle entire list of memmaps v3: Fix 32bit build issue v4: Addressing comments from Baoquan - Not exclude nn@ss

Re: [PATCH v4] x86: fix kaslr and memmap collision

On 01/03/2017 07:37 PM, Baoquan He wrote: > Hi Dave, > > I have several concerns, please see the inline comments. > > On 01/03/17 at 01:48pm, Dave Jiang wrote: >> CONFIG_RANDOMIZE_BASE relocates the kernel to a random base address. >> However it does not take into ac

[PATCH v4] x86: fix kaslr and memmap collision

. The nn@ss ranges will be skipped by the mem_avoid set since it indicates memory useable. Signed-off-by: Dave Jiang <dave.ji...@intel.com> --- arch/x86/boot/boot.h |3 + arch/x86/boot/compressed/kaslr.c | 131 ++ arch/x86/boot/st

Re: [PATCH] x86: fix kaslr and memmap collision

>> On Tue, Nov 22, 2016 at 12:47 AM, Ingo Molnar <mi...@kernel.org> wrote: >>>> >>>> * Dave Jiang <dave.ji...@intel.com> wrote: >>>> >>>>> CONFIG_RANDOMIZE_BASE relocates the kernel to a random base address. >>>>> H

Re: [tip:x86/urgent] x86/boot: Prevent KASLR and memmap collision

On 12/20/2016 01:31 AM, Ingo Molnar wrote: > > * tip-bot for Dave Jiang <tip...@zytor.com> wrote: > >> Commit-ID: d1a5058c063d9e0aaaf4d360d0f8074ee55ed096 >> Gitweb: >> http://git.kernel.org/tip/d1a5058c063d9e0aaaf4d360d0f8074ee55ed096 >> Autho

Re: [PATCH] NTB: Fix 'request_irq()' and 'free_irq()' inconsistancy

On 12/18/2016 10:52 PM, Christophe JAILLET wrote: > 'request_irq()' and 'free_irq()' should have the same 'dev_id'. > > Signed-off-by: Christophe JAILLET <christophe.jail...@wanadoo.fr> Acking the Intel driver portion. Acked-by: Dave Jiang <dave.ji...@intel.com> > -

[PATCH v3] x86: fix kaslr and memmap collision

. Signed-off-by: Dave Jiang <dave.ji...@intel.com> --- arch/x86/boot/boot.h |3 + arch/x86/boot/compressed/kaslr.c | 124 ++ arch/x86/boot/string.c | 38 3 files changed, 165 insertions(+) diff --git a/arch/x8

Re: arch/x86/include/asm/pgtable.h:888:2: error: implicit declaration of function 'native_pud_clear'

Fengguang, I don't believe Andrew has picked up this patch yet: http://marc.info/?l=linux-mm=148883870428812=2 Unless you are seeing issues with that patch. On 03/11/2017 03:55 PM, kbuild test robot wrote: > Hi Matthew, > > FYI, the error/warning still remains. > > tree:

Re: When will Linux support M2 on RAID ?

On 03/06/2017 09:52 PM, Christoph Hellwig wrote: > On Sun, Mar 05, 2017 at 06:09:42PM -0800, David F. wrote: >> More and more systems are coming with M2 on RAID and Linux doesn't >> work unless you change the system out of RAID mode. This is becoming >> more and more of a problem. What is the

Re: [PATCH v2 1/3] dmaengine: add DMA_PREP_CMD for non-Data descriptors.

On 07/31/2017 05:34 AM, Vinod Koul wrote: > On Fri, Jul 28, 2017 at 09:38:56PM +0530, Abhishek Sahu wrote: >> On 2017-07-19 17:48, Abhishek Sahu wrote: >>> On 2017-07-19 15:37, Vinod Koul wrote: On Mon, Jun 26, 2017 at 06:19:27PM +0530, Abhishek Sahu wrote: > Some of the DMA controllers

Re: [PATCH] dmaengine: ioatdma: Fix error handling path in 'ioat_dma_self_test()'

On 07/20/2017 12:24 AM, walter harms wrote: > > > Am 20.07.2017 00:16, schrieb Christophe JAILLET: >> If the 'memcmp' fails, free allocated resources as done in all other >> error handling paths. >> >> Signed-off-by: Christophe JAILLET >> --- >> Please review

Re: [PATCH] dmaengine: ioatdma: Fix error handling path in 'ioat_dma_self_test()'

On 07/19/2017 03:16 PM, Christophe JAILLET wrote: > If the 'memcmp' fails, free allocated resources as done in all other > error handling paths. > > Signed-off-by: Christophe JAILLET <christophe.jail...@wanadoo.fr> Good catch! Thanks. Signed-off-by: Dave Jiang <

Re: [PATCH] dmaengine: ioatdma: Fix error handling path in 'ioat_dma_self_test()'

On 07/21/2017 12:57 AM, Vinod Koul wrote: > On Thu, Jul 20, 2017 at 09:56:45AM -0700, Dave Jiang wrote: >> >> >> On 07/20/2017 12:24 AM, walter harms wrote: >>> >>> >>> Am 20.07.2017 00:16, schrieb Christophe JAILLET: >>>> If the '

Re: [PATCH v3 08/16] switchtec_ntb: introduce initial NTB driver

On 07/25/2017 01:57 PM, Logan Gunthorpe wrote: > Seeing the Switchtec NTB hardware shares the same endpoint as the > management endpoint we utilize the class_interface API to register > an NTB driver for every Switchtec device in the system that has the > NTB class code. > > Signed-off-by:

Re: [RFC PATCH] dax: add badblocks check to Device DAX

On 05/03/2017 02:48 PM, Dan Williams wrote: > On Wed, May 3, 2017 at 11:46 AM, Kani, Toshimitsu wrote: >> On Wed, 2017-05-03 at 09:30 -0700, Dan Williams wrote: >>> On Wed, May 3, 2017 at 9:09 AM, Kani, Toshimitsu >>> wrote: On Wed, 2017-05-03 at

Re: [PATCH 03/44] dmaengine: ioat: don't use DMA_ERROR_CODE

On 06/08/2017 06:25 AM, Christoph Hellwig wrote: > DMA_ERROR_CODE is not a public API and will go away. Instead properly > unwind based on the loop counter. > > Signed-off-by: Christoph Hellwig <h...@lst.de> Acked-by: Dave Jiang <dave.ji...@intel.com> > --- >

Re: [PATCH] dmaengine: ioat: Fix error handling path

On 11/17/2017 02:37 PM, Christophe JAILLET wrote: > If the last test in 'ioat_dma_self_test()' fails, we must release all > the allocated resources and not just part of them. > > Signed-off-by: Christophe JAILLET <christophe.jail...@wanadoo.fr> Good catch! Thanks! Acked-by: D

Re: [GIT PULL] NTB bug fixes for v4.15

On 11/20/2017 03:53 PM, Logan Gunthorpe wrote: > > > On 20/11/17 03:37 PM, Stephen Rothwell wrote: >> OK, all I need is the (git) URL for a tree/branch (or tag) and a >> contact (or more than one) to whom I can report conflicts and build >> problems.  I then fetch it every day (so all you have

Re: [GIT PULL] NTB bug fixes for v4.15

On 11/20/2017 03:37 PM, Stephen Rothwell wrote: > Hi Logan, > > On Sun, 19 Nov 2017 23:51:48 -0700 Logan Gunthorpe > wrote: >> >>> I do want to protest the timing and the lack of linux-next coverage. >>> If it has really been ready for months, why hasn't it been in >>>

Re: [PATCH 2/8] NTB: Setup the DMA mask globally for all drivers

; Fixes: 7f46c8b3a552 ("NTB: ntb_tool: Add full multi-port NTB API support") > Signed-off-by: Logan Gunthorpe Acked-by: Dave Jiang for the Intel parts and the generic parts > --- > drivers/ntb/hw/amd/ntb_hw_amd.c | 4 > drivers/ntb/hw/idt/ntb_hw_idt.c

Re: [PATCH] dmaengine: ioat: Use common error handling code in ioat_xor_val_self_test()

On 10/23/2017 12:27 AM, Dan Carpenter wrote: > These patches hurt readability. > > regards, > dan carpenter > I agree with Dan. I'm ok with not accepting this patch.

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