tegra_dma_abort_all() won't be called on channel freeing
if pending list is empty or channel not busy. We need to clear isr_handler
on channel freeing to avoid locking. Also I added small optimization to prepare
functions, so current channel type checked before making allocations.
Signed-off-by: Dmitry
Also code looks not thread-safe, is it ok? For example we can protect prepare
functions with a spinlock and add tegra_dma_terminate_all_locked for calling on
channel freeing under spinlock to avoid reschedule. What do you think?
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This prevents playing sound with wrong speed.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
---
I'm using deep sleep on my tablet and faced with this bug when played sound via
hdmi after suspend. I know that there is no deep sleep support in upstream
kernel,
but will be nice to see that bug
Added suspend/resume pm ops. We need to store current regs vals on suspend and
restore them on resume.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
---
Tested on my tablet.
drivers/pinctrl/pinctrl-tegra.c | 94 +++--
1 file changed, 91 insertions(+), 3
Fixed err msg params order on irq request fail.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
---
drivers/dma/tegra20-apb-dma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index 528c62d..4d816be 100644
tegra_dma_abort_all() won't be called on channel freeing
if pending list is empty.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
---
drivers/dma/tegra20-apb-dma.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index 4d816be..00c5dee 100644
Add guard to check whether RGB output is already enabled in the way it's
done for HDMI output. Fixes possible hang on trying to disable output twice
(first time during driver probe and second on fb registering).
Signed-off-by: Dmitry Osipenko dig...@gmail.com
---
drivers/gpu/drm/tegra/rgb.c | 11
11.02.2014 23:13, Erik Faye-Lund пишет:
On Tue, Feb 11, 2014 at 6:12 PM, Dmitry Osipenko dig...@gmail.com wrote:
Add guard to check whether RGB output is already enabled in the way it's
done for HDMI output. Fixes possible hang on trying to disable output twice
(first time during driver probe
Use device_init_wakeup() instead of device_set_wakeup_capable() and move it
before rtc dev registering. This fixes alarmtimer not registered when tps6586x
rtc is the only wakeup compatible rtc in the system.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
---
V2: changed description
drivers
23.05.2013 02:22, Andrew Morton пишет:
On Sun, 12 May 2013 18:25:06 +0400 Dmitry Osipenko dig...@gmail.com wrote:
Use device_init_wakeup() instead of device_set_wakeup_capable() and move it
before rtc dev registering. This fixes issue with alarmtimer that checks
wakeup
capability
Use device_init_wakeup() instead of device_set_wakeup_capable() and move it
before rtc dev registering. This fixes issue with alarmtimer that checks wakeup
capability with device_may_wakeup() on device add.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
---
drivers/rtc/rtc-tps6586x.c | 3 ++-
1
Commit d127e9c5c5bc1ee22a7b1fe804397cddd132f756 (ARM: tegra: make tegra_resume
can work with current and later chips) removed tegra_get_soc_id macro leaving
used cpu register unassigned and as result causing execution of unintended code
on tegra20. Fix it by re-adding macro.
Signed-off-by: Dmitry
: tegra: make tegra_resume can work with current and later
chips)
Cc: sta...@vger.kernel.org # v3.13+
Reviewed-by: Felipe Balbi ba...@ti.com
Signed-off-by: Dmitry Osipenko dig...@gmail.com
---
V2: added Cc's for lakml and stable, added Reviewed-by: Felipe Balbi
arch/arm/mach-tegra/reset-handler.S
-by: Dmitry Osipenko dig...@gmail.com
Fixes: 7232398abc6a (ARM: tegra: Convert PMC to a driver)
Cc: sta...@vger.kernel.org # v3.17+
---
drivers/soc/tegra/pmc.c | 37 +++--
1 file changed, 19 insertions(+), 18 deletions(-)
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc
Oh, just after sending email, I realized that commit description isn't correct.
I'll send V2.
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Please
it by making PMC driver use
syscore PM ops to ensure correct order of scratch register usage.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
Fixes: 7232398abc6a (ARM: tegra: Convert PMC to a driver)
Cc: sta...@vger.kernel.org # v3.17+
---
v2: changed commit description
drivers/soc/tegra/pmc.c
I think ARM: tegra: is wrong prefix for this patch and soc: tegra: should be
used instead to show that it belongs to SoC driver, not arch code.
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More majordomo
-by: Dmitry Osipenko dig...@gmail.com
Fixes: 58ecb23f64ee (ARM: tegra: add missing unit addresses to DT)
Cc: sta...@vger.kernel.org # v3.13+
---
arch/arm/boot/dts/tegra20.dtsi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts
and in the same time used by
tegra20 cpuidle driver for storing cpu1 resettable status, so it implied
strict order of scratch register use. Fix it by using scratch 40 instead of 41
for tegra_resume() location store.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
Fixes: 7232398abc6a (ARM: tegra: Convert PMC
22.12.2014 19:17, Stephen Warren пишет:
On 12/21/2014 03:52 PM, Dmitry Osipenko wrote:
Commit 7232398abc6a (ARM: tegra: Convert PMC to a driver) changed
tegra_resume()
location storing from late to early and as result broke suspend on tegra20.
PMC scratch register 41 was used by tegra lp1
08.10.2014 23:24, Dmitry Osipenko пишет:
Commit d127e9c5c5bc1ee22a7b1fe804397cddd132f756 (ARM: tegra: make
tegra_resume
can work with current and later chips) removed tegra_get_soc_id macro leaving
used cpu register unassigned and as result causing execution of unintended
code
on tegra20
with current and later
chips)
Cc: sta...@vger.kernel.org # v3.13+
Reviewed-by: Felipe Balbi ba...@ti.com
Signed-off-by: Dmitry Osipenko dig...@gmail.com
---
V2: added Cc's for lakml and stable, added Reviewed-by: Felipe Balbi
V3: changed commit description, tested on real hw
PS: It wasn't a bug
26.01.2015 19:03, Wolfram Sang пишет:
Gaahh! I'm sure it wasn't working before! I'll make more testing and send v3
without val = 0, if all will be fine.
Please either send V3 or explicitly say V2 is OK. No need to hurry, just
saying that I am waiting for updates here...
Sure!
--
Dmitry
--
Support CPU BE mode by adding endianness conversion for memcpy interactions.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
Acked-by: Alexandre Courbot acour...@nvidia.com
---
Changelog:
v2: For consistency cpu_to_le32() changed to le32_to_cpu() because
i2c_writel() takes BE value in BE CPU
In big endian CPU mode l2x0_saved_regs structure stores registers values in BE
format. In order to maintain BE CPU mode, these values and immediate constants
must be converted back to LE format before writing them to cache controller.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
---
arch/arm
Support CPU BE mode by adding endianness conversion for memcpy interactions.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
---
drivers/i2c/busses/i2c-tegra.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 28b87e6
19.01.2015 21:26, Dmitry Osipenko пишет:
19.01.2015 21:00, Dmitry Osipenko пишет:
19.01.2015 20:45, Stephen Warren пишет:
On 01/19/2015 10:41 AM, Dmitry Osipenko wrote:
19.01.2015 20:26, Stephen Warren пишет:
Hopefully this works out. I suppose it's unlikely anyone will be
running code
In big endian CPU mode l2x0_saved_regs structure stores registers values in BE
format. In order to maintain BE CPU mode, these values and immediate constants
must be converted back to LE format before writing them to cache controller.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
---
V2
19.01.2015 17:12, Thierry Reding пишет:
On Thu, Jan 15, 2015 at 01:58:57PM +0300, Dmitry Osipenko wrote:
Commit 7232398abc6a (ARM: tegra: Convert PMC to a driver) changed
tegra_resume()
location storing from late to early and, as a result, broke suspend on Tegra20.
PMC scratch register 41
19.01.2015 20:26, Stephen Warren пишет:
Hopefully this works out. I suppose it's unlikely anyone will be running code on
the AVP upstrem, so any potential conflict with AVP's usage of IRAM isn't likely
to occur.
I don't see how it can conflict with AVP code. First KB of IRAM is reserved for
19.01.2015 20:45, Stephen Warren пишет:
On 01/19/2015 10:41 AM, Dmitry Osipenko wrote:
19.01.2015 20:26, Stephen Warren пишет:
Hopefully this works out. I suppose it's unlikely anyone will be
running code on
the AVP upstrem, so any potential conflict with AVP's usage of IRAM
isn't likely
19.01.2015 21:00, Dmitry Osipenko пишет:
19.01.2015 20:45, Stephen Warren пишет:
On 01/19/2015 10:41 AM, Dmitry Osipenko wrote:
19.01.2015 20:26, Stephen Warren пишет:
Hopefully this works out. I suppose it's unlikely anyone will be
running code on
the AVP upstrem, so any potential conflict
it by storing resettable status in
IRAM instead of PMC scratch register.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
Fixes: 7232398abc6a (ARM: tegra: Convert PMC to a driver)
Cc: sta...@vger.kernel.org # v3.17+
---
arch/arm/mach-tegra/cpuidle-tegra20.c | 5 ++---
arch/arm/mach-tegra/reset
Hi, this is third attempt to fix Tegra20 suspend bug. First was to use other
PMC scratch register for tegra_resume() address store and second to use syscore
ops for PMC driver.
Thierry Reding proposed other solution: to use IRAM instead of PMC scratch
register. I prepared two implementation
it by storing tegra_resume() physical
address in IRAM instead of PMC scratch register.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
Fixes: 7232398abc6a (ARM: tegra: Convert PMC to a driver)
Cc: sta...@vger.kernel.org # v3.17+
---
arch/arm/mach-tegra/pm.c| 3 +++
arch/arm/mach-tegra
CPU1 resettable status is already cleared by final suspend function in case
of suspend abortion and by reset handler in case of completed CPU powergate,
no point to do it again.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
---
arch/arm/mach-tegra/cpuidle-tegra20.c | 2 --
1 file changed, 2
15.01.2015 15:49, Dmitry Osipenko пишет:
CPU1 resettable status is already cleared by final suspend function in case
of suspend abortion and by reset handler in case of completed CPU powergate,
no point to do it again.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
---
arch/arm/mach-tegra
22.01.2015 18:22, Dmitry Osipenko пишет:
22.01.2015 10:55, Alexandre Courbot пишет:
On Thu, Jan 22, 2015 at 4:40 PM, Thierry Reding
thierry.red...@gmail.com wrote:
Should this not technically be le32_to_cpu() since the data originates
from the I2C controller?
No, i2c_readl returns value
22.01.2015 10:55, Alexandre Courbot пишет:
On Thu, Jan 22, 2015 at 4:40 PM, Thierry Reding
thierry.red...@gmail.com wrote:
Should this not technically be le32_to_cpu() since the data originates
from the I2C controller?
No, i2c_readl returns value in CPU endianness, so it's correct. But for
22.01.2015 19:06, Dmitry Osipenko пишет:
22.01.2015 18:22, Dmitry Osipenko пишет:
22.01.2015 10:55, Alexandre Courbot пишет:
On Thu, Jan 22, 2015 at 4:40 PM, Thierry Reding
thierry.red...@gmail.com wrote:
Should this not technically be le32_to_cpu() since the data originates
from the I2C
Support CPU BE mode by adding endianness conversion for memcpy interactions.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
---
Changelog:
v2: For consistency cpu_to_le32() changed to le32_to_cpu() because
i2c_writel() takes BE value in BE CPU mode and value is in LE format.
drivers/i2c
23.01.2015 12:45, Thierry Reding пишет:
On Thu, Jan 22, 2015 at 08:18:34PM +0300, Dmitry Osipenko wrote:
22.01.2015 19:06, Dmitry Osipenko пишет:
22.01.2015 18:22, Dmitry Osipenko пишет:
22.01.2015 10:55, Alexandre Courbot пишет:
On Thu, Jan 22, 2015 at 4:40 PM, Thierry Reding
thierry.red
+0100, Thierry Reding wrote:
Old Signed by an unknown key
On Mon, Dec 22, 2014 at 11:00:16AM -0700, Stephen Warren wrote:
On 12/22/2014 10:27 AM, Dmitry Osipenko wrote:
22.12.2014 19:17, Stephen Warren пишет:
On 12/21/2014 03:52 PM, Dmitry Osipenko wrote:
Commit 7232398abc6a (ARM: tegra: Convert
by an unknown key
On Mon, Dec 22, 2014 at 11:00:16AM -0700, Stephen Warren wrote:
On 12/22/2014 10:27 AM, Dmitry Osipenko wrote:
22.12.2014 19:17, Stephen Warren пишет:
On 12/21/2014 03:52 PM, Dmitry Osipenko wrote:
Commit 7232398abc6a (ARM: tegra: Convert PMC to a driver) changed
tegra_resume
08.01.2015 13:58, Thierry Reding пишет:
On Thu, Jan 08, 2015 at 12:42:47PM +0300, Dmitry Osipenko wrote:
08.01.2015 11:49, Thierry Reding пишет:
I don't like changing this back to syscore_ops since it makes things
less easier to follow. I also don't think that using PMC_SCRATCH41 for
two
08.01.2015 11:49, Thierry Reding пишет:
I don't like changing this back to syscore_ops since it makes things
less easier to follow. I also don't think that using PMC_SCRATCH41 for
two different purposes is a good thing. There are a couple of
suggestions in my reply to your original patch.
07.01.2015 17:33, Thierry Reding пишет:
On Tue, Dec 09, 2014 at 10:36:50PM +, Paul Walmsley wrote:
Tegra SoCs with 64-bit ARM support don't currently support deep CPU
low-power states in mainline Linux. When this support is added in the
future, it will probably look rather different from
07.01.2015 18:24, Dmitry Osipenko пишет:
For now there is no feedback for my suspend bug patch (other than for V1),
but,
To be more correct, by V1 I meant http://patchwork.ozlabs.org/patch/423224/
--
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Support big-endian kernel by using endian-aware register access functions.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
---
drivers/clocksource/tegra20_timer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clocksource/tegra20_timer.c
b/drivers/clocksource
Now, after making drivers and arch code aware of big-endian CPU mode, NVIDIA
Tegra SoC supports big-endian kernel across all generations. Enable it in
Kconfig.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
---
arch/arm/mach-tegra/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git
In big-endian CPU mode l2x0_saved_regs structure stores registers values in BE
format. In order to maintain BE CPU mode, these values and immediate constants
must be converted back to LE format before writing them to cache controller.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
Acked
This patch adds support for big-endian CPU mode to assembler code, which is
required for booting secondary CPU's, cpuidle drivers and machine suspend/resume
functionality with big-endian kernel.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
---
Tested on Tegra 2 and 3.
arch/arm/mach-tegra
11.03.2015 13:18, Thierry Reding пишет:
On Tue, Jan 20, 2015 at 03:36:55PM +0300, Dmitry Osipenko wrote:
In big endian CPU mode l2x0_saved_regs structure stores registers values in BE
format. In order to maintain BE CPU mode, these values and immediate constants
must be converted back to LE
This patch adds support for big-endian CPU mode to assembler code, which is
required for booting secondary CPU's, cpuidle drivers and machine suspend/resume
functionality with big-endian kernel.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
---
Tested on Tegra 2 and 3.
Changelog:
V2: Cleanup
Convert CPU reset vector address to LE to support big-endian kernel.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
---
arch/arm/firmware/trusted_foundations.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/firmware/trusted_foundations.c
b/arch/arm/firmware
This patch not tested. I assume that firmware save/restore cp15 context, i.e. it
doesn't require switching to LE before smc call and restore endianness after.
--
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20.03.2015 19:07, Stephen Warren пишет:
On 03/20/2015 09:36 AM, Dmitry Osipenko wrote:
Convert CPU reset vector address to LE to support big-endian kernel.
Naively this sounds a little odd; the value here is in a CPU register all the
time, not in memory, so I'm not sure why endianness
11.03.2015 13:29, Thierry Reding пишет:
On Thu, Jan 15, 2015 at 01:58:57PM +0300, Dmitry Osipenko wrote:
Commit 7232398abc6a (ARM: tegra: Convert PMC to a driver) changed
tegra_resume()
location storing from late to early and, as a result, broke suspend on Tegra20.
PMC scratch register 41
25.03.2015 11:59, Tomeu Vizoso пишет:
As there isn't a way for the firmware on the Nyan chromebooks to hand
over the display to the kernel, and the kernel isn't redoing the whole
configuration at present.
With this patch, the SOR is brought to a known state and we get correct
display on every
23.01.2015 16:27, Dmitry Osipenko пишет:
23.01.2015 12:45, Thierry Reding пишет:
On Thu, Jan 22, 2015 at 08:18:34PM +0300, Dmitry Osipenko wrote:
22.01.2015 19:06, Dmitry Osipenko пишет:
22.01.2015 18:22, Dmitry Osipenko пишет:
22.01.2015 10:55, Alexandre Courbot пишет:
On Thu, Jan 22, 2015
Panel DPMS got broken after adding support for atomic modesetting.
Fix it by making RGB output use of generic atomic DPMS helpers.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
---
drivers/gpu/drm/tegra/rgb.c | 49 -
1 file changed, 17 insertions
of shutdown if reset wasn't defined. Fix it by
setting conn_id's in gpiod_lookup_table.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
Fixes: 72daceb (net: rfkill: gpio: Add default GPIO driver mappings for ACPI)
Cc: sta...@vger.kernel.org # v3.19+
---
arch/arm/mach-tegra/board-paz00.c | 4 ++--
1
MLOCK's debug info, spewed on CDMA timeout, contains meaningless MLOCK
owner channel ID because HOST1X_SYNC_MLOCK_OWNER_CHID_F() returns shifted
value, while unshifted should be used. Fix it by changing '_F' to '_V'.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
---
drivers/gpu/host1x/hw
30.06.2015 16:42, Alexandre Courbot пишет:
On Mon, Jun 29, 2015 at 4:34 AM, Dmitry Osipenko dig...@gmail.com wrote:
Commit 72daceb9a10a (net: rfkill: gpio: Add default GPIO driver mappings
for ACPI) removed possibility to request GPIO by table index for non-ACPI
platforms without changing
of shutdown if reset wasn't defined. Fix it by
making gpiod_lookup_table use con_id's instead of indexes.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
Fixes: 72daceb (net: rfkill: gpio: Add default GPIO driver mappings for ACPI)
Cc: sta...@vger.kernel.org # v3.19+
Acked-by: Alexandre Courbot
30.06.2015 17:15, Dmitry Osipenko пишет:
Commit 72daceb9a10a ("net: rfkill: gpio: Add default GPIO driver mappings
for ACPI") removed possibility to request GPIO by table index for non-ACPI
platforms without changing it users. As result "shutdown" GPIO request
will fail i
28.06.2015 22:27, Dmitry Osipenko пишет:
MLOCK's debug info, spewed on CDMA timeout, contains meaningless MLOCK
owner channel ID because HOST1X_SYNC_MLOCK_OWNER_CHID_F() returns shifted
value, while unshifted should be used. Fix it by changing '_F' to '_V'.
Signed-off-by: Dmitry Osipenko <
On 25.05.2016 18:09, Jon Hunter wrote:
On 05/05/16 15:24, Dmitry Osipenko wrote:
Hello, Jon!
On 05.05.2016 16:17, Jon Hunter wrote:
Thanks for the report. I have been unable to reproduce this, but then I
don't see my tegra20 entering LP2 during cpuidle. I did force my tegra20
into LP2
On 26.05.2016 17:32, Jon Hunter wrote:
On 26/05/16 12:42, Dmitry Osipenko wrote:
On 26.05.2016 11:42, Jon Hunter wrote:
On 25/05/16 19:51, Dmitry Osipenko wrote:
On 25.05.2016 18:09, Jon Hunter wrote:
...
If you are able to reproduce this on v3.18, then it would be good if
you
could
On 26.05.2016 18:27, Jon Hunter wrote:
On 26/05/16 15:57, Dmitry Osipenko wrote:
On 26.05.2016 17:32, Jon Hunter wrote:
On 26/05/16 12:42, Dmitry Osipenko wrote:
On 26.05.2016 11:42, Jon Hunter wrote:
On 25/05/16 19:51, Dmitry Osipenko wrote:
On 25.05.2016 18:09, Jon Hunter wrote
On 27.05.2016 15:46, Jon Hunter wrote:
On 26/05/16 18:01, Dmitry Osipenko wrote:
On 26.05.2016 18:27, Jon Hunter wrote:
On 26/05/16 15:57, Dmitry Osipenko wrote:
...
That's how I see it:
+--+
|CPU 0
On 26.05.2016 11:42, Jon Hunter wrote:
On 25/05/16 19:51, Dmitry Osipenko wrote:
On 25.05.2016 18:09, Jon Hunter wrote:
...
If you are able to reproduce this on v3.18, then it would be good if you
could trace the CCF calls around this WARNING to see what is causing the
contention.
I
Hello Sergei,
25.03.2016 14:12, Sergei Shtylyov пишет:
[snip]
udc = container_of(gadget, struct fsl_udc, gadget);
+udc->softconnect = (is_on != 0);
!!is_on? Parens not needed anyway though.
Okay :) I'll change to it in V2 as well as a bit messed up commit message.
Thanks
udc->softconnect should be set regardless of the VBUS state, otherwise
the USB peripheral device, connected during suspend, won't be detected
since can_pullup() would return false and the UDC won't be enabled.
Fixes: 252455c40316 (usb: gadget: fsl driver pullup fix)
Signed-off-by: Dmitry Osipe
udc->softconnect should be set regardless of the VBUS state, otherwise
the USB peripheral device, connected during suspend, won't be detected
since can_pullup() would return false the UDC controller won't be enabled.
Fixes: 252455c40316 (usb: gadget: fsl driver pullup fix)
Signed-off-by: Dmi
29.03.2016 13:31, Felipe Balbi пишет:
Dmitry Osipenko <dig...@gmail.com> writes:
udc->softconnect should be set regardless of the VBUS state, otherwise
the USB peripheral device, connected during suspend, won't be detected
since can_pullup() would return false and the UDC won't b
I forgot to mention that this is observed on 3.18 android kernel fork under a
quite specific condition: EMC scaling enabled and set to the lowest freq, CPU
max freq reduced. This may cause higher latency on CPU idle enter/exit.
I couldn't reproduce this issue with the upstream kernel, guess
Hello, Jon!
On 05.05.2016 16:17, Jon Hunter wrote:
Thanks for the report. I have been unable to reproduce this, but then I
don't see my tegra20 entering LP2 during cpuidle. I did force my tegra20
into LP2 during suspend which will exercise the same code but I did not
trigger this either.
) from []
(start_kernel+0x3b4/0x3c0)
[3.435557] [] (start_kernel) from [<8074>] (0x8074)
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
drivers/clk/tegra/clk-tegra-pmc.c | 9 +
drivers/soc/tegra/pmc.c | 2 +-
include/linux/clk/tegra.h | 2 ++
3 f
On 07.02.2017 20:22, Tobias Guggenmos wrote:
> Am Sonntag, 5. Februar 2017, 11:30:30 CET schrieb Larry Finger:
>> On 02/05/2017 05:34 AM, Dmitry Osipenko wrote:
>>> BTW, I have an issue with the 8192cu: WiFi stops to work after a while
>>> (3-15 minutes) if
On 07.02.2017 19:45, Tobias Guggenmos wrote:
> Am Montag, 6. Februar 2017, 09:45:31 CET schrieb Larry Finger:
>> On 02/06/2017 04:29 AM, Johannes Berg wrote:
>>> On Sat, 2017-02-04 at 12:41 -0600, Larry Finger wrote:
>>>> On 02/04/2017 10:58 AM, Dmitry Osipenko
On 05.02.2017 04:05, Larry Finger wrote:
> On 02/04/2017 01:32 PM, Dmitry Osipenko wrote:
>> On 04.02.2017 21:41, Larry Finger wrote:
>>> On 02/04/2017 10:58 AM, Dmitry Osipenko wrote:
>>>> Seems the problem is caused by rtl92c_dm_*() casting .priv to &qu
Hello,
I ran a 4.9.7 kernel with CONFIG_KASAN=y on my machine and it detected the
following problem:
[ 23.012238] rtl8192cu: MAC auto ON okay!
[ 23.045656] rtl8192cu: Tx queue select: 0x05
[ 23.541152]
==
[ 23.541160] BUG:
On 05.02.2017 20:30, Larry Finger wrote:
> On 02/05/2017 05:34 AM, Dmitry Osipenko wrote:
>> BTW, I have an issue with the 8192cu: WiFi stops to work after a while (3-15
>> minutes) if I enable WMM QoS on the AP. There is nothing suspicious in KMSG,
>> connection is up but no
Seems the problem is caused by rtl92c_dm_*() casting .priv to "struct
rtl_pci_priv", while it is "struct rtl_usb_priv".
--
Dmitry
On 04.02.2017 21:41, Larry Finger wrote:
> On 02/04/2017 10:58 AM, Dmitry Osipenko wrote:
>> Seems the problem is caused by rtl92c_dm_*() casting .priv to "struct
>> rtl_pci_priv", while it is "struct rtl_usb_priv".
>
> Those routines are shared by rtl8
address.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
drivers/gpu/drm/tegra/dc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index 39940f5..a98dd3e 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/g
On 06.09.2016 14:33, Jon Hunter wrote:
>
> On 03/09/16 01:32, Nicolin Chen wrote:
>> This series of patches add memcpy support for tegra210 ADMA engine.
>
> Thanks. Any reason you choose this DMA and not the APB DMA? The APB DMA
> is more of a generic DMA and so for memcpy it would seem to be a
On 06.09.2016 16:46, Jon Hunter wrote:
>
> On 06/09/16 14:04, Jon Hunter wrote:
>>
>> On 06/09/16 13:03, Dmitry Osipenko wrote:
>>> On 06.09.2016 14:33, Jon Hunter wrote:
>>>>
>>>> On 03/09/16 01:32, Nicolin Chen wrote:
>>>>>
Chromakey is a simple way of video overlay overlap implementation. This
patch adds 2 new IOCTL's: first - sets color key and is common across of
all Tegra SoC's, second - sets plane blending controls and allows to
utilize the color key, this one is exclusive to Tegra20/30.
Signed-off-by: Dmitry
On 02.09.2016 18:51, Thierry Reding wrote:
> On Fri, Sep 02, 2016 at 05:32:19PM +0200, Thierry Reding wrote:
>> On Fri, Sep 02, 2016 at 12:33:42PM +0300, Dmitry Osipenko wrote:
>>> Chromakey is a simple way of video overlay overlap implementation. This
>>> patch adds
tps6586x MFD spews hundreds of "failed to read interrupt status" KMSG's on
resume from suspend with eventual disablement of the IRQ when tps6586x's
RTC wakes the system. This happens because IRQ gets handled before I2C been
resumed.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com&
Overlay plane should be clipped, otherwise overlay output gets distorted
once plane crosses display boundary. As a "side effect" this patch also
adds a sanity check for the primary plane, insuring that it covers whole
display area.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com&
On 11.01.2017 04:53, Larry Finger wrote:
> On 01/10/2017 11:40 AM, Dmitry Osipenko wrote:
>> Hello, this patch causes a kernel panic with the rtl8192cu driver.
>>
>
> The fix is being merged into mainline. The reference is
> http://marc.info/?l=linux-wireless=1482340
n 10, 2017 at 08:40:28PM +0300, Dmitry Osipenko wrote:
>>>>> Hello, this patch causes a kernel panic with the rtl8192cu driver.
>>>>
>>>> Ick, not good! Does this cause a problem in Linus's tree as well?
>>>>
>>>
>>> http://
Hello, this patch causes a kernel panic with the rtl8192cu driver.
<6>[ 20.847025] IPv6: ADDRCONF(NETDEV_CHANGE): wlan0: link becomes ready
<1>[ 21.699551] BUG: unable to handle kernel NULL pointer dereference at
0048
<1>[ 21.699626] IP: [] rtl_lps_leave+0x13/0x40 [rtlwifi]
<4>[
-off-by: Joerg Roedel <jroe...@suse.de>
> ---
> drivers/iommu/tegra-gart.c | 26 ++
> 1 file changed, 26 insertions(+)
>
Reviewed-by: Dmitry Osipenko <dig...@gmail.com>
Tested-by: Dmitry Osipenko <dig...@gmail.com>
> diff --git a/dri
onsistency.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
include/linux/iommu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index 2cb54adc4a33..f1ce8e517d8d 100644
--- a/include/linux/iommu.h
+++ b/inclu
regressions
spotted on Tegra20.
Reviewed-by: Dmitry Osipenko <dig...@gmail.com>
Tested-by: Dmitry Osipenko <dig...@gmail.com>
--
Dmitry
parentheses.
>
> Fix these problems by using pr_cont to remove unnecessary newlines
> and by fixing other small issues.
>
> Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
> ---
It's indeed a bit more readable now.
Reviewed-by: Dmitry Osipenko <dig...@gmail.com>
Tested-by: Dmitry Osipenko <dig...@gmail.com>
--
Dmitry
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