phy-phandle is now a preferred method to reference a PHY device. The new
method also allows you to specify a reset gpio which is required for
this board.
Signed-off-by: Enric Balletbo i Serra
---
arch/arm/boot/dts/am335x-sl50.dts | 16 +---
1 file changed, 9 insertions(+), 7
Adopt the SPDX license identifier headers to ease license compliance
management.
Signed-off-by: Enric Balletbo i Serra
---
Changes in v3: None
Changes in v2: None
drivers/extcon/extcon-usbc-cros-ec.c | 20 +---
1 file changed, 5 insertions(+), 15 deletions(-)
diff --git
The license text is specifying "GPLv2" but the MODULE_LICENSE is set to
GPL which means GNU Public License v2 or later. When MODULE_LICENSE and
boiler plate does not match, go for boiler plate license.
Signed-off-by: Enric Balletbo i Serra
---
Changes in v3: None
Changes in v2: None
Adopt the SPDX license identifier headers to ease license compliance
management.
Signed-off-by: Enric Balletbo i Serra
---
Changes in v3: None
Changes in v2: None
drivers/input/keyboard/cros_ec_keyb.c | 34 ++-
1 file changed, 12 insertions(+), 22 deletions(-)
diff
and remove the boiler plate license text.
Signed-off-by: Enric Balletbo i Serra
---
arch/arm/boot/dts/am335x-igep0033.dtsi | 7 ++-
arch/arm/boot/dts/omap3-igep.dtsi| 6 ++
arch/arm/boot/dts/omap3-igep0020-common.dtsi | 5 +
arch/arm/boot/dts/omap3-igep0020-rev-f.dts
,
not the MIDAS displays.
Signed-off-by: Enric Balletbo i Serra
---
arch/arm/boot/dts/am335x-sl50.dts | 69 ++-
1 file changed, 68 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/am335x-sl50.dts
b/arch/arm/boot/dts/am335x-sl50.dts
index 58fe84f2ec8b
The board can be either a host, or a peripheral, so set the controller as
OTG mode to reflect this.
Signed-off-by: Enric Balletbo i Serra
---
arch/arm/boot/dts/am335x-sl50.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/am335x-sl50.dts
b/arch/arm/boot
:
- Removed '[PATCH 5/9] rtc: cros-ec: Switch to SPDX identifier' from
series as it was applied.
- s/Chrome OS/ChromeOS/
- [1/9] Fixed wrong copyright year.
- [6/9] Do not remove last paragraph.
- [8/9] Fixed wrong copyright year.
Enric Balletbo i Serra (12):
platform/chrome: Make license text
On 06/06/18 17:31, klaus.go...@theobroma-systems.com wrote:
> Hi Enric,
>
>> On 06.06.2018, at 17:21, Enric Balletbo i Serra
>> wrote:
>>
>> Adopt the SPDX license identifier headers to ease license compliance
>> management.
>
> [snip]
>
>
The cros-ec I2C and SPI transport drivers have been moved from MFD
subsystem to platform/chrome, at the same time, the config symbol has
been renamed and lost the MFD_ prefix, so update all configs to the new
config symbol name.
Signed-off-by: Enric Balletbo i Serra
---
arch/arm/configs
symbols, modifies the defconfigs that used these symbols and
fixes the KEYBOARD_CROS_EC Kconfig help.
Best regards,
Enric
Enric Balletbo i Serra (3):
platform/chrome: Move cros-ec transport drivers to drivers/platform.
arm/arm64: configs: Remove the MFD_ prefix for MFD_CROS_EC_I2C/SPI
The cros-ec I2C and SPI transport drivers have been moved from MFD
subsystem to platform/chrome, at the same time, the config symbol
has been renamed and lost the MFD_ prefix So, update the help message
accordingly.
Signed-off-by: Enric Balletbo i Serra
---
drivers/input/keyboard/Kconfig | 2
symbols.
Signed-off-by: Enric Balletbo i Serra
---
drivers/mfd/Kconfig | 20 ---
drivers/mfd/Makefile | 2 --
drivers/platform/chrome/Kconfig | 20 +++
drivers/platform/chrome/Makefile
Hi Grek,
On 25/06/18 03:57, Greg KH wrote:
> On Tue, Jun 05, 2018 at 08:14:24PM +0200, Enric Balletbo i Serra wrote:
>> Hi Fabio,
>>
>> On 05/06/18 20:04, Fabio Estevam wrote:
>>> Hi Enric,
>>>
>>> On Tue, Jun 5, 2018 at 2:54 PM, Enric Balletbo
Hi Dmitry,
I think I can answer some of your questions (not all).
cc'ing the new Thierry's address and Gwendal.
On 21/06/18 01:05, Dmitry Torokhov wrote:
> On Mon, Nov 20, 2017 at 8:18 AM Thierry Escande
> wrote:
>>
>> The cros_ec_dev module is responsible for registering the MFD devices
>>
From: Sameer Nanda <sna...@chromium.org>
This driver gets various bits of information about what is connected to
USB PD ports from the EC and converts that into power_supply properties.
Signed-off-by: Sameer Nanda <sna...@chromium.org>
Signed-off-by: Enric Balletbo i Serra
log functionality (will be send on a follow up patch)
- [2/3] Removed the extra custom sysfs attributes (will be send on a follow up
patch)
- [3/3] Use ARRAY_SIZE instead of hardcoded 1.
Enric Balletbo i Serra (1):
mfd: cros_ec_dev: Register cros_usbpd-charger driver as a subdevice.
Sameer Nanda
From: Sameer Nanda <sna...@chromium.org>
The USBPD charger driver gets information from the ChromeOS EC, this
patch adds the USBPD charger definitions needed by this driver.
Signed-off-by: Sameer Nanda <sna...@chromium.org>
Signed-off-by: Enric Balletbo i Serra <enric.balle..
Check whether this EC instance has USBPD host command support and
instatiate the cros_usbpd-charger driver as a subdevice in such case.
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes in v3: None
Changes in v2:
- [3/3] Use ARRAY_SIZE instead of hardc
Hi Lee,
Thanks for the reviews.
On 01/05/18 10:29, Lee Jones wrote:
> On Mon, 30 Apr 2018, Enric Balletbo i Serra wrote:
>
>> From: Sameer Nanda <sna...@chromium.org>
>>
>> The USBPD charger driver gets information from the ChromeOS EC, this
>> patch adds
Hi Lee,
On 01/05/18 10:32, Lee Jones wrote:
> On Mon, 30 Apr 2018, Enric Balletbo i Serra wrote:
>
>> Check whether this EC instance has USBPD host command support and
>> instatiate the cros_usbpd-charger driver as a subdevice in such case.
>>
>> Signed-
From: Sameer Nanda <sna...@chromium.org>
This driver gets various bits of information about what is connected to
USB PD ports from the EC and converts that into power_supply properties.
Signed-off-by: Sameer Nanda <sna...@chromium.org>
Signed-off-by: Enric Balletbo i Serra
d SPDX header, use devm_ variant and drop .owner
- [2/3] Removed the PD log functionality (will be send on a follow up patch)
- [2/3] Removed the extra custom sysfs attributes (will be send on a follow up
patch)
- [3/3] Use ARRAY_SIZE instead of hardcoded 1.
Enric Balletbo i Serra (1):
mfd: cros_
Check whether this EC instance has USBPD host command support and
instatiate the cros_usbpd-charger driver as a subdevice in such case.
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- [3/3] Use ARRAY_SIZE i
Hi Sebastian,
On 02/05/18 12:57, Sebastian Reichel wrote:
> Hi,
>
> I found one more issue, otherwise the driver looks fine to me.
>
> On Wed, May 02, 2018 at 11:53:42AM +0200, Enric Balletbo i Serra wrote:
>> This driver gets various bits of information about what is c
From: Sameer Nanda <sna...@chromium.org>
The USBPD charger driver gets information from the ChromeOS EC, this
patch adds the USBPD charger definitions needed by this driver.
Signed-off-by: Sameer Nanda <sna...@chromium.org>
Signed-off-by: Enric Balletbo i Serra <enric.balle..
Hi Rob,
Thanks for the review.
On 27/04/18 22:00, Rob Herring wrote:
> On Tue, Apr 24, 2018 at 10:37:41AM +0200, Enric Balletbo i Serra wrote:
>> In ATF we already wait for DDR dvfs finish, so don't need to do this in
>> kernel, so remove the interrupts properties as is not
From: Sameer Nanda <sna...@chromium.org>
This driver gets various bits of information about what is connected to
USB PD ports from the EC and converts that into power_supply properties.
Signed-off-by: Sameer Nanda <sna...@chromium.org>
Signed-off-by: Enric Balletbo i Serra
:
- [2/3] Add SPDX header, use devm_ variant and drop .owner
- [2/3] Removed the PD log functionality (will be send on a follow up patch)
- [2/3] Removed the extra custom sysfs attributes (will be send on a follow up
patch)
- [3/3] Use ARRAY_SIZE instead of hardcoded 1.
Enric Balletbo i Serra (1
From: Sameer Nanda <sna...@chromium.org>
The USBPD charger driver gets information from the ChromeOS EC, this
patch adds the USBPD charger definitions needed by this driver.
Signed-off-by: Sameer Nanda <sna...@chromium.org>
Signed-off-by: Enric Balletbo i Serra <enric.balle..
Check whether this EC instance has USBPD host command support and
instatiate the cros_usbpd-charger driver as a subdevice in such case.
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes in v2:
- [3/3] Use ARRAY_SIZE instead of hardcoded 1.
drive
Hi MyungJoo
On 03/07/18 12:57, MyungJoo Ham wrote:
>> @@ -988,12 +1030,13 @@ static ssize_t governor_store(struct device *dev,
>> struct device_attribute *attr,
>> if (ret != 1)
>> return -EINVAL;
>>
>> -mutex_lock(_list_lock);
>> -governor =
/ devfreq: map devfreq drivers to governor using name)
Signed-off-by: Enric Balletbo i Serra
---
Changes in v4:
- Kept "locked" devfreq_list from the return of find_devfreq_governor() to
the unlock of governor_store(). Requested by MyungJoo Ham.
Changes in v3:
- Remove unne
<0 4 8 12 16 20 ... 4096 4156 4216 4276 ... 65535>
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes since RFCv2:
- Replace use-linear-interpolation for num-interpolated-steps so it's
more flexible to specify any kind of curve to the user.
- Rework
The patch 'backlight: pwm_bl: compute brightness of LED linearly to
human eye' introduced a default brightness-levels table that is used
when brightness-levels is not availablel in the dts so move move
brightness-levels and default-brightness-level to be optional.
Signed-off-by: Enric Balletbo i
The num-interpolated-steps property specifies the number of
interpolated steps between each value of brightness-level table. This is
useful for high resolution PWMs to not have to list out every possible
value in the brightness-level array.
Signed-off-by: Enric Balletbo i Serra <enric.ba
based on the PWM resolution.
The calculation of the table using the CIE 1931 algorithm is enabled by
default when you do not define the 'brightness-levels' propriety in your
device tree.
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes since RFCv2:
- Pre-c
[2] https://lkml.org/lkml/2017/11/16/301
Best regards,
Enric Balletbo i Serra (4):
backlight: pwm_bl: linear interpolation between brightness-levels
dt-bindings: pwm-backlight: add a num-interpolation-steps property.
backlight: pwm_bl: compute brightness of LED linearly to human eye.
dt
Dear all,
These patches introduces the ChromeOS EC USBPD charger driver, the
driver has been used on Chromebooks kernels and ported to mainline. The
patches were tested succesfully with a Samsung Chromebook Plus device
but depends on the for-next Benson Leung branch [1] to apply cleanly.
This
From: Sameer Nanda <sna...@chromium.org>
This driver gets various bits of information about what is connected to
USB PD ports from the EC and converts that into power_supply properties.
Signed-off-by: Sameer Nanda <sna...@chromium.org>
Signed-off-by: Enric Balletbo i Serra
From: Sameer Nanda <sna...@chromium.org>
Check whether this EC instance has USBPD host command support and
instatiate the cros_usbpd-charger driver as a subdevice in such case.
Signed-off-by: Sameer Nanda <sna...@chromium.org>
Signed-off-by: Enric Balletbo i Serra <enric.balle..
From: Sameer Nanda <sna...@chromium.org>
The USB PD charger driver gets information from the ChromeOS EC, this
patch adds the USBPD charger definitions needed by this driver.
Signed-off-by: Sameer Nanda <sna...@chromium.org>
Signed-off-by: Enric Balletbo i Serra <enric.balle..
;
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Hi,
This is an attempt to revive a patch [1] that was sent last October. Sean
Paul requested some changes but I think that never was send a v5 version.
The patch fixes and issue where backlight panel is not correctly reco
Hi Jeffy,
On 12/02/18 23:13, Brian Norris wrote:
> Hi Jeffy,
>
> On Sat, Feb 10, 2018 at 07:09:05PM +0800, Jeffy Chen wrote:
>> Add support for specifying event actions to trigger wakeup when using
>> the gpio-keys input device as a wakeup source.
>>
>> This would allow the device to configure
Hi Heiko,
On 10/02/18 17:16, Heiko Stuebner wrote:
> Hi Enric,
>
> Am Mittwoch, 7. Februar 2018, 17:31:49 CET schrieb Enric Balletbo i Serra:
>> From: Chris Zhong <z...@rock-chips.com>
>>
>> Add a node for the cdn DP controller which is embedded in the rk3399
&
From: Chris Zhong <z...@rock-chips.com>
Enable cdn_dp and create a cdn-dp-sound for the DP audio. Delete the
endpoints between dp and vopL for gru, since we want the DP only use
VOP big, which can support 4K mode.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Signed-off-by: Enri
From: Chris Zhong <z...@rock-chips.com>
This patch adds a binding that describes the cdn DP controller for
rk3399.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com&
From: Chris Zhong <z...@rock-chips.com>
Add a node for the cdn DP controller which is embedded in the rk3399
SoC.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes since v1:
- None
arch/arm64
Hence move
this switch to PHY driver, the PHY driver can distinguish between PHY 0
and PHY 1, and then write the correct register bit.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes since v1:
-
clear this bit means enable PHY 0.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes since v1:
- This patch is new on these series but as a consequence of the work
done need to be reworked. The patch was sen
should
clear the usb3tousb2 bit before pipe ready. So let's enable the usb3
host after pipe ready to avoid the Type-C PHY initialization failure.
Signed-off-by: William wu <w...@rock-chips.com>
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes since v1:
-
-c force usb3 to usb2
enable control.
- rockchip,external-psm : the register of type-c phy external psm clock
selection.
- rockchip,pipe-status : the register of type-c phy pipe status.
Signed-off-by: Enric Balletbo i Serra <enric.ba
3 mode, when USB disconnect.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes since v1:
- Use the registers offsets from the driver not the DT.
drivers/phy/rockchip/phy-rockchip-typec.c | 21 +++
cks the phy base address of the running
instance and applies the right offsets.
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes since v1:
- This patch is new in this series to accomplish the purpose of get rid
of some registers from the DT. Suggested by Rob Her
based on the PWM resolution.
The calculation of the table using the CIE 1931 algorithm is enabled by
default when you do not define the 'brightness-levels' propriety in your
device tree.
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes since v2:
- None
Changes
detailed info is available in the commit message of every patch.
Both functionalities were tested on a Samsung Chromebook Plus (that has
a 16 bits PWM) and a SL50 device (with a 8 bits PWM)
Waiting for your feedback.
Best regards,
Enric Balletbo i Serra (4):
backlight: pwm_bl: linear
The patch 'backlight: pwm_bl: compute brightness of LED linearly to
human eye' introduced a default brightness-levels table that is used
when brightness-levels is not available in the dts. So move
brightness-levels and default-brightness-level to be optional.
Signed-off-by: Enric Balletbo i Serra
<0 4 8 12 16 20 ... 4096 4156 4216 4276 ... 65535>
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes since v2:
Requested by Daniel Thompson:
- Use a devres alloc for table creatiion and then just swap pointers.
- No need to use calloc because the lo
The num-interpolated-steps property specifies the number of
interpolated steps between each value of brightness-level table. This is
useful for high resolution PWMs to not have to list out every possible
value in the brightness-level array.
Signed-off-by: Enric Balletbo i Serra <enric.ba
From: William wu <w...@rock-chips.com>
rockchip,usb3-host-disable is the register of type-c phy disable usb3 host
rockchip,usb3-host-port is the register of type-c phy usb3 port number
Signed-off-by: William wu <w...@rock-chips.com>
Signed-off-by: Enric Balletbo i Serra
should
clear the usb3tousb2 bit before pipe ready. So let's enable the usb3
host after pipe ready to avoid the Type-C PHY initialization failure.
Signed-off-by: William wu <w...@rock-chips.com>
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
arch/arm64/boot/dts/ro
3 mode, when USB disconnect.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-typec.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/dr
<0 4 8 12 16 20 ... 4096 4156 4216 4276 ... 65535>
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes since v1:
- None.
drivers/video/backlight/pwm_bl.c | 86
1 file changed, 86 insertions(+)
diff --git a/driv
detailed info is available in the commit message of every patch.
Both functionalities were tested on a Samsung Chromebook Plus (that has
a 16 bits PWM) and a SL50 device (with a 8 bits PWM)
Waiting for your feedback.
Best regards,
Enric Balletbo i Serra (4):
backlight: pwm_bl: linear
The patch 'backlight: pwm_bl: compute brightness of LED linearly to
human eye' introduced a default brightness-levels table that is used
when brightness-levels is not available in the dts. So move
brightness-levels and default-brightness-level to be optional.
Signed-off-by: Enric Balletbo i Serra
The num-interpolated-steps property specifies the number of
interpolated steps between each value of brightness-level table. This is
useful for high resolution PWMs to not have to list out every possible
value in the brightness-level array.
Signed-off-by: Enric Balletbo i Serra <enric.ba
based on the PWM resolution.
The calculation of the table using the CIE 1931 algorithm is enabled by
default when you do not define the 'brightness-levels' propriety in your
device tree.
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes since v1:
- Fix an ho
isplay after a
suspend/resume with following errors:
rockchip-dp ff97.edp: Input stream clock not detected.
rockchip-dp ff97.edp: Timeout of video streamclk ok
rockchip-dp ff97.edp: unable to config video
Signed-off-by: Yakir Yang <y...@rock-chips.com>
Signed-off-by: Enri
From: Chris Zhong <z...@rock-chips.com>
Enable cdn_dp and create a cdn-dp-sound for the DP audio. Delete the
endpoints between dp and vopL for gru, since we want the DP only use
VOP big, which can support 4K mode.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Signed-off-by: Enri
From: Chris Zhong <z...@rock-chips.com>
Add a node for the cdn DP controller which is embedded in the rk3399
SoC.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
arch/arm64/boot/dts/rockchi
3 mode, when USB disconnect.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes since v2:
- None.
Changes since v1:
- Use the registers offsets from the driver not the DT.
drivers/phy/rockchip/phy-roc
should
clear the usb3tousb2 bit before pipe ready. So let's enable the usb3
host after pipe ready to avoid the Type-C PHY initialization failure.
Signed-off-by: William wu <w...@rock-chips.com>
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes since v2:
- None
Hence move
this switch to PHY driver, the PHY driver can distinguish between PHY 0
and PHY 1, and then write the correct register bit.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes since v2:
- None
cks the phy base address of the running
instance and applies the right offsets.
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes since v2:
- Suggested by Heiko Stuebner:
- Prefix phy config struct with rk3399_ as is rk3399-specific.
- Create a new struct s
clear this bit means enable PHY 0.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes since v2:
- None.
Changes since v1:
- This patch is new on these series but as a consequence of the work
done need to be r
-c force usb3 to usb2
enable control.
- rockchip,external-psm : the register of type-c phy external psm clock
selection.
- rockchip,pipe-status : the register of type-c phy pipe status.
Signed-off-by: Enric Balletbo i Serra <enric.ba
Hi,
This patchset is another recopilation of some patches that were send
before but never merged.
First patch was already sent [1] but did not receive feedback so I am
resending it. Needs to go throught platform/chrome tree and can be
picked without dependencies.
The second patch is new, like
From: Shawn Nematbakhsh <sha...@chromium.org>
Add info useful for debugging USB-PD port state.
Signed-off-by: Shawn Nematbakhsh <sha...@chromium.org>
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
drivers/platform/chrome/cros
check before the device is
added so the features map obtained from the EC is ready on time.
Signed-off-by: Gwendal Grignou <gwen...@chromium.org>
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
drivers/mfd/cros_ec_dev.c | 19
drive
status() instead of
cros_ec_cmd_xfer() so an error message is printed in the syslog.
Signed-off-by: Gwendal Grignou <gwen...@chromium.org>
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
drivers/platform/chrome/cros_ec_sysfs.c | 25 -
Hi Gwendal,
On 22/02/18 03:20, Gwendal Grignou wrote:
> On Mon, Feb 19, 2018 at 2:41 PM, Enric Balletbo i Serra
> <enric.balle...@collabora.com> wrote:
>> From: Gwendal Grignou <gwen...@chromium.org>
> This patch is not needed anymore. It was added to
>>
>>
is this delay in milli seconds.
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
Acked-by: Pavel Machek <pa...@ucw.cz>
---
Based on the original Huang Lin <h...@rock-chips.com> work.
Changes since v4:
- Rebase on top of mainline.
Changes since v3:
- Replace us fo
.
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
Acked-by: Pavel Machek <pa...@ucw.cz>
Acked-by: Daniel Thompson <daniel.thomp...@linaro.org>
Acked-by: Jingoo Han <jingooh...@gmail.com>
---
Changes since v4:
- Rebased on top of mainline.
- Added th
The minnie devices comes with an AUO B101EAN01 panel which is different
from default veyron devices, thus the power on/off timing sequence is
slightly different. The datasheet specifies a pwm delay of 200 ms, so
update the PMW delay proprieties accordingly.
Signed-off-by: Enric Balletbo i Serra
a symmetric power sequence, hence the same value is used.
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
Acked-by: Pavel Machek <pa...@ucw.cz>
---
Changes since v4:
- Rebased on top of mainline.
Changes since v3:
- Use new -ms names for proprieties.
Changes since v2
:
- N133HSE-EA1 (Innolux)
- N116BGE (Innolux)
- N156BGE-L21 (Innolux)
- B101EAN0 (Auo)
- B101AW03 (Auo)
- LTN101NT05 (Samsung)
- CLAA101WA01A (Chunghwa)
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
Acked-by: Daniel Thompson <daniel.thomp...@linaro.o
ed-off-by: Daniel Hung-yu Wu <h...@chromium.org>
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes in v2:
- [6/8] This patch is new in this series.
drivers/mfd/cros_ec_dev.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/mfd/cros_ec_d
-by Gwendal.
- [8/8] This patch is new in this series replacing [5/6] of v1.
Daniel Hung-yu Wu (1):
mfd: cros_ec_dev: register shutdown function for debugfs
Douglas Anderson (1):
mfd: cros_ec: Don't try to grab log when suspended
Enric Balletbo i Serra (1):
mfd: cros_ec_dev: Register cros-ec
needs to be resumed earlier
due to some status polling from the EC FW (e.g. battery status). So we
move the PM ops to late stage to make it work normally.
Signed-off-by: Joseph Lo <jose...@nvidia.com>
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Cha
From: Wei-Ning Huang <wnhu...@google.com>
Add ACPI module device table for matching cros-ec devices to load the
cros_ec_i2c driver automatically.
Signed-off-by: Wei-Ning Huang <wnhu...@google.com>
Acked-by: Benson Leung <ble...@chromium.org>
Signed-off-by: Enric Balletbo i
deprecated EC commands (Glimmer based devices).
Tested-by: Gwendal Grignou <gwen...@chromium.org>
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
Reviewed-by: Gwendal Grignou <gwen...@chromium.org>
---
Changes in v2:
- [5/8] Add the Reviewed-by Gwendal.
drivers/mfd/
Hi Andy,
On 21/02/18 16:16, Andy Shevchenko wrote:
> On Wed, Feb 21, 2018 at 4:50 PM, Enric Balletbo i Serra
> <enric.balle...@collabora.com> wrote:
>> From: Gwendal Grignou <gwen...@chromium.org>
>>
>> This adds a sysfs attribute (/sys/class/chromeos/cros_ec/k
Fixed the following checkpatch warning:
WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider
using octal permissions '0444'.
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes since v1:
- New in this series. Andy Shevchenko suggest
Add a define to get the cros_ec_dev from device and use it.
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes since v1:
- New in this series. Suggested by Andy Shevchenko.
drivers/platform/chrome/cros_ec_sysfs.c | 11 +--
1 file changed, 5 insertions
status() instead of
cros_ec_cmd_xfer() so an error message is printed in the syslog.
Signed-off-by: Gwendal Grignou <gwen...@chromium.org>
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes since v1:
- None
drivers/platform/chrome/cr
for the
pd feature and another one to use octal permissions.
Enric Balletbo i Serra (3):
platform/chrome: cros_ec_sysfs: introduce to_cros_ec_dev define.
platform/chrome: cros_ec_sysfs: use permission-specific DEVICE_ATTR
variants
platform/chrome: cros_ec_debugfs: Use octal permissions
check before the device is
added so the features map obtained from the EC is ready on time.
Signed-off-by: Gwendal Grignou <gwen...@chromium.org>
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes since v1:
- Suggested by Andy Shevchenko:
- Use th
From: Shawn Nematbakhsh <sha...@chromium.org>
Add info useful for debugging USB-PD port state.
Signed-off-by: Shawn Nematbakhsh <sha...@chromium.org>
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes since v1:
- Drop unrelated changes. Suggested
Use DEVICE_ATTR variants for read/write attributes. This simplifies the
source code, improves readbility, and reduces the chance of
inconsistencies.
Signed-off-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
---
Changes since v1:
- New in this series. Suggested by Andy Shev
-kernel@vger.kernel.org/msg1467253.html
Best regards,
Enric Balletbo i Serra (1):
mfd: cros_ec_dev: Register cros-ec-rtc driver as a subdevice.
Gwendal Grignou (1):
mfd: cros_ec_dev: Check communication with ec at resume
Thierry Escande (1):
mfd: cros_ec_dev: Register cros_ec_accel_legacy
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